Prosecution Insights
Last updated: August 16, 2026
Application No. 18/389,247

ENERGY SOURCE FOR MEMORY DEVICE

Final Rejection §102§103
Filed
Nov 14, 2023
Examiner
CRUM, GAGE STEPHEN
Art Unit
2841
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SMART Modular Technologies Inc.
OA Round
2 (Final)
57%
Grant Probability
Moderate
3-4
OA Rounds
0m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 57% of resolved cases
57%
Career Allowance Rate
105 granted / 185 resolved
-11.2% vs TC avg
Strong +31% interview lift
Without
With
+31.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
32 currently pending
Career history
222
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
58.1%
+18.1% vs TC avg
§102
24.8%
-15.2% vs TC avg
§112
16.2%
-23.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 185 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-2, and 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kano (US 20150022718 A1, and hereinafter “Kano”). Regarding claim 1, Kano teaches a memory device (Fig. 1, 7, Abstract : image pickup apparatus with memory 41) comprising: a housing (Fig. 1, 7, [0059] : camera body 4); a primary portion a housing (Fig. 1, 27, 30, [0162], [0173] : main board unit 3) positioned within the housing (Fig. 1, 27, 30, [0162], [0173] : main board unit 3 is positioned within camera body 4), the primary portion comprising at least one memory element (Fig. 1, 7, 27, 30, [0162], [0173] : main board unit 3 comprises memory 4f); and a detachable portion (Fig. 1, 7, 24, 27, 30, [0154-0167], [0173] : battery 60) selectively coupled to the primary portion (Fig. 1, 7, 24, 27, 30, [0154-0167], [0173] : battery 60 connects to main board 3), and when coupled to the primary portion, the detachable portion is positioned within the housing (Fig. 1, 7, 24, 27, 30, [0154-0167], [0173] : when battery 60 couples to main board 3, battery 60 is positioned within camera body 4), and when the detachable portion is detached from the primary portion, the detachable portion may be removed from the housing (Fig. 1, 7, 24, 27, 30, [0154-0167], [0173] : when battery 60 is disconnected from the main board 3, battery 60 may be removed from camera body 4). Regarding claim 2, Kano teaches the memory device of claim 1, further comprising an energy source module (ESM) positioned on the detachable portion (Fig. 1, 7, 24, 27, 30, [0154-0167], [0173] : battery 60). Regarding claim 11, Kano teaches the memory device of claim 2, further comprising a lever (Fig. 1, 7, 24, 27, 30, [0154-0167], [0173] : lever 65) coupled to the detachable portion (Fig. 1, 7, 24, 27, 30, [0154-0167], [0173] : lever 65 is coupled to the battery box 61 and batter 60), wherein the lever is configured to open and provide a handle with which to detach the detachable portion from the primary portion (Fig. 1, 7, 24, 27, 30, [0154-0167], [0173] : lever 65 is used as a handle to detach the battery 60 from the main board unit 3). Regarding claim 12, Kano teaches the memory device of claim 2, further comprising a spring mechanism to eject the detachable portion (Fig. 1, 7, 24, 27, 30, [0154-0167], [0173] : ejection spring 66 pushes battery 60 out of battery box 61). Claim(s) 1-2, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Douglas (US 7414854 B1, and hereinafter “Douglas”). Regarding claim 1, Douglas teaches a memory device (Fig. 3-4, Abstract : a system with a cache) comprising: a housing (Fig. 3-4, Col. 9, Lines 45-63 : case housing the boards 410 and 430); a primary portion (Fig. 3-4, Col. 9, Lines 45-63 : board 430) positioned within the housing (Fig. 3-4, Col. 9, Lines 45-63 : board 430 is housed within the case), the primary portion comprising at least one memory element (Fig. 3-4, Col. 9, Lines 45-67, Col. 10, Lines 1-9 : board 430 comprises a cache 438); and a detachable portion (Fig. 3-4, Col. 9, Lines 45-67, Col. 10, Lines 1-9 : module 450) selectively coupled to the primary portion (Fig. 3-4, Col. 9, Lines 45-67, Col. 10, Lines 1-9 : module 450 connects to the board 410 and board 430), and when coupled to the primary portion, the detachable portion is positioned within the housing (Fig. 3-4, Col. 9, Lines 45-67, Col. 10, Lines 1-9 : when module 450 connects to the board 410 and 430, the module 450 is within the case), and when the detachable portion is detached from the primary portion, the detachable portion may be removed from the housing (Fig. 3-4, Col. 9, Lines 45-67, Col. 10, Lines 1-9 : when module 450 is disconnected from the board 410 and 430, module 450 can be removed from the case). Regarding claim 2, Douglas teaches the memory device of claim 1, further comprising an energy source module (ESM) (Fig. 3-4, Col. 9, Lines 45-67, Col. 10, Lines 1-9 : module 450 is a battery module) positioned on the detachable portion (Fig. 3-4, Col. 9, Lines 45-67, Col. 10, Lines 1-9 : module 450 is a battery module). Regarding claim 13, Douglas teaches the memory device of claim 2, further comprising a button (Fig. 3-4, Col. 9, Lines 45-67, Col. 10, Lines 1-9 : release button 416) coupled to a lever (Fig. 3-4, Col. 8, Lines 27-50, Col. 9, Lines 45-67, Col. 10, Lines 1-9 : release button 332/416 is coupled to the ejection arm 338) configured to push the detachable portion out of the housing (Fig. 3-4, Col. 8, Lines 27-50, Col. 9, Lines 45-67, Col. 10, Lines 1-9 : when the release button 332/416 is pressed, the ejection arm ejects the battery module 450 out of the case). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-2, and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Wyler (US 5596483 A, hereinafter “Wyler”), in view of Yoo (US 20130016484 A1, and hereinafter “Yoo”). Regarding claim 1, Wyler teaches a memory device (Fig. 1-3, Abstract, Col. 4, Lines 18-29 : a computer with a disk drive 36) comprising: a housing (Fig. 1-3, Col. 3, Lines 3-30, Col. 4, Lines 18-29 : housing 10); a primary portion (Fig. 1-3, Col. 3, Lines 3-30, Col. 4, Lines 18-29, Col. 5, Lines 13-33 : metal chassis 52) positioned within the housing (Fig. 1-3, Col. 3, Lines 3-30, Col. 4, Lines 18-29, Col. 5, Lines 13-33 : metal chassis 52 is positioned within housing 10), the primary portion comprising at least one memory element (Fig. 1-3, Col. 3, Lines 3-30, Col. 4, Lines 18-29, Col. 5, Lines 13-33 : metal chassis 52 comprises a disk drive 36); and a portion (Fig. 1-3, Col. 3, Lines 3-30, Col. 4, Lines 18-29, Col. 5, Lines 13-33, Claim 1 : power supply 46) selectively coupled to the primary portion (Fig. 1-3, Col. 3, Lines 3-30, Col. 4, Lines 18-29, Col. 5, Lines 13-33, Claim 1 : power supply 46 powers the board 25 and 28, and are connected to them), and when coupled to the primary portion, the portion is positioned within the housing (Fig. 1-3, Col. 3, Lines 3-30, Col. 4, Lines 18-29, Col. 5, Lines 13-33, Claim 1 : when power supply 46, the power supply 46 is within the housing 10). Wyler does not teach a detachable portion, and when the detachable portion is detached from the primary portion, the detachable portion may be removed from the housing. However, Yoo teaches a detachable portion, and when the detachable portion (Fig. 1, 4, [0110] : power supply unit 190 is detachably mounted to a terminal body, and electrically connected to a PCB 220) is detached from the primary portion, the detachable portion may be removed from the housing (Fig. 1, 4, [0110] : when power supply unit 190 is detached from the PCB 220, it can be removed from the terminal body). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to incorporate detachable portion as taught by Yoo into Wyler’s memory device. The suggestion / motivation for doing so would be to provide ease of maintenance and upgrade of the device . Additionally, having detachable components for providing ease of maintenance and upgrade is known as evidence by Wyler (Col. 5, Lines 13-33). Regarding claim 2, Wyler as modified by Yoo teaches the memory device of claim 1, further comprising an energy source module (ESM) positioned on the detachable portion (Fig. 1-3, Col. 3, Lines 3-30, Col. 4, Lines 18-29, Col. 5, Lines 13-33, Claim 1 of Wyler, and Fig. 1, 4, [0110] of Yoo : power supply 46 is detachable). Regarding claim 8, Wyler as modified by Yoo teaches the memory device of claim 2, wherein the housing comprises a face (Fig. 1-3, Col. 3, Lines 3-30, Col. 4, Lines 18-29, Col. 5, Lines 13-33, Claim 1 of Wyler : front and upper face of housing 10) through which the detachable portion may be removed (Fig. 1-3, Col. 3, Lines 3-30, Col. 4, Lines 18-29, Col. 5, Lines 13-33, Claim 1 of Wyler, and Fig. 1, 4, [0110] of Yoo : power supply 46 is detachable, and can removed through front and upper face of housing 10). Regarding claim 9, Wyler as modified by Yoo teaches the memory device of claim 8, wherein the primary portion extends across part of a lateral axis of the face (Fig. 1-3, Col. 3, Lines 3-30, Col. 4, Lines 18-29, Col. 5, Lines 13-33, Claim 1 of Wyler : metal chassis 52 extends across part of a lateral axis of the front face of housing 10). Regarding claim 10, Wyler as modified by Yoo teaches the memory device of claim 8, wherein the detachable portion extends across substantially all of a lateral axis of the face and extends across part of a longitudinal axis of the housing (Fig. 1-3, Col. 3, Lines 3-30, Col. 4, Lines 18-29, Col. 5, Lines 13-33, Claim 1 of Wyler : power supply 46 extends across substantially all of a lateral axis of the front face of housing 10, and extends across part of a longitudinal axis of the housing 10). Claim(s) 3, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Wyler and Yoo combination as applied above, in view of Brown et al. (US 20230031359 A1, and hereinafter “Brown”). Regarding claim 3, Wyler as modified by Yoo teaches the memory device of claim 2. Wyler as modified by Yoo does not teach wherein the ESM comprises a battery. However, Brown teaches wherein the ESM comprises a battery (Fig. 1, [0027] : power supply 152 can be a power supplied from a power plant to a building, a battery, a capacitor, and etc.). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to incorporate a battery as taught by Brown into Wyler and Yoo combination’s memory device by using a battery as a power supply. The suggestion / motivation for doing so would be to provide power to the computer. Additionally, using a battery as a power supply in information handling system is known as evidence by Brown ([0027]). Regarding claim 15, Wyler as modified by Yoo teaches the memory device of claim 2. Wyler as modified by Yoo does not teach wherein the ESM comprises either a capacitor or a hybrid capacitor. However, Brown teaches wherein the ESM comprises either a capacitor or a hybrid capacitor (Fig. 1, [0027] : power supply 152 can be a power supplied from a power plant to a building, a battery, a capacitor, and etc.). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to incorporate a capacitor as taught by Brown into Wyler and Yoo combination’s memory device by using a capacitor as a power supply. The suggestion / motivation for doing so would be to provide power to the computer. Additionally, using a capacitor as a power supply in information handling system is known as evidence by Brown ([0027]). Claim(s) 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Wyler and Yoo combination as applied above, in view of Gieski (US 20230163528 A1, and hereinafter “Gieski”). Regarding claim 4, Wyler as modified by Yoo teaches the memory device of claim 2. Wyler as modified by Yoo does not teach wherein the primary portion comprises a first connector and the detachable portion comprises a second connector, the first connector, and the second connector configured to mate and form electrical connections therethrough. However, Gieski teaches wherein the primary portion (Fig. 3, [0052] : PCB 480) comprises a first connector (Fig. 3, [0052] : mating interface 410) and the detachable portion (Fig. 3, [0052] : PSU 470) comprises a second connector (Fig. 3, [0052] : slot 412), the first connector, and the second connector configured to mate and form electrical connections therethrough (Fig. 3, [0052] : mating interface 410 and slot 412 are configured to mate and form electrical connections). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to incorporate the first connector and second connector as taught by Gieski into Wyler and Yoo combination’s memory device by adding the mating interface and the slot to the board and the power supply. The suggestion / motivation for doing so would be to enable electronic assemblies to be efficiently configured for any of multiple power requirements (Abstract of Gieski). Regarding claim 5, Wyler and Yoo combination as modified by Wyler teaches the memory device of claim 4, wherein the primary portion is L-shaped (Fig. 1-3, Col. 3, Lines 3-30, Col. 4, Lines 18-29, Col. 5, Lines 13-33, Claim 1 of Wyler, and Fig. 3, [0052] of Gieski : PCB 480 is L-shaped), and the detachable portion is shaped to fit within an angle of the L (Fig. 1-3, Col. 3, Lines 3-30, Col. 4, Lines 18-29, Col. 5, Lines 13-33, Claim 1 of Wyler, and Fig. 3, [0052] of Gieski : power supply 46 and PSU 470 are shaped to fit within an angle of the board 25/28 and PCB 480). Regarding claim 6, Wyler and Yoo combination as modified by Gieski teaches the memory device of claim 5, wherein the first connector is on a short side of the L (Fig. 1-3, Col. 3, Lines 3-30, Col. 4, Lines 18-29, Col. 5, Lines 13-33, Claim 1 of Wyler, and Fig. 3, [0052] of Gieski : mating interface 410 is on a short side of the L) Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Wyler, Yoo, and Gieski combination as applied above, in view of Harris (US 6328598 B1, and hereinafter “Harris”). Regarding claim 7, Wyler and Yoo combination as modified by Gieski teaches the memory device of claim 5. Wyler and Yoo combination as modified by Gieski does not teach wherein the first connector is on a long side of the L. However, Harris teaches wherein the first connector (Fig. 2, Col. 3, Lines 39-61 : ribbon connector 18) is on a long side of the L (Fig. 2, Col. 3, Lines 39-61 : ribbon connector 18 is on a long side of the L of main board portion 12). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to incorporate the first connector on a long side of the L as taught by Harris into Wyler, Yoo, and Gieski combination’s memory device by moving the mating interface and the slot to the long side of the L of the board. The suggestion / motivation for doing so would be to establish an electrical connection, and minimize the damage on the connector through utilizing a flexible connector. Additionally, the Wyler and Yoo combination as modified by Gieski discloses the claimed invention except for the first connector is on a long side of the L. It would have been obvious to one having ordinary skill in the art, before the effective filing date, to move the location of the first connector to the long side of the L, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Wyler and Yoo combination as applied above, in view of Ikeda et al. (US 20160131721 A1, and hereinafter “Ikeda”). Regarding claim 14, Wyler as modified by Yoo teaches the memory device of claim 2. Wyler as modified by Yoo does not teach further comprising a light-emitting diode (LED) coupled to the ESM and configured to provide an indication of ESM health. However, Ikeda teaches further comprising a light-emitting diode (LED) coupled to the ESM and configured to provide an indication of ESM health (Fig. 1-3, [0035] : indicator 40, which can be an LED, is configured to provide the state of the internal power supply 24). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to incorporate the light-emitting diode (LED) as taught by Ikeda into Wyler and Yoo combination’s memory device by adding the indicator on the housing and/or the metal chassis. The suggestion / motivation for doing so would be to notify the user the status of the energy source module, and allow the user to perform preventative maintenance ([0128] of Ikeda). Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over Fleisher et al. (US 11288122 B1, and hereinafter “Fleisher”), in view of Kidd et al. (US 20240361818 A1, and hereinafter “Kidd”). Regarding claim 16, Fleisher teaches a computing device (Fig. 4, Abstract : storage server) comprising: a memory device (Fig. 4, Col. 18, Lines 53-67, Col. 19, Lines 1-7 : storage server 400) comprising: a memory housing (Fig. 4, Col. 18, Lines 53-67, Col. 19, Lines 1-7 : chassis 402); a primary portion (Fig. 4, Col. 18, Lines 53-67, Col. 19, Lines 1-7, Col. 20, Lines 31-52 : slidable drive tray 410) positioned within the memory housing (Fig. 4, Col. 18, Lines 53-67, Col. 19, Lines 1-7 : slidable tray 410 is positioned within the chassis 402), the primary portion comprising at least one memory element (Fig. 4, Col. 18, Lines 53-67, Col. 19, Lines 1-7, Col. 20, Lines 31-52 : slidable drive tray 410 comprises SSDs 150A-Z); and a detachable portion (Fig. 4, Col. 18, Lines 53-67, Col. 19, Lines 1-7, Col. 20, Lines 31-52 : PSU 405A-D) selectively coupled to the primary portion (Fig. 4, Col. 18, Lines 53-67, Col. 19, Lines 1-7, Col. 20, Lines 31-52 : PSU 405A-D powers the storage server 400, and connects to the chassis 402 and the slidable drive tray 410) and when coupled to the primary portion, the detachable portion is positioned within the memory housing (Fig. 4, Col. 18, Lines 53-67, Col. 19, Lines 1-7, Col. 20, Lines 31-52 : when PSU 405A-D is connected to the chassis 402 and the slidable drive tray 410, it is positioned within the chassis 402) and when the detachable portion is detached from the primary portion, the detachable portion may be removed from the memory housing (Fig. 4, Col. 18, Lines 53-67, Col. 19, Lines 1-7, Col. 20, Lines 31-52 : PSU 405A-D are hot swappable and can be removed from the chassis 402). Fleisher does not each a computer housing delimiting one or more bays on a first face. However, Kidd teaches a computer housing (Fig. 1-2, 5, [0031], [0037] : rack 205) delimiting one or more bays on a first face (Fig. 1-2, 5, [0031], [0037] : rack 205 has space on a first face for plurality of information handling systems 100/210/500); a memory housing (Fig. 1-2, 5, [0031], [0037] : housing of information handling systems 100/210/500) configured to comply with a published form factor and fit within the one or more bays (Fig. 1-2, 5, [0031], [0037] : housing of information handling systems 100/210/500 are configured to comply with a published form factor of rack 205 and fit within the space of rack 205); It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to incorporate computer housing and its bays to which the memory housings fit as taught by Kidd into Fleisher’ computing device by adding racks and inserting storage servers into the racks. The suggestion / motivation for doing so would be to improve organization, and provide easier access for maintenance. Additionally, mounting storage servers on a rack is known as evidence by (Col. 3, Lines 41-60 of Fleisher). Claim(s) 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Le Roy et al. (US 20190278914 A1, and hereinafter “Le Roy”), in view of Bhesania et al. (US 20060290326 A1, and hereinafter “Bhesania”). Regarding claim 17, Le Roy teaches a method of manipulating a memory device (Fig. 1-3, Abstract : technique for providing data protection in an integrated circuit with memory), comprising: detecting removal of an energy source module (ESM) from a memory device (Fig. 1-3, [0031-0034], [0064], [0084] : computing device 100 can detect removal of external power source 185); continuing operation of volatile memory while the ESM is removed (Fig. 1-3, [0031-0034], [0064], [0084] : volatile memory 120 operates while the external power source 185 is removed). Le Roy does not teach reporting removal to a remote location. However, Bhesania teaches reporting removal to a remote location (Fig. 1, 7, [0020-0022] : device 130 can report power status to host 140 via network). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to incorporate the reporting removal to a remote location as taught by Bhesania into Le Roy’s method of manipulating a memory device by implementing and connecting a host to the computing device. The suggestion / motivation for doing so would be to better help users manage limited power resources for their respective device, and improve user experience through an automated monitoring method (Abstract of Bhesania). Regarding claim 18, Le Roy as modified by Bhesania teaches the method of claim 17, wherein reporting the removal comprises reporting removal to a host (Fig. 1-3, [0031-0034], [0064], [0084] of Le Roy, and Fig. 1, 7, [0020-0022] of Bhesania : computing device 100 can detect removal of external power source 185, and device 130 can report power status to host 140 via network). Regarding claim 19, Le Roy as modified by Bhesania teaches the method of claim 17, further comprising detecting insertion of a second ESM (Fig. 1-3, [0031-0034], [0064], [0084] of Le Roy, and Fig. 1, 7, [0020-0022] of Bhesania : computing device 100 can detect insertion of external power source 185, and device 130 can report power status to host 140 via network). Regarding claim 20, Le Roy as modified by Bhesania teaches the method of claim 19, further comprising reporting the insertion (Fig. 1-3, [0031-0034], [0064], [0084] of Le Roy, and Fig. 1, 7, [0020-0022] of Bhesania : computing device 100 can detect removal of external power source 185, and device 130 can report power status to host 140 via network). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEON KIM whose telephone number is (703)756-4580. The examiner can normally be reached Monday to Friday, 9:00 AM - 5:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Allen L Parker can be reached on 303-297-4722. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALLEN L PARKER/Supervisory Patent Examiner, Art Unit 2841 /KEON NMN KIM/Examiner, Art Unit 2841
Read full office action

Prosecution Timeline

Nov 14, 2023
Application Filed
Sep 17, 2025
Non-Final Rejection mailed — §102, §103
Nov 26, 2025
Response Filed
Aug 13, 2026
Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
57%
Grant Probability
88%
With Interview (+31.2%)
2y 5m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
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