DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on November 14, 2023 has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: FLIP CHIP QUAD FLAT NO LEADS (QFN) PACKAGE INCLUDING CONDUCTIVE PILLARS HAVING CROSS-SECTIONS OF A PLURALITY OF SIZES AND SHAPES.
Election/Restrictions
Claims 9 and 11 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species IB and IIB, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on May 08, 2026.
Status of the Claims
Claims 9 and 11 are withdrawn. Claims 1-8, 10, and 12-16 are present for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "… the first silver spots …" in line 15. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of examination, the Examiner believes the limitation should recite, “… the at least one first silver spot …”.
Claim 1 recites the limitation "… the second silver spots …" in lines 15 and 16. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of examination, the Examiner believes the limitation should recite, “… the at least one second silver spot …”.
Claim 2 recites the limitation "… the first and second silver spots." in line 3. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of examination, the Examiner believes the limitation should recite, “… the at least one first silver spot and the at least one second silver spot.”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5, 8, 10, and 12-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baello (US 2019/0326245 A1).
Claim 1, Baello discloses an integrated circuit package (packaged integrated circuit 1000 is an integrated circuit package, hereinafter, integrated circuit package 1000, [0045], Fig. 10), comprising:
a leadframe (package substrate 209/309/409/809/909/1009/1109 includes a leadframe, hereinafter, leadframe 209/309/409/809/909/1009/1109, [0045], Fig. 10) including a first plurality of leads (pillar bumps 210/310/410/610/910/1010 include a first plurality of leads, hereinafter, first plurality of leads 610_1/1010_1, [0045], Fig. 10) and a second plurality of leads (pillar bumps 210/310/410/610/910/1010 include a second plurality of leads, hereinafter, second plurality of leads 610_2/1010_2, [0045], Fig. 10), wherein each lead of the first and second plurality of leads 1010 has an upper surface (each lead of the first and second plurality of leads 1010 has an upper surface, [0040], Figs. 6N and 10);
at least one first silver spot (solder layer 645 is includes silver and is at least one first silver spot, hereinafter, at least one first silver spot 645_1, [0034], Figs. 6N and 10) on the upper surface of each lead of the first plurality of leads 1010_1 (the at least one first silver spot 645_1 is on the upper surface of each lead of the first plurality of leads 1010_1, [0034], Figs. 6N and 10), wherein each first silver spot 645_1 has a first size and first shape in plan (the first plurality of leads 610_1 includes a first silver spot 645_1 which has a first size and first shape in plan (i.e. round pillar bump feature 751 with a diameter between 50 and 150 µm), [0041], Figs. 6N, 7A-7B, and 10);
at least one second silver spot (solder layer 645 is includes silver and is at least one second silver spot, hereinafter, at least one second silver spot 645_2, [0034], Figs. 6N and 10) on the upper surface of each lead of the second plurality of leads 1010_2 (the at least one second silver spot 645_2 is on the upper surface of each lead of the second plurality of leads 1010_2, [0034], Figs. 6N and 10), wherein each second silver spot 645_2 has a second size and second shape in plan (the second plurality of leads 610_2 includes a second silver spot 645_2 which has a second size and second shape in plan (i.e. oval bump feature 753 with a length between 100 and 400 µm and a width between 50 and 200 µm), [0041], Figs. 6N, 7A-7B, and 10);
an integrated circuit die (integrated circuit die 103/203/303/403/603/803/903/1003, [0045], Figs. 6N and 10) having a front surface including a first plurality of interconnection pads (integrated circuit die 103/203/303/403/603/803/903/1003 has a front surface including bond pad 623 is a first plurality of interconnection pads, hereinafter, first plurality of interconnection pads 623_1, [0027], Figs. 6N and 10) and a second plurality of interconnection pads (integrated circuit die 103/203/303/403/603/803/903/1003 has a front surface including bond pad 623 is a second plurality of interconnection pads, hereinafter, second plurality of interconnection pads 623_2, [0027], Figs. 6N and 10);
a first pillar (pillar 641 is a first pillar, hereinafter, first pillar 641_1, [0040], Figs. 6N and 10) mounted to each interconnection pad 623 of the first plurality of interconnection pads 623_1 (first pillar 641_1 is mounted to each interconnection pad 623 of the first plurality of interconnection pads 623_1, [0040], Figs. 6N and 10), wherein the first pillar 641_1 has a third size and third shape in plan (first pillar 641_1 has a third size and third shape in plan, [0041], Figs. 6N, 7A-7B, and 10);
a second pillar (pillar 641 is a second pillar, hereinafter, second pillar 641_2, [0040], Figs. 6N and 10) mounted to each interconnection pad 623 of the second plurality of interconnection pads 623_2 (second pillar 641_2 is mounted to each interconnection pad 623 of the second plurality of interconnection pads 623_2, [0040], Figs. 6N and 10), wherein the second pillar 641_2 has a fourth size and fourth shape in plan (second pillar 641_2 has a fourth size and fourth shape in plan, [0041], Figs. 6N, 7A-7B, and 10);
wherein the integrated circuit die 103/203/303/403/603/803/903/1003 is mounted in flip chip orientation to the leadframe 209/309/409/809/909/1009/1109 with the first pillars 641_1 soldered to the at least one first silver spot 645_1 and the second pillars 641_1 soldered to the at least one second silver spot 645_2 (integrated circuit die 1003 is mounted in flip chip orientation to the leadframe 1009 with the first pillars 641_1 soldered to the at least one first silver spot 645_1 and the second pillars 641_1 soldered to the at least one second silver spot 645_2, [0020], Fig. 10); and
a resin body (mold compound 1033 is formed of a resin and is a resin body, hereinafter, resin body 1033, [0045], Fig. 10) encapsulating the integrated circuit die 1003 mounted to the leadframe 1009 (resin body 1033 encapsulates the integrated circuit die 1003 mounted to the leadframe 1009, [0045], Fig. 10).
Claim 2, Baello discloses the integrated circuit package (integrated circuit package 1000, [0045], Fig. 10) of claim 1.
Baello discloses further comprising a non-solder wetting layer (seed layer 631 is a non-solder wetting layer, hereinafter, non-solder wetting layer 631, [0030], Figs. 6N and 10) on the upper surface of each lead of the first and second plurality of leads 610 (non-solder wetting layer 631 is on the upper surface of each lead of the first and second plurality of leads 610, [0030], Figs. 6N and 10), said non-solder wetting layer 631 surrounding the at least one first silver spot 645_1 and at least one second silver spot 645_2 (non-solder wetting layer 631 surrounds the at least one first silver spot 645_1 and at least one second silver spot 645_2, [0027], Figs. 6N and 10).
Claim 5, Baello discloses the integrated circuit package (integrated circuit package 1000, [0045], Fig. 10) of claim 2.
Baello discloses wherein said non-solder wetting layer 631 is formed using at least one of a chemical process, a heating process and a sputtering process (non-solder wetting layer 631 is formed using a chemical process (i.e. electroplating or electroless plating), [0030], Figs. 6A and 6N).
Claim 8, Baello discloses the integrated circuit package (integrated circuit package 1000, [0045], Fig. 10) of claim 1.
Baello discloses wherein the first size (the first plurality of leads 610_1 includes a first silver spot 645_1 which has a first size in plan (first size 645_1 is round pillar bump feature 751 with a diameter between 50 and 150 µm), [0041], Figs. 6N, 7A-7B, and 10) is larger than the third size (first pillar 641_1 has a third size in plan (third size 641_1 is round pillar bump feature 751 with a diameter between 50 and 150 µm), wherein the first size is larger than the third size, [0041], Figs. 6N, 7A-7B, and 10) and the first shape (first shape 645_1 is round pillar bump feature 751, [0041], Figs. 6N, 7A-7B, and 10) and third shape are the same (third shape 641_1 is round pillar bump feature 751 with a diameter between 50 and 150 µm and is the same as the first shape 645_1, [0041], Figs. 6N, 7A-7B, and 10).
Claim 10, Baello discloses the integrated circuit package (integrated circuit package 1000, [0045], Fig. 10) of claim 1.
Baello discloses wherein the second size (the second plurality of leads 610_2 includes a second silver spot 645_2 which has a second size in plan (second size 645_2 is round pillar bump feature 751 with a diameter between 50 and 150 µm), [0041], Figs. 6N, 7A-7B, and 10) is larger than the fourth size (second pillar 641_2 has a fourth size in plan (fourth size 641_1 is round pillar bump feature 751 with a diameter between 50 and 150 µm), wherein the second size is larger than the fourth size, [0041], Figs. 6N, 7A-7B, and 10) and the second shape (second shape 645_2 is round pillar bump feature 751, [0041], Figs. 6N, 7A-7B, and 10) and fourth shape are the same (fourth shape 641_2 is round pillar bump feature 751 with a diameter between 50 and 150 µm and is the same as the second shape 645_2, [0041], Figs. 6N, 7A-7B, and 10).
Claim 12, Baello discloses the integrated circuit package (integrated circuit package 1000, [0045], Fig. 10) of claim 1.
Baello discloses wherein the second plurality of leads 610_2/1010_2 (second plurality of leads 610_2/1010_2 are oval shaped and are oval lands 1141 wherein second plurality of leads 610_2/1010_2 include the leads which include oval lands 1141, [0046], Figs. 10 and 11) comprise segment leads (leads 1121 are segment leads, hereinafter, segment leads 1121, [0046], Figs. 10 and 11) extending longitudinally in a first direction between opposed first and second sides of the resin body 1033 (second plurality of leads 610_2/1010_2 comprises segment leads 1121 extending longitudinally in a first direction (i.e. horizontal x-direction) between opposed first and second sides of the resin body 1033, [0046], Figs. 10 and 11), wherein the first and second sides extend in a second direction (i.e. vertical y-direction) perpendicular to the first direction (first and second sides extend in the y-direction, wherein the y-direction is perpendicular to the x-direction, [0046], Figs. 10 and 11).
Claim 13, Baello discloses the integrated circuit package (integrated circuit package 1000, [0045], Fig. 10) of claim 12.
Baello discloses wherein the resin body 1033 further includes opposed third and fourth sides extending in the first direction (i.e. horizontal x-direction) (resin body 1033 further includes opposed third and fourth sides extending in the x-direction, [0046], Figs. 10 and 11), and wherein the first plurality of leads 610_1/1010_1 comprise end leads arranged in two groups with a first one of said two groups arranged along the third side and a second one of said two groups arranged along the fourth side (first plurality of leads 610_1/1010_1 comprise end leads arranged in two groups with a first one of said two groups arranged along the third side and a second one of said two groups arranged along the fourth side, [0047], Figs. 10 and 11).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Baello.
Claim 6, Baello discloses the integrated circuit package (integrated circuit package 1000, [0045], Fig. 10) of claim 1.
Baello discloses wherein the first plurality of leads 1010_1 provide electrode contacts at a side and bottom of the resin body 1033 (leads 1121 are electrode contacts at a side and bottom of the resin body 1033 which are configured to receive the first plurality of leads 1010_1, [0046], Figs. 10 and 11).
Baello does not explicitly disclose the resin body for a flat no leads type package.
However, Baello discloses the resin body 1033 may alternatively be configured to be a quad flat no-lead (QFN) package. The combination to utilize a package configured as a flat no leads type package allows for surface mounting to a system board (Baello, [0045]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a package configured as a flat no leads type package to allow for surface mounting to a system board (Baello, [0045]).
Claim 7, Baello discloses the integrated circuit package (integrated circuit package 1000, [0045], Fig. 10) of claim 1.
Baello discloses wherein the second plurality of leads 1010_2 provide electrode contacts at a side and bottom of the resin body 1033 (leads 1121 are electrode contacts at a side and bottom of the resin body 1033 which are configured to receive the second plurality of leads 1010_2, [0046], Figs. 10 and 11).
Baello does not explicitly disclose the resin body for a flat no leads type package.
However, Baello discloses the resin body 1033 may alternatively be configured to be a quad flat no-lead (QFN) package. The combination to utilize a package configured as a flat no leads type package allows for surface mounting to a system board (Baello, [0045]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a package configured as a flat no leads type package to allow for surface mounting to a system board (Baello, [0045]).
Claim 16, Baello discloses the integrated circuit package (integrated circuit package 1000, [0045], Fig. 10) of claim 1.
Baello discloses wherein then integrated circuit die 103/203/303/403/603/803/903/1003 further includes a third plurality of interconnection pads (integrated circuit die 103/203/303/403/603/803/903/1003 includes bond pad 623 is a first plurality of interconnection pads, hereinafter, first plurality of interconnection pads 623_1, [0027], Figs. 6N and 10) on the front surface (first plurality of interconnection pads 623_1 is on the front surface, [0027], Figs. 6N and 10), and further comprising a third pillar (pillar 641 is a third pillar, hereinafter, third pillar 641_3, [0040], Figs. 6N and 10 mounted to each interconnection pad 623 of the third plurality of interconnection pads 623_3 (third pillar 641_3 is mounted to each interconnection pad 623 of the third plurality of interconnection pads 623_3, [0040], Figs. 6N and 10).
Baello does not explicitly disclose wherein at least one of a size and a shape of the third pillar is different from a corresponding size and shape of each of the first and second pillars.
However, Baello discloses wherein at least one of a size and a shape of the third pillar is different from a corresponding size and shape of each of the first and second pillars as shapes other than the circular and ovular pillars may be used, including other sizes.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to vary, through routine experimentation, “the result effective variable of pillar cross-sectional shape and size (result effective at least insofar as pillar cross-sectional shape and size determines the current that will be carried by the pillar bump between a particular signal and the integrated circuit (Baello, [0041])) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05).
Further, the specification contains no disclosure of either the critical nature of the claimed pillar cross-sectional shape and size or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Baello in view of Yatagawa (US 2021/0375550 A1).
Claim 3, Baello discloses the integrated circuit package (integrated circuit package 1000, [0045], Fig. 10) of claim 2.
Baello does not explicitly disclose wherein said non-solder wetting layer is an oxide layer.
However, Yatagawa discloses wherein said non-solder wetting layer is an oxide layer (Yatagawa, covering layer 8 is less wettable than a surface of an adjacent plating layer by solder, hereinafter, non-solder wetting layer 8, wherein non-solder wetting layer 8 is formed of an oxide film (i.e. oxide layer), [0069], Fig. 1; Baello, non-solder wetting layer 631, [0030], Figs. 6N and 10).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Yatagawa, including the specific material of copper oxide, to the teachings of Baello.
The motivation to do so is that the combination yields the predictable results of allowing for the selection of a known material based on its suitability for the intended use as the material of the covering layer is less wettable than a surface of an adjacent plating layer by solder (Yatagawa, [0069]). Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also MPEP 2144.07.
Claim 4, Baello/Yatagawa discloses the integrated circuit package (Baello, integrated circuit package 1000, [0045], Fig. 10; Yatagawa, electronic component 1A, [0069], Fig. 1) of claim 3.
Baello/Yatagawa discloses wherein said oxide layer is a brown oxide layer (Yatagawa, non-solder wetting layer 8 is formed of a copper oxide film (i.e. brown oxide), [0069], Fig. 1; Baello, non-solder wetting layer 631, [0030], Figs. 6N and 10).
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Baello in view of Gupta (US 2018/0190608 A1).
Claim 14, Baello discloses the integrated circuit package (integrated circuit package 1000, [0045], Fig. 10) of claim 13.
Baello does not explicitly disclose wherein end surfaces of the segment leads are exposed from the resin body at the first and second sides, and wherein end surfaces of the end leads are exposed from the resin body at the third and fourth sides.
However, Gupta discloses wherein end surfaces of the segment leads are exposed from the resin body at the first and second sides (Gupta, end surfaces of the segment leads 102 are exposed from the resin body 112 at the first and second sides, [0022], Figs. 1A and 1B; Baello, resin body 1033, Figs. 10 and 11), and wherein end surfaces of the end leads 102 are exposed from the resin body 1033 at the third and fourth sides (Gupta, end surfaces of the end leads 102 are exposed from the resin body 1033 at the third and fourth sides, [0022], Figs. 1A and 1B; Baello, resin body 1033, Figs. 10 and 11). The combination to utilize segment leads specifically configured such that end surfaces are exposed from the resin body at chosen sides enables connection of desired input/output (I/O) terminals between the flip-chip semiconductor die and the underlying PCB (Gupta, [0028]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize segment leads specifically configured such that end surfaces are exposed from the resin body at chosen sides to enable connection of desired input/output (I/O) terminals between the flip-chip semiconductor die and the underlying PCB (Gupta, [0028]).
Claim 15, Baello/Gupta discloses the integrated circuit package (Baello, integrated circuit package 1000, [0045], Fig. 10; Gupta, packaged semiconductor device 100, [0025], Figs. 1A and 1B) of claim 14.
Baello/Gupta discloses wherein end surfaces of some of the end leads are exposed from the resin body at the first and second sides (Gupta, end surfaces of some of the end leads 102 are exposed from the resin body 1033 at the first and second sides, [0022], Figs. 1A and 1B; Baello, resin body 1033, Figs. 10 and 11).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nangia (US 2023/0102688 A1) discloses a (QFN) no lead package 300 further including a semiconductor die 301 that is flip-chip mounted through post connects 315 and electrically connected to conductive bond pads 325 by solder.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEVY J BOEGEL whose telephone number is (703)756-1299. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights