DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
1. The information disclosure statement (IDS) submitted on 2/14/2024 and is in compliance with the provisions of 37 CFR 1.97. According, the information disclosure statement is being considered by the Examiner.
Claim Objection
2. Claim 9 is objected to because of the following informalities: Regarding claim 9, line 2, “a temperature above 150 F” should be changed to --- a temperature above 150oC ---.
Examiner Notes
3. Examiner cites particular paragraphs, columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1-2 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (NPL: “Reliability of Wafer-Level Ultra-Thining down to 3 µm using 20 nm-Node DRAMS”; hereinafter “Chen”).
Regarding claim 1, Chen discloses a method of forcing memory cell failure in a memory chip (using a high temperature stress test for forcing DRAM memory cell to fail. See at least in the sections of Abstract and Conclusion.), comprising:
subjecting the memory chip having at least one memory cell to an elevated temperature for a predetermined amount of time sufficient to allow particles proximate or within the at least one memory cell to migrate to a vulnerable area (copper particles or Cu contamination from the backside of a wafer when the Cu contamination was involved with one of packing process. The effect of Cu contamination, causing stand-by failure, on device reliability in DRAM was investigated. Experimental tests on the DRAM were performed at different temperatures in a range of 25oC to 180oC at predetermined times 1hr, 10hrs and 100hrs, see Table 1. The test results showed that Cu particles migrated into silicon Si from the back of the wafer and Cu particles out-diffusion to a neighboring gate, herein silicon or neighboring gate area is equivalent to a vulnerable area. See section 3: Results and Discussion and section 4: Conclusion).
Regarding claim 2, Chen discloses the method of claim 1, wherein subjecting the memory chip to the elevated temperature, comprises subjecting the memory chip to a temperature above 150 C (“The HTS tests were performed at 150oC and 180oC…”, see section 3: Results and Discussion and Table 1).
Regarding claim 7, Chen discloses the method of claim 1, further comprising testing the at least one memory cell for viability after removing the memory chip from the elevated temperature (testing and evaluating the memory cell at different stage with different temperatures, see section 3 and table 1).
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 3-5 and 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Jo et al. (US. Pub. 2016/0225824; hereinafter “Jo”).
Regarding claim 3, Chen discloses the method of claim 1, further comprising while subjecting the memory chip to the elevated temperature to the memory chip (see section 3: Results and Discussion and Table 1). Chen does not explicitly specify that applying an electrical field to the memory cell.
Jo discloses a method of applying an electrical field to a memory cell (Fig. 2) to stimulate particles to migrate from one region to another region (see at least in [0043]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the memory chip of Chen by applying an electrical field to the memory cell for sufficient time to allow particles proximate or within the memory cell to migrate to an evaluated area as taught by Jo in order to meet the system design and specification requirement.
Regarding claim 4, Chen and Jo disclose the method of claim 3, Jo further teaches wherein the electrical field is oriented so as to drive a positive ion in a first location towards the vulnerable area (applying an electric field the memory cell so that ionizes metal atoms or metal particles from a layer 204, causes diffusion of the metal particles into a layer 206, see [0043, 49]).
Regarding claim 5, Chen and Jo disclose the method of claim 3, wherein the electrical field is oriented so as to drive a copper particle towards a doped section of a substrate in the at least one memory cell (applying the electrical field to the memory cell for stimulating migration of metal particles as taught by Chen, with under inducing by thermal activity process as taught by Chen, a copper particle or Cu contamination from the backside of the wafer migrated into silicon Si and Cu particles out-diffusion to a neighboring gate; see section 3: Result and Discussion of Chen).
Regarding claim 8, Chen discloses a method of forcing memory cell failure in a memory chip (using a high temperature stress test for forcing DRAM memory cell to fail. See at least in abstract and Conclusion), comprising: applying an electrical field to the memory chip having at least one memory cell for sufficient time to allow particles proximate or within the memory cell to migrate to a vulnerable area (copper particles or Cu contamination from the backside of a wafer when the Cu contamination was involved with one of packing process. The effect of Cu contamination, causing stand-by failure, on device reliability in DRAM was investigated. The exponential model TTF (time-to-failure) describing the effect of temperature and the electric field induced on the TTF. Under inducing by thermal activation process, Copper particles migrated into silicon Si from the back of the wafer and Cu particles out-diffusion to a neighboring gate, herein silicon or neighboring gate area is equivalent to a vulnerable area. See section 3: Results and Discussion).
Chen does not explicitly specify that applying an electrical field to the memory cell for sufficient time to allow particles proximate or within the memory cell to migrate to a vulnerable area. However using the electric field to stimulate movement or migration of conductive particles is well known in the art.
Jo discloses a method of applying an electrical field to a memory cell (Fig. 2) to stimulate particles to migrate from one region to another region (see at least in [0043]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the memory chip of Chen by applying an electrical field to the memory cell for sufficient time to allow particles proximate or within the memory cell to migrate to an evaluated area as taught by Jo in order to meet the system design and specification requirement.
Regarding claim 9, Chen and Jo disclose the method of claim 8, Chen further teaches comprising, while applying the electrical field, subjecting the memory chip to a temperature above 150 F (see section 3: Result and Discussion).
Regarding claim 10, Chen and Jo disclose the method of claim 9, Chen further teaches wherein the particles comprise at least one copper particle (Cu contamination, see abstract or section 1: Introduction).
Regarding claim 11, discloses a memory chip (DRAM in Fig. 1) comprising a memory cell having a particle (copper particles or Cu contamination) in a vulnerable area (silicon or neighboring gate, see Fig. 1), wherein the particle migrated to the vulnerable area after manufacturing as a result of the memory chip being exposed to an elevated temperature above 150 C and an electrical field (copper particles or Cu contamination from the backside of a wafer when the Cu contamination was involved with one of packing process. The effect of Cu contamination, causing stand-by failure, on device reliability in DRAM was investigated. The exponential model TTF (time-to-failure) describing the effect of temperature and the electric field induced on the TTF. Under inducing by thermal activation process, Copper particles migrated into silicon Si from the back of the wafer and Cu particles out-diffusion to a neighboring gate, herein silicon or neighboring gate area is equivalent to a vulnerable area. See section 3: Results and Discussion).
Chen does not explicitly specify that applying an electrical field to the memory cell for sufficient time to allow particles proximate or within the memory cell to migrate to a vulnerable area. However using the electric field to stimulate movement or migration of conductive particles is well known in the art.
Jo discloses a method of applying an electrical field to a memory cell (Fig. 2) to stimulate particles to migrate from one region to another region (see at least in [0043]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the memory chip of Chen by applying an electrical field to the memory cell for sufficient time to allow particles proximate or within the memory cell to migrate to an evaluated area as taught by Jo in order to meet the system design and specification requirement.
7. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Jo and further in view of Takagi et al. (US. Pub. 20100112341; hereinafter “Takagi”).
Regarding claim 6, Chen and Jo disclose the method of claim 3, except for specifying wherein the electrical field is oriented to drive a mold compound particle on a side wall of the at least one memory cell to the vulnerable area.
Takagi discloses applying a strong electrical field to drive a mold compound to accelerate the ion migration.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the memory chip of Chen and Jo by applying a strong electrical field to drive a mold compound to accelerate the particle migration as taught by Takagi in order to drive a mold compound particle on a side wall of the at least one memory cell to the suspected area.
Prior Art of Record
8. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Matsumoto (U.S Pub. 2015/0318222) discloses a method of evaluating metal contamination in a semiconductor wafer that has been subjected to a heat treatment (see specification for more details).
Tsumura (U.S Pub. 2012/0319296) discloses a semiconductor device (see specification for more details).
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANG LE whose telephone number is (571)272-9349. The examiner can normally be reached on Monday thru Friday 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached on (571) 272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THANG X LE/Primary Examiner, Art Unit 2858
3/20/2026