DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species B & 1 in the reply filed on 3/20/2026 is acknowledged. Claims 13-16, 23, and 26-27 are cancelled. Claims 1-12, 17-22, & 24-25 are examined on the merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-5, 10, 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. Pub. No. US 20210408011 A1, which is of record, to Fujiwara et al. (hereinafter “Fujiwara”).
Regarding claim 1, Fujiwara teaches an integrated circuit comprising:
a cell array (layout 206; fig. 2B) [0034] comprising a plurality of cells (212(1) and 212(2)) [0036], each of the plurality of cells (212) including at least one transistor (P1, P2, P3, P4, hereinafter “transistor”; figs. 2A & 2B) [0028];
a power rail (buried conductive patterns 222; fig. 2B & 2D) [0047] in a power rail layer (layer of 222) under (vertically) the cell array (206), the power rail (222) being configured to provide power [0047] to the cell array (206); and
a plurality of contacts (buried contact-to-transistor component patterns BVD 220(1 or 2); figs. 2B & 2D) [0047] between (in a vertical sense, or in a direction perpendicular to the x-y plane of fig. 2B) the cell array (206) and the power rail (222),
wherein each of the plurality of contacts (220) extends downward (vertically) from a source (present in the active region AR(1); fig. 2D) [0059] of a transistor (present in the active region AR(1); figs. 2A & 2D) of a corresponding one of the plurality of cells (212) to the power rail (222).
To further clarify, regarding the transistors and the source, it is interpreted that these elements are inherently present in the active layer, in spite of Fujiwara being silent on this matter. Fujiwara teaches the presence of transistors (P1, P2, etc.; fig. 2A) [0028] and contact-to-transistor-component structures (MD; fig. 2D) (abstract) but is silent on the specific positioning (i.e., in the z-direction) of the transistors. However, given the above, and given that transistors are active elements, the “contact-to-transistor-component” suggests that the elements MD would be in contact with the transistors. Additionally, there is no other obvious place (i.e., more likely place) where the transistors could be disposed and because the transistors are active elements, it is at least more likely than not that the transistors would be disposed in the active region.
The above is believed to satisfy the evidence and reasoning requirements of M.P.E.P. 2112 IV.
Regarding claim 3, Fujiwara teaches the integrated circuit of claim 1, wherein each of the plurality of cells (212) has a same footprint (same size in a plan view; fig. 2B), and the plurality of contacts (220) are arranged on the power rail (222).
Regarding claim 4, Fujiwara teaches the integrated circuit of claim 1, wherein the plurality of cells (212) comprise a first cell (212(1)) and a second cell (212(2)) adjacent to the first cell (212(1)), and the first cell (212(1)) and the second cell (212(2)) are symmetrical with each other about a boundary (horizontal boundary between cells in fig. 2B) between the first cell (212(1)) and the second cell (212(2)).
Regarding claim 5, Fujiwara teaches the integrated circuit of claim 4, wherein the power rail (222) comprises a first portion (portion of 222(2) under 212(1)) under the first cell (212(1)) and a second portion (portion of 222(2) under 212(2)) under the second cell (212(2)), and the first portion (222(2) of 212(1)) and the second portion (222(2) of 212(2)) are symmetrical with each other about a boundary (divide between first and second cells 212) between the first portion (222(2) of 212(1)) and the second portion (222(2) of 212(2)).
Regarding claim 10, Fujiwara teaches an integrated circuit comprising:
a cell array (layout 206; fig. 2B) [0034] comprising a plurality of cells (212(1) and 212(2)) [0036], each of the plurality of cells (212) including at least one transistor (P1, P2, P3, P4, hereinafter “transistor”; figs. 2A & 2B) [0028];
a power rail (buried conductive patterns 222; fig. 2B & 2D) [0047] in a power rail layer (layer of 222) under (vertically) the cell array (206), the power rail (222) being configured to provide power [0047] to the cell array (206); and
a plurality of contacts (buried contact-to-transistor component patterns BVD 220(1 or 2); figs. 2B & 2D) [0047] between (in a vertical sense, or in a direction perpendicular to the x-y plane of fig. 2B) the cell array (206) and the power rail (222),
wherein each of the plurality of contacts (222) has a top surface (vertically) connected (at least electrically) to a source (present in the active region AR(1); fig. 2D) [0059] of a transistor (transistor) of a corresponding one of the plurality of cells (212) and a bottom surface (vertically) connected (at least electrically) to the power rail (222).
To further clarify, regarding the transistors and the source, it is interpreted that these elements are inherently present in the active layer, in spite of Fujiwara being silent on this matter. Fujiwara teaches the presence of transistors (P1, P2, etc.; fig. 2A) [0028] and contact-to-transistor-component structures (MD; fig. 2D) (abstract) but is silent on the specific positioning (i.e., in the z-direction) of the transistors. However, given the above, and given that transistors are active elements, the “contact-to-transistor-component” suggests that the elements MD would be in contact with the transistors. Additionally, there is no other obvious place (i.e., more likely place) where the transistors could be disposed and because the transistors are active elements, it is at least more likely than not that the transistors would be disposed in the active region.
The above is believed to satisfy the evidence and reasoning requirements of M.P.E.P. 2112 IV.
Regarding claim 12, Fujiwara teaches the integrated circuit of claim 10, wherein each of the plurality of cells (212) has a same footprint (same size in a plan view; fig. 2B), and the plurality of contacts (220) are arranged on the power rail (222).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 19 & 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara in view of U.S. Pat. Pub. No. US 20160307882 A1 to Chen et al. (hereinafter “Chen”).
Regarding claim 19, Fujiwara teaches an integrated circuit comprising:
a cell array (layout 206; fig. 2B) [0034] comprising a plurality of cells (212(1) and 212(2)) [0036], each cell comprising two transistors ((P1, P2, P3, P4, hereinafter “transistor”; figs. 2A & 2B) [0028] that are cross-coupled to each other (fig. 2A);
a power rail (buried conductive patterns 222; fig. 2B & 2D) [0047] in a power rail layer (layer of 222) under the cell array (206); and
a plurality of contacts (buried contact-to-transistor component patterns BVD 220(1 or 2); figs. 2B & 2D) [0047] between the cell array (206) and the power rail (222),
wherein each of the plurality of contacts (222) extends downward (vertically) from a source (present in the active region AR(1); fig. 2D) [0059] of a transistor (one of P1, P2, P3, or P4) of a corresponding one of the two transistors (transistors) to the power rail (222).
Fujiwara does not teach that the transistors are inverters.
Chen et al, however, teaches an integrated circuit comprising cross-coupled transistors (PU-2 & PD-2; fig. 1) [0018] functioning as inverters [0018].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the transistors of Fujiwara to comprise inverters which are cross-coupled to form a storage unit as taught by Chen [0018].
To further clarify, regarding the transistors and the source, it is interpreted that these elements are inherently present in the active layer, in spite of Fujiwara being silent on this matter. Fujiwara teaches the presence of transistors (P1, P2, etc.; fig. 2A) [0028] and contact-to-transistor-component structures (MD; fig. 2D) (abstract) but is silent on the specific positioning (i.e., in the z-direction) of the transistors. However, given the above, and given that transistors are active elements, the “contact-to-transistor-component” suggests that the elements MD would be in contact with the transistors. Additionally, there is no other obvious place (i.e., more likely place) where the transistors could be disposed and because the transistors are active elements, it is at least more likely than not that the transistors would be disposed in the active region.
The above is believed to satisfy the evidence and reasoning requirements of M.P.E.P. 2112 IV.
Regarding claim 21, Fujiwara in view of Chen teaches the integrated circuit of claim 19, wherein each of the plurality of cells (212) has a same footprint (same size in a plan view; fig. 2B), and the plurality of contacts (220) are arranged on the power rail (222).
Regarding claim 22, Fujiwara in view of Chen teaches the integrated circuit of claim 19, wherein the plurality of cells (212) comprise a first cell (212(1)) and a second cell (212(2)) adjacent to the first cell (212(1)), and the first cell (212(1)) and the second cell (212(2)) are symmetrical with each other about a boundary (horizontal boundary between cells in fig. 2B) between the first cell (212(1)) and the second cell (212(2)).
Claims 6-7, 9, & 18 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara as applied to claims 1 and 10 above, and further in view of U.S. Pat. Pub. No. US 20210343332 A1, which is of record, to Chiu et al. (hereinafter “Chiu”).
Regarding claim 6, Fujiwara does not teach the integrated circuit of claim 4, wherein the plurality of cells further comprise a third cell adjacent to the first cell and a fourth cell adjacent to the second cell, the first cell and the third cell are symmetrical with each other about a boundary between the first cell and the third cell, and the second cell and the fourth cell are symmetrical with each other about a boundary between the second cell and the fourth cell.
Chiu, however, teaches an integrated circuit (figs. 1-2) wherein the plurality of cells further comprise a third cell (any of 104; fig. 1) [0030] adjacent to the first cell (any of 104 adjacent to the third cell; fig. 1) [0030] and a fourth cell (any of 104 adjacent to the second cell; fig. 1) [0030] adjacent to the second cell (any of 104 adjacent to the fourth cell; fig. 1) [0030], the first cell and the third cell are symmetrical with each other about a boundary (see symmetrical boundaries between cells 104; fig. 1) between the first cell and the third cell, and the second cell and the fourth cell are symmetrical with each other about a boundary (see symmetrical boundaries between cells 104; fig. 1) between the second cell and the fourth cell.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the circuit of Fujiwara to include additional cells to meet the limitations of claim 6 to allow for performance tuning (i.e., more cells means more tuning opportunities) as taught by Chiu [0030].
Regarding claim 7, Fujiwara in view of Chiu teaches the integrated circuit of claim 6, wherein the power rail (222) comprises a first portion (portion under first cell) under the first cell (212(1)) and a second portion (portion under second cell) under the second cell (212(2)), the first portion and the second portion are symmetrical with each other about a boundary between the first portion and the second portion (same boundary as divides the cells), the power rail further comprises a third portion (portion under a third cell, as modified by Chiu) under the third cell (third cell of Chiu) and a fourth portion (portion under a fourth cell, as modified by Chiu) under the fourth cell (fourth cell of Chiu), the first portion and the third portion are symmetrical with each other about a boundary between the first portion and the third portion, and the second portion and the fourth portion are symmetrical with each other about a boundary between the second portion and the fourth portion (requiring a symmetrical grid, this being met if even Fujiwara fig. 2B is duplicated).
The Examiner notes that the modification of Chiu adds a grid like structure to the circuit of Fujiwara.
Regarding claim 9, Fujiwara does not teach the integrated circuit of claim 1, further comprising a plurality of word lines extending parallel to each other in a first horizontal direction in a first wiring layer over the cell array, wherein, in the first wiring layer, a pattern between adjacent word lines, from among the plurality of word lines, is omitted.
Chiu, however, teaches an integrated circuit (fig. 1) comprising a plurality of word lines (word lines 108; fig. 1) [0027] extending parallel to each other (parallel on other sides of the structure in fig. 1) in a first horizontal direction (direction of word lines) in a first wiring layer (layer of word lines) over (vertically) the cell array (array of fig. 1), wherein, in the first wiring layer, a pattern between adjacent word lines, from among the plurality of word lines, is omitted (there are no word lines between the word lines 108 on either edge).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the circuit of Fujiwara to comprise word lines meeting the limitations of claim 9 to improve overall device performance as taught by Chiu [0027].
Regarding claim 18, Fujiwara does not teach the integrated circuit of claim 10, further comprising a plurality of word lines extending parallel to each other in a first horizontal direction in a first wiring layer over the cell array, wherein, in the first wiring layer, a pattern between adjacent word lines of the plurality of word lines is omitted.
Chiu, however, teaches an integrated circuit (fig. 1) comprising a plurality of word lines (word lines 108; fig. 1) [0027] extending parallel to each other (parallel on other sides of the structure in fig. 1) in a first horizontal direction (direction of word lines) in a first wiring layer (layer of word lines) over (vertically) the cell array (array of fig. 1), wherein, in the first wiring layer, a pattern between adjacent word lines, from among the plurality of word lines, is omitted (there are no word lines between the word lines 108 on either edge).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the circuit of Fujiwara to comprise word lines meeting the limitations of claim 9 to improve overall device performance as taught by Chiu [0027].
Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara as applied to claims 8 and 17 above, and further in view of U.S. Pat. Pub. No. US 20210375883 A1, which is of record, to Hsu et al. (hereinafter “Hsu”).
Regarding claim 8, Fujiwara does not teach the integrated circuit of claim 1, wherein the plurality of cells are each configured to operate based on a positive supply voltage and a negative supply voltage, and the power rail is configured to receive the negative supply voltage.
Hsu, however, teaches an integrated circuit (figs. 4B & 5) wherein the plurality of cells (SRAM cells 120, which may be duplicated; figs. 4B & 5) [0016] are each configured to operate based on a positive supply voltage (potential power rail VDD; fig. 4B) [0014] and a negative supply voltage (potential through ground Vss; fig. 5) [0014], and the power rail (Vss) is configured to receive the negative supply voltage [0029].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the circuit of Fujiwara to comprise positive and negative voltages to allow for power supply and ground protection as taught by Hsu [0021] & [0053].
Regarding claim 17, Fujiwara does not teach the integrated circuit of claim 10, wherein the plurality of cells are each configured to operate based on a positive supply voltage and a negative supply voltage, and the power rail is configured to receive the negative supply voltage.
Hsu, however, teaches an integrated circuit (figs. 4B & 5) wherein the plurality of cells (SRAM cells 120, which may be duplicated; figs. 4B & 5) [0016] are each configured to operate based on a positive supply voltage (potential power rail VDD; fig. 4B) [0014] and a negative supply voltage (potential through ground Vss; fig. 5) [0014], and the power rail (Vss) is configured to receive the negative supply voltage [0029].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the circuit of Fujiwara to comprise positive and negative voltages to allow for power supply and ground protection as taught by Hsu [0021] & [0053].
Claims 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara in view of Chen as applied to claim 22 above, and further in view of Chiu.
Regarding claim 24, Fujiwara in view of Chen does not teach the integrated circuit of claim 22, wherein the plurality of cells further comprise a third cell adjacent to the first cell and a fourth cell adjacent to the second cell, the first cell and the third cell are symmetrical with each other about a boundary between the first cell and the third cell, and the second cell and the fourth cell are symmetrical with each other about a boundary between the second cell and the fourth cell.
Chiu, however, teaches an integrated circuit (figs. 1-2) wherein the plurality of cells further comprise a third cell (any of 104; fig. 1) [0030] adjacent to the first cell (any of 104 adjacent to the third cell; fig. 1) [0030] and a fourth cell (any of 104 adjacent to the second cell; fig. 1) [0030] adjacent to the second cell (any of 104 adjacent to the fourth cell; fig. 1) [0030], the first cell and the third cell are symmetrical with each other about a boundary (see symmetrical boundaries between cells 104; fig. 1) between the first cell and the third cell, and the second cell and the fourth cell are symmetrical with each other about a boundary (see symmetrical boundaries between cells 104; fig. 1) between the second cell and the fourth cell.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the circuit of Fujiwara to include additional cells to meet the limitations of claim 6 to allow for performance tuning (i.e., more cells means more tuning opportunities) as taught by Chiu [0030].
Regarding claim 25 Fujiwara in view of Chen and Chiu teaches the integrated circuit of claim 24, Fujiwara teaches the integrated circuit of claim 6, wherein the power rail (222) comprises a first portion (portion under first cell) under the first cell (212(1)) and a second portion (portion under second cell) under the second cell (212(2)), the first portion and the second portion are symmetrical with each other about a boundary between the first portion and the second portion (same boundary as divides the cells), the power rail further comprises a third portion (portion under a third cell, as modified by Chiu) under the third cell (third cell of Chiu) and a fourth portion (portion under a fourth cell, as modified by Chiu) under the fourth cell (fourth cell of Chiu), the first portion and the third portion are symmetrical with each other about a boundary between the first portion and the third portion, and the second portion and the fourth portion are symmetrical with each other about a boundary between the second portion and the fourth portion (requiring a symmetrical grid, this being met if even Fujiwara fig. 2B is duplicated).
The Examiner notes that the modification of Chiu adds a grid like structure to the circuit of Fujiwara.
Allowable Subject Matter
Claims 2, 11, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding the subject matter, Fujiwara cannot be modified to meet the limitations of these claims as it would render Fujiwara unsatisfactory for its intended purpose i.e., a moving of the contacts of Fujiwara would more likely than not cause the circuit of Fujiwara to not function as intended. M.P.E.P. 2143.01 V.
1,3-10,12,17-19 and 21-25
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN EDWARD CUTLER whose telephone number is (703)756-5415. The examiner can normally be reached Monday-Friday 7:30 am - 5:00 pm Eastern Time.
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/ETHAN EDWARD CUTLER/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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