DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/18/2026 has been entered.
Response to Amendment
The amendment with respect to claim(s) 1, and 6-8 filed on 9/28/2026 have been fully considered for examination based on their merits. The previously presented claim(s) 2-3, and 9-13 have been considered. Claim(s) 4-5 are canceled.
Response to Arguments
Applicant’s arguments, see Remarks, pages 5-10, filed 08/18/2026, with respect to the rejection(s) of claim(s) 1-13 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of KIM.
Regarding Claim 1. Applicant argues that YAMAGUCHI fails to disclose or suggest the amended features, recites, “a power module comprising: wherein at least one of the first substrate or the second substrate includes a plurality of sensing patterns individually formed to receive a potential of the first portion and a potential of the second portion, respectively, and wherein the plurality of sensing patterns are electrically isolated from a power pattern through which a first current from the semiconductor chip flows.”. Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, the prior-art of KIM teaches a power module with a structure similar to the instant application, wherein the via spacer is separated from the semiconductor chip by a predetermined distance in the second direction as compared drawings depicted below.
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Regarding Claims 2-3, and 6-13: The dependent claims 2-3, and 6-13 follow similar arguments as Claim 1, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim(s) 1 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. For instance, the amended claim limitations with specific relevance to “sensing patterns” and “power patterns”, it appears, there are no sufficient support available throughout the specification. A couple of paragraphs of the instant application, for example, paras [0048], and [0073] exhibited the co-occurrence of the terms, “sensing”, “power” and “pattern(s)”, however it was not very clear to the Examiner, the claimed limitations mentioned above were supported by the above referred paragraphs. Therefore, the amended features, “sensing patterns” and/or the “power patterns” are considered as “new matters” as opposed to the arguments (see Remarks, page 5).
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim limitation “plurality of sensing patterns individually formed to receive a potential of the first portion and portion of the second portion; wherein the plurality of sensing patterns are electrically isolated from a power pattern” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. It appears that there is a lack of support in the specification regarding the sensing patterns and power pattern thus leads to interpret the term “sensing patterns formed as a “means” to receive a potential of the first portion” in the amended claim 1 as . Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claims 2-3, and 6-13 depends on claim 1, and are subjected to 112(a), 112(b) and 112(f) rejections as discussed above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Woo-Yong Jeon, (hereinafter JEON), US 20160126157 A1, in view of Nobuhisa Yamaguchi et al, (hereinafter YAMAGUCHI), US 20120147641 A1, and Hyeon Uk Kim et al, (hereinafter KIM), KR20220048806A.
Regarding Claim 1, JEON teaches a power module (Fig. 2, 200, cooling power module) comprising:
a first substrate (Fig. 2, 210, low-end terminal) and a second substrate (Fig. 2, 260, upper-end terminal), each of which includes an insulating layer (Fig. 2, 212/262, ceramic plate) and a metal layer (Fig. 2, 213/261, copper plate) disposed on a surface of the insulating layer (Fig. 2, 212/262, ceramic plate), wherein the metal layers (Fig. 2, 213/261, copper plate) are arranged and spaced from each other to face each other in a first direction (annotated Figure 2);
a semiconductor chip (Fig. 2, 231, power semiconductor chip) disposed between the first substrate (Fig. 2, 210, low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal) in the first direction (annotated Figure 2); and
a via spacer (annotated Figure 2) extending in the first direction (annotated Figure 2), electrically connecting (Fig. 2, solder) the first substrate (Fig. 2, 210, low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal), between the first substrate (Fig. 2, 210, low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal) and separated from the semiconductor chip (Fig. 2, 231, power semiconductor chip) with a predetermined distance (annotated Figure 2) in a second direction crossing the first direction (annotated Figure 2).
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JEON does not explicitly disclose a power module comprising: wherein the via spacer includes: a first portion electrically connected to the first substrate; a second portion electrically connected to the second substrate; and a resistor portion including a resistance value greater than resistance values of the first portion and the second portion and arranged between the first portion and the second portion in the first direction.
YAMAGUCHI teaches a power module (Fig. 2, PM) comprising:
wherein the via spacer (annotated Figure 2) includes:
a first portion (Fig. 2, 24p/24n, via conductor) electrically connected (Fig. 2, 26, wiring layer) to the first substrate (Fig. 2, 30, the conductor);
a second portion (Fig. 2, 32p/32n, via conductor) electrically connected (Fig. 2, 34p/34n, wiring layer) to the second substrate (Fig. 2, 40p/40n, the conductor); and
a resistor portion (annotated Figure 2, 22p/22n, semiconductor chip, [0049]) including a resistance value greater than resistance values (see Notes below) of the first portion (Fig. 2, 24p/24n, via conductor) and the second portion (Fig. 2, 32p/32n, via conductor) and arranged between (annotated Figure 2) the first portion (Fig. 2, 24p/24n, via conductor) and the second portion (Fig. 2, 32p/32n, via conductor) in the first direction (annotated Figure 2). [NOTE: According to Wikipedia, the electrical resistance or resistivity of a semiconductor is greater than the conductor; please see https://en/wikipedia.org/wiki/Electrical_resistivity_and_conductivity].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified JEON to incorporate the teachings of YAMAGUCHI, such that a power module comprising: wherein the via spacer includes: a first portion electrically connected to the first substrate; a second portion electrically connected to the second substrate; and a resistor portion including a resistance value greater than resistance values of the first portion and the second portion and arranged between the first portion and the second portion in the first direction. The said arrangement of a semiconductor chip having a switching element (Swp/Swn) and a floating diode (FDp/FDn) in parallel configuration with a snubber resistor (18p), to form a snubber circuit, enables to reduce the parasitic inductance, while the heat generated from the snubber circuit is dissipated through the conductor on both sides of the semiconductor chip (YAMAGUCHI, Figures 1-2, [0003-0008]).
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JEON as modified by YAMAGUCHI does not explicitly disclose a power module comprising: wherein at least one of the first substrate or the second substrate includes a plurality of sensing patterns individually formed to receive a potential of the first portion and a potential of the second portion, respectively, and wherein the plurality of sensing patterns are electrically isolated from a power pattern through which a first current from the semiconductor chip flows.
KIM teaches a power module (Fig. 1, power module, [0009]) comprising:
wherein at least one of the first substrate (annotated Figure 1; Fig. 2, 100, first insulating substrate) or the second substrate (annotated Figure 1; Fig. 2, 200, second insulating substrate) includes a plurality of sensing patterns (annotated Figure 1) individually formed to receive a potential of the first portion and a potential of the second portion (annotated Figure 1), respectively, and
wherein the plurality of sensing patterns (annotated Figure 1) are electrically isolated from a power pattern (annotated Figure 1) through which a first current from the semiconductor chip flows (Figs. 4a-4c, 40; heat conduction paths or thermal diffusion paths, while also securing a path for transmitting electric signals, [0007], [0052], [0069]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have JEON as modified by YAMAGUCHI to incorporate the teachings of KIM, such that a power module comprising: wherein at least one of the first substrate or the second substrate includes a plurality of sensing patterns individually formed to receive a potential of the first portion and a potential of the second portion, respectively, and wherein the plurality of sensing patterns are electrically isolated from a power pattern through which a first current from the semiconductor chip flows, so that the heat generated from a semiconductor chip can be effectively (KIM, [0077]).
Regarding Claim 2, JEON as modified by YAMAGUCHI, and KIM teaches the power module of claim 1.
YAMAGUCHI further teaches the power module (Fig. 2, PM), wherein the first portion (Fig. 2, 24p/24n, via conductor) and the second portion (Fig. 2, 32p/32n, via conductor) extend in a same length in the first direction (annotated Figure 2), and the resistor portion (annotated Figure 2, 22p/22n, semiconductor chip, [0049]) is disposed at a center portion of the via spacer (annotated Figure 2).
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Regarding Claim 3, JEON as modified by YAMAGUCHI, and KIM teaches the power module of claim 1.
YAMAGUCHI further teaches the power module (Fig. 2, PM), wherein the resistor portion (annotated Figure 2, 22p/22n, semiconductor chip, [0049]) extends in a same length (annotated Figure 2) as the first portion (Fig. 2, 24p/24n, via conductor) and the second portion (Fig. 2, 32p/32n, via conductor) in the second direction (annotated Figure 2).
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Regarding Claim 4, JEON as modified by YAMAGUCHI, teaches the power module of claim 1.
YAMAGUCHI further teaches the power module (Fig. 2, PM), wherein potentials (Figs. 1-2, high-potential side wiring (Lp)/low-potential side wiring (Ln)/intermediate wiring (Lo), [0038-0041]) of the first portion (Fig. 2, 24p/24n, via conductor) and the second portion (Fig. 2, 32p/32n, via conductor) are transferred (Fig. 2, high-potential side, Lp, low-potential side Ln, and the intermediate wiring Lo, [0039-0041]); to at least one of the first substrate (Fig. 2, 30, the conductor) and the second substrate (Fig. 2, 40, the conductor).
Regarding Claim 5, JEON as modified by YAMAGUCHI, teaches the power module of claim 4.
YAMAGUCHI further teaches the power module (Fig. 2, PM), wherein at least one of the first substrate (Fig. 2, 30, the conductor) and the second substrate (Fig. 2, 40, the conductor) includes a plurality of patterns (Fig. 2, 42p/42n or 42#, patterning of the insulating film, [0095]) individually formed to receive the potentials (Fig. 2, 42p/42n is connected to the 40p/40n and 40p/40n having high-potential side and low-potential side, [0039-0041]).
Regarding Claim 6, JEON as modified by YAMAGUCHI, and KIM teaches the power module of claim 1.
YAMAGUCHI further teaches the power module (Fig. 2, PM), wherein the first portion (Fig. 2, 24p/24n, via conductor) and the second portion (Fig. 2, 32p/32n, via conductor) are each connected to the plurality of sensing patterns (Fig. 2, 42p/42n or 42#, patterning of the insulating film, [0095]) through a wire (Fig. 2, 38p/38n, the conductor).
Regarding Claim 7, JEON as modified by YAMAGUCHI, and KIM teaches the power module of claim 5.
YAMAGUCHI further teaches the power module (Fig. 2, PM), wherein the plurality of patterns (Fig. 2, 42p/42n or 42#, patterning of the insulating film, [0095]) are connected to a signal lead (Figs. 2/16, bonding wires, G, KE, [0136]) transferring the received potential of the first potion (Fig. 2, 24p/24n, via conductor) and the received potential of the second portion (Fig. 2, 32p/32n, via conductor) to an outside (Fig2. 2/16, 68p/68n, terminals, [0136]) of the power module (Figs. 2/16, PM).
Regarding Claim 8, JEON as modified by YAMAGUCHI, and KIM teaches the power module of claim 1.
JEON further teaches the power module (Fig. 2, 200, cooling power module), wherein the via spacer (Fig. 2, 251-1/251-2, first/second horizontal spacers, [0044]) receives a first current (Fig. 2, current flows from the positive electrode terminal, (+), 213-1 to the first output terminal, 263-1 of the upper-end terminal 260 through the first power semiconductor chip, 231, and the first horizontal spacer, 251-1, [0053]) passed through the semiconductor chip (Fig. 2, 231, first power semiconductor chip) through one of the first substrate (Fig. 2, 210, low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal) and transfers the received first current to another of the first substrate (Fig. 2, 210, low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal).
Regarding Claim 9, JEON as modified by YAMAGUCHI, and KIM teaches the power module of claim 8.
YAMAGUCHI further teaches the power module (Fig. 2, PM), wherein the resistor portion (annotated Figure 2, 22p/22n, semiconductor chip, [0049]) receives a second current for sensing the first current, separately from the first current (Fig. 2, the sense terminal is provided to output a minute electric current that has a correlation with an electric current flowing between a pair of terminals of the switching element, Swp of semiconductor chip, 22p, [0137]).
Regarding Claim 10, JEON as modified by YAMAGUCHI, and KIM teaches the power module of claim 8.
YAMAGUCHI further teaches the power module (Fig. 2, PM), wherein the second current (Fig. 2, the sense terminal is provided to output a minute electric current, [0137]) includes a current value less than a current of the first current (Fig. 2, high-frequency current is equivalent to large current, [0141]).
Regarding Claim 11, JEON as modified by YAMAGUCHI, and KIM teaches the power module of claim 1.
JEON teaches a power module (Fig. 2, 200, cooling power module), further including a chip spacer (Fig. 2, 251-1/251-2, horizontal spacer) connecting a first surface (annotated Figure 2) of the semiconductor chip (Fig. 1, 231, power semiconductor chip) to one of the first substrate (Fig. 2, 210 low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal) and a second surface (annotated Figure 2) of the semiconductor chip (Fig. 1, 231, power semiconductor chip) is connected to a remaining (annotated Figure 2) one of the first substrate (Fig. 2, 210 low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal).
Regarding Claim 12, JEON as modified by YAMAGUCHI, and KIM teaches the power module of claim 11.
JEON further teaches a power module (Fig. 2, 200, cooling power module), wherein the chip spacer (Fig. 2, 251-1/251-2, horizontal spacer) is connected to the first surface (annotated Figure 2) of the semiconductor chip (Fig. 1, 231, power semiconductor chip) and the one of the first substrate (Fig. 2, 210 low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal) by an adhesive (Fig. 2, solder) and the second surface (annotated Figure 2) of the semiconductor chip (Fig. 1, 231, power semiconductor chip) is connected to the remaining (annotated Figure 2) one of the first substrate (Fig. 2, 210 low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal) by the adhesive (Fig. 2, solder).
Regarding Claim 13, , JEON as modified by YAMAGUCHI, and KIM teaches the power module of claim 1.
JEON further teaches a power module (Fig. 2, 200, cooling power module), wherein the first substrate (Fig. 2, 210 low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal) includes additional metal layers (Fig. 2, 211/263, copper plate) arranged on opposite sides (annotated Figure 2) of the insulating layers (Fig. 2, 212/262, ceramic plate), facing an outside of the power module (annotated Figure 2).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20200111721 A1 – Figure 1
STATEMENT OF RELEVANCE – A view showing a structure of a power module comprising upper substrate, and lower substrate and a semiconductor device is positioned in between the upper and lower substrate.
US 20210358829 A1 – Figure 3
STATEMENT OF RELEVANCE – A cross-sectional view illustrating a spacer includes: first metal layers, and a second metal layer disposing between the first metal layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON T FLETCHER can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
