DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 11/14/2023 and 11/29/2023 are in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Woo-Yong Jeon, (hereinafter JEON), US 20160126157 A1, in view of Nobuhisa Yamaguchi et al, (hereinafter YAMAGUCHI), US 20120147641 A1.
Regarding Claim 1, JEON teaches a power module (Fig. 2, 200, cooling power module) comprising:
a first substrate (Fig. 2, 210, low-end terminal) and a second substrate (Fig. 2, 260, upper-end terminal), each of which includes an insulating layer (Fig. 2, 212/262, ceramic plate) and a metal layer (Fig. 2, 213/261, copper plate) disposed on one surface of the insulating layer (Fig. 2, 212/262, ceramic plate), wherein the metal layers (Fig. 2, 213/261, copper plate) are arranged and spaced from each other to face each other in a first direction (annotated Figure 2);
a semiconductor chip (Fig. 2, 231, power semiconductor chip) disposed between the first substrate (Fig. 2, 210, low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal) in the first direction (annotated Figure 2); and
a via spacer (annotated Figure 2) extending in the first direction (annotated Figure 2), electrically connecting (Fig. 2, solder) the first substrate (Fig. 2, 210, low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal), between the first substrate (Fig. 2, 210, low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal) and separated from the semiconductor chip (Fig. 2, 231, power semiconductor chip) with a predetermined distance (annotated Figure 2) in a second direction crossing the first direction (annotated Figure 2).
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JEON does not explicitly disclose a power module comprising: wherein the via spacer includes: a first portion electrically connected to the first substrate; a second portion electrically connected to the second substrate; and a resistor portion including a resistance value greater than resistance values of the first portion and the second portion and arranged between the first portion and the second portion in the first direction.
YAMAGUCHI teaches a power module (Fig. 2, PM) comprising:
wherein the via spacer (annotated Figure 2) includes:
a first portion (Fig. 2, 24p/24n, via conductor) electrically connected (Fig. 2, 26, wiring layer) to the first substrate (Fig. 2, 30, the conductor);
a second portion (Fig. 2, 32p/32n, via conductor) electrically connected (Fig. 2, 34p/34n, wiring layer) to the second substrate (Fig. 2, 40p/40n, the conductor); and
a resistor portion (annotated Figure 2, 22p/22n, semiconductor chip, [0049]) including a resistance value greater than resistance values (see Notes below) of the first portion (Fig. 2, 24p/24n, via conductor) and the second portion (Fig. 2, 32p/32n, via conductor) and arranged between (annotated Figure 2) the first portion (Fig. 2, 24p/24n, via conductor) and the second portion (Fig. 2, 32p/32n, via conductor) in the first direction (annotated Figure 2). [NOTE: According to Wikipedia, the electrical resistance or resistivity of a semiconductor is greater than the conductor; please see https://en/wikipedia.org/wiki/Electrical_resistivity_and_conductivity].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified JEON to incorporate the teachings of YAMAGUCHI, such that a power module comprising: wherein the via spacer includes: a first portion electrically connected to the first substrate; a second portion electrically connected to the second substrate; and a resistor portion including a resistance value greater than resistance values of the first portion and the second portion and arranged between the first portion and the second portion in the first direction. The said arrangement of a semiconductor chip having a switching element (Swp/Swn) and a floating diode (FDp/FDn) in parallel configuration with a snubber resistor (18p), to form a snubber circuit, enables to reduce the parasitic inductance, while the heat generated from the snubber circuit is dissipated through the conductor on both sides of the semiconductor chip (YAMAGUCHI, Figures 1-2, [0003-0008]).
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Regarding Claim 2, JEON as modified by YAMAGUCHI teaches the power module of claim 1.
YAMAGUCHI further teaches the power module (Fig. 2, PM), wherein the first portion (Fig. 2, 24p/24n, via conductor) and the second portion (Fig. 2, 32p/32n, via conductor) extend in a same length in the first direction (annotated Figure 2), and the resistor portion (annotated Figure 2, 22p/22n, semiconductor chip, [0049]) is disposed at a center portion of the via spacer (annotated Figure 2).
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Regarding Claim 3, JEON as modified by YAMAGUCHI teaches the power module of claim 1.
YAMAGUCHI further teaches the power module (Fig. 2, PM), wherein the resistor portion (annotated Figure 2, 22p/22n, semiconductor chip, [0049]) extends in a same length (annotated Figure 2) as the first portion (Fig. 2, 24p/24n, via conductor) and the second portion (Fig. 2, 32p/32n, via conductor) in the second direction (annotated Figure 2).
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Regarding Claim 4, JEON as modified by YAMAGUCHI teaches the power module of claim 1.
YAMAGUCHI further teaches the power module (Fig. 2, PM), wherein potentials (Figs. 1-2, high-potential side wiring (Lp)/low-potential side wiring (Ln)/intermediate wiring (Lo), [0038-0041]) of the first portion (Fig. 2, 24p/24n, via conductor) and the second portion (Fig. 2, 32p/32n, via conductor) are transferred (Fig. 2, high-potential side, Lp, low-potential side Ln, and the intermediate wiring Lo, [0039-0041]); to at least one of the first substrate (Fig. 2, 30, the conductor) and the second substrate (Fig. 2, 40, the conductor).
Regarding Claim 5, JEON as modified by YAMAGUCHI teaches the power module of claim 4.
YAMAGUCHI further teaches the power module (Fig. 2, PM), wherein at least one of the first substrate (Fig. 2, 30, the conductor) and the second substrate (Fig. 2, 40, the conductor) includes a plurality of patterns (Fig. 2, 42p/42n or 42#, patterning of the insulating film, [0095]) individually formed to receive the potentials (Fig. 2, 42p/42n is connected to the 40p/40n and 40p/40n having high-potential side and low-potential side, [0039-0041]).
Regarding Claim 6, JEON as modified by YAMAGUCHI teaches the power module of claim 5.
YAMAGUCHI further teaches the power module (Fig. 2, PM), wherein the first portion (Fig. 2, 24p/24n, via conductor) and the second portion (Fig. 2, 32p/32n, via conductor) are each connected to the plurality of patterns (Fig. 2, 42p/42n or 42#, patterning of the insulating film, [0095]) through a wire (Fig. 2, 38p/38n, the conductor).
Regarding Claim 7, JEON as modified by YAMAGUCHI teaches the power module of claim 5.
YAMAGUCHI further teaches the power module (Fig. 2, PM), wherein the plurality of patterns (Fig. 2, 42p/42n or 42#, patterning of the insulating film, [0095]) are connected to a signal lead (Figs. 2/16, bonding wires, G, KE, [0136]) transferring the received potentials to an outside (Fig2. 2/16, 68p/68n, terminals, [0136]) of the power module (Figs. 2/16, PM).
Regarding Claim 8, JEON as modified by YAMAGUCHI teaches the power module of claim 1.
JEON further teaches the power module (Fig. 2, 200, cooling power module), wherein the via spacer (Fig. 2, 251-1/251-2, first/second horizontal spacers, [0044]) receives a first current (Fig. 2, current flows from the positive electrode terminal, (+), 213-1 to the first output terminal, 263-1 of the upper-end terminal 260 through the first power semiconductor chip, 231, and the first horizontal spacer, 251-1, [0053]) passed through the semiconductor chip (Fig. 2, 231, first power semiconductor chip) through one of the first substrate (Fig. 2, 210, low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal) and transfers the received first current to another of the first substrate (Fig. 2, 210, low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal).
Regarding Claim 9, JEON as modified by YAMAGUCHI and JEON teaches the power module of claim 8.
YAMAGUCHI further teaches the power module (Fig. 2, PM), wherein the resistor portion (annotated Figure 2, 22p/22n, semiconductor chip, [0049]) receives a second current for sensing the first current, separately from the first current (Fig. 2, the sense terminal is provided to output a minute electric current that has a correlation with an electric current flowing between a pair of terminals of the switching element, Swp of semiconductor chip, 22p, [0137]).
Regarding Claim 10, , JEON as modified by YAMAGUCHI and JEON teaches the power module of claim 8.
YAMAGUCHI further teaches the power module (Fig. 2, PM), wherein the second current (Fig. 2, the sense terminal is provided to output a minute electric current, [0137]) includes a current value less than a current of the first current (Fig. 2, high-frequency current is equivalent to large current, [0141]).
Regarding Claim 11, JEON as modified by YAMAGUCHI teaches the power module of claim 1.
JEON teaches a power module (Fig. 2, 200, cooling power module), further including a chip spacer (Fig. 2, 251-1/251-2, horizontal spacer) connecting a first surface (annotated Figure 2) of the semiconductor chip (Fig. 1, 231, power semiconductor chip) to one of the first substrate (Fig. 2, 210 low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal) and a second surface (annotated Figure 2) of the semiconductor chip (Fig. 1, 231, power semiconductor chip) is connected to a remaining (annotated Figure 2) one of the first substrate (Fig. 2, 210 low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal).
Regarding Claim 12, JEON as modified by YAMAGUCHI teaches the power module of claim 11.
JEON teaches a power module (Fig. 2, 200, cooling power module), wherein the chip spacer (Fig. 2, 251-1/251-2, horizontal spacer) is connected to the first surface (annotated Figure 2) of the semiconductor chip (Fig. 1, 231, power semiconductor chip) and the one of the first substrate (Fig. 2, 210 low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal) by an adhesive (Fig. 2, solder) and the second surface (annotated Figure 2) of the semiconductor chip (Fig. 1, 231, power semiconductor chip) is connected to the remaining (annotated Figure 2) one of the first substrate (Fig. 2, 210 low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal) by the adhesive (Fig. 2, solder).
Regarding Claim 13, , JEON as modified by YAMAGUCHI teaches the power module of claim 1.
JEON teaches a power module (Fig. 2, 200, cooling power module), wherein the first substrate (Fig. 2, 210 low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal) includes additional metal layers (Fig. 2, 211/263, copper plate) arranged on opposite sides (annotated Figure 2) of the insulating layers (Fig. 2, 212/262, ceramic plate), facing an outside of the power module (annotated Figure 2).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20200111721 A1 – Figure 1
STATEMENT OF RELEVANCE – Structure of a power module with via spacer (500) and a semiconductor chip (300) between first substrate (100) and second substrate (200).
US 20170216948 A1 – Figure 1
STATEMENT OF RELEVANCE – Structure of a power module, having solder (60) which is fusible metal alloy for bonding, used as the bonding process that couples the chip to the substrate.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2812
/CHRISTINE S. KIM/ Supervisory Patent Examiner, Art Unit 2812