DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment with respect to claim(s) 1 filed on 6/15/2026 have been fully considered and entered. The previously presented claim(s) 2-13 have been considered.
Response to Arguments
Applicant's arguments filed 04/21/2026 have been fully considered but they are not persuasive.
Regarding Independent Claim 1. The Applicant argues (see Remarks, page 5) that, in the prior art, JEON and YAMAGUCHI fail to disclose or suggest the inventive feature of claim 1, specifically, YAMAGUCHI does not each the “via spacer separated from the semiconductor chip with the predetermined distance in the second direction crossing the first direction.” The Applicant further argues (see Remarks, page 6) that the Examiner’s mapped elements of via spacer, such as 24p/24n, and 32p/32n as equated to first portion and the second portion, and 22p/22n as equated to resistor portion as in the instant application are the “semiconductor chips” that are part of the chip mounting structure, and further constitute “the chip spacer” that directly connects the semiconductor chip to the substrates. Moreover, the Applicant reiterated that the 22p/22n of YAMAGUCHI is the active semiconductor chip and not to be considered or equated to the resistor portion as claimed by the instant application. The Examiner respectfully disagreed, and the arguments are not persuasive because the “via spacer” arrangements are represented by three portions, out of which the first and second portions are equated to via conductors, 24p/24n, and 32p/32n respectively. According to paragraphs [0015] and [0061] of the instant application, the first portion, 310, and the second portion, 320, are electrically connected to the first substrate, 110 and second substrate, 120. Additionally, according to paragraph [0067], when the current flown into the first portion, 310 of the power module passes through the resistor portion, 330, and then exits through the second portion, 320, a voltage drop occurs due to the resistance in the resistor portion, 330, leading to the generation of a potential difference (or voltage drop) between the first portion, 310, and the second portion, 320. Based on the aforementioned paragraph references, it appears the first portion, 310 and the second portion, 320 are the conductors, therefore, equating 24p/24n and 32p/32n as via conductors of the YAMAGUCHI art to the first portion 310, and 320 of the instant applications are appropriate as for the POSITA is concerned. Though 22p/22n is a semiconductor chip, according to YAMAGUCHI’s paragraph [0173], the power module (PM) includes, the low-potential side switching element, (Swp as labeled in Figure 2) as the “first flowing restriction element”, the free wheel diode (FDp as labeled in Figure 2) connected in antiparallel with the switching element (Swp), and the series connection unit including the high-potential side free wheel diode (FDp) as the “second flowing restriction element.” The role of “flowing restriction element” according to [0005] of YAMAGUCHI art, is to allow or restrict the flowing path of an electric current. According to [0195], YAMAGUCHI, the first surface and a second surface of the first semiconductor chip (22p/22n), provide ends of the “flowing path of the electric current of the first/second flowing restriction element.” This is identical to the paragraph [0087] of the instant application, in the power module, the via spacer, including the “resistor portion (330)” doubles as the electrical connection and the “current” sensing between the first substrate (110) and the second substrate (120). Therefore, equating “22p/22n as a flowing restriction element” of YAMAGUCHI art to“ 330 as a resistor portion” of the instant application appears to be appropriate, because the functionality of Swp/FDp, the flowing restriction element, is similar to the resistor portion to control the flowing path of current as discussed above. The arrangement of via spacers as annotated (Fig. 2) in the previous office action (page 6) filed on 01/21/2026 is appropriate with respect to the via spacer as claimed in Claim 1 of the instant application, and therefore, the Examiner maintains the rejection of the record.
Regarding Claims 2-13. The dependent claims 2-13 follow similar arguments as Claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Woo-Yong Jeon, (hereinafter JEON), US 20160126157 A1, in view of Nobuhisa Yamaguchi et al, (hereinafter YAMAGUCHI), US 20120147641 A1.
Regarding Claim 1, JEON teaches a power module (Fig. 2, 200, cooling power module) comprising:
a first substrate (Fig. 2, 210, low-end terminal) and a second substrate (Fig. 2, 260, upper-end terminal), each of which includes an insulating layer (Fig. 2, 212/262, ceramic plate) and a metal layer (Fig. 2, 213/261, copper plate) disposed on a surface of the insulating layer (Fig. 2, 212/262, ceramic plate), wherein the metal layers (Fig. 2, 213/261, copper plate) are arranged and spaced from each other to face each other in a first direction (annotated Figure 2);
a semiconductor chip (Fig. 2, 231, power semiconductor chip) disposed between the first substrate (Fig. 2, 210, low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal) in the first direction (annotated Figure 2); and
a via spacer (annotated Figure 2) extending in the first direction (annotated Figure 2), electrically connecting (Fig. 2, solder) the first substrate (Fig. 2, 210, low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal), between the first substrate (Fig. 2, 210, low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal) and separated from the semiconductor chip (Fig. 2, 231, power semiconductor chip) with a predetermined distance (annotated Figure 2) in a second direction crossing the first direction (annotated Figure 2).
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JEON does not explicitly disclose a power module comprising: wherein the via spacer includes: a first portion electrically connected to the first substrate; a second portion electrically connected to the second substrate; and a resistor portion including a resistance value greater than resistance values of the first portion and the second portion and arranged between the first portion and the second portion in the first direction.
YAMAGUCHI teaches a power module (Fig. 2, PM) comprising:
wherein the via spacer (annotated Figure 2) includes:
a first portion (Fig. 2, 24p/24n, via conductor) electrically connected (Fig. 2, 26, wiring layer) to the first substrate (Fig. 2, 30, the conductor);
a second portion (Fig. 2, 32p/32n, via conductor) electrically connected (Fig. 2, 34p/34n, wiring layer) to the second substrate (Fig. 2, 40p/40n, the conductor); and
a resistor portion (annotated Figure 2, 22p/22n, semiconductor chip, [0049]) including a resistance value greater than resistance values (see Notes below) of the first portion (Fig. 2, 24p/24n, via conductor) and the second portion (Fig. 2, 32p/32n, via conductor) and arranged between (annotated Figure 2) the first portion (Fig. 2, 24p/24n, via conductor) and the second portion (Fig. 2, 32p/32n, via conductor) in the first direction (annotated Figure 2). [NOTE: According to Wikipedia, the electrical resistance or resistivity of a semiconductor is greater than the conductor; please see https://en/wikipedia.org/wiki/Electrical_resistivity_and_conductivity].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified JEON to incorporate the teachings of YAMAGUCHI, such that a power module comprising: wherein the via spacer includes: a first portion electrically connected to the first substrate; a second portion electrically connected to the second substrate; and a resistor portion including a resistance value greater than resistance values of the first portion and the second portion and arranged between the first portion and the second portion in the first direction. The said arrangement of a semiconductor chip having a switching element (Swp/Swn) and a floating diode (FDp/FDn) in parallel configuration with a snubber resistor (18p), to form a snubber circuit, enables to reduce the parasitic inductance, while the heat generated from the snubber circuit is dissipated through the conductor on both sides of the semiconductor chip (YAMAGUCHI, Figures 1-2, [0003-0008]).
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Regarding Claim 2, JEON as modified by YAMAGUCHI teaches the power module of claim 1.
YAMAGUCHI further teaches the power module (Fig. 2, PM), wherein the first portion (Fig. 2, 24p/24n, via conductor) and the second portion (Fig. 2, 32p/32n, via conductor) extend in a same length in the first direction (annotated Figure 2), and the resistor portion (annotated Figure 2, 22p/22n, semiconductor chip, [0049]) is disposed at a center portion of the via spacer (annotated Figure 2).
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Regarding Claim 3, JEON as modified by YAMAGUCHI teaches the power module of claim 1.
YAMAGUCHI further teaches the power module (Fig. 2, PM), wherein the resistor portion (annotated Figure 2, 22p/22n, semiconductor chip, [0049]) extends in a same length (annotated Figure 2) as the first portion (Fig. 2, 24p/24n, via conductor) and the second portion (Fig. 2, 32p/32n, via conductor) in the second direction (annotated Figure 2).
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Regarding Claim 4, JEON as modified by YAMAGUCHI teaches the power module of claim 1.
YAMAGUCHI further teaches the power module (Fig. 2, PM), wherein potentials (Figs. 1-2, high-potential side wiring (Lp)/low-potential side wiring (Ln)/intermediate wiring (Lo), [0038-0041]) of the first portion (Fig. 2, 24p/24n, via conductor) and the second portion (Fig. 2, 32p/32n, via conductor) are transferred (Fig. 2, high-potential side, Lp, low-potential side Ln, and the intermediate wiring Lo, [0039-0041]); to at least one of the first substrate (Fig. 2, 30, the conductor) and the second substrate (Fig. 2, 40, the conductor).
Regarding Claim 5, JEON as modified by YAMAGUCHI teaches the power module of claim 4.
YAMAGUCHI further teaches the power module (Fig. 2, PM), wherein at least one of the first substrate (Fig. 2, 30, the conductor) and the second substrate (Fig. 2, 40, the conductor) includes a plurality of patterns (Fig. 2, 42p/42n or 42#, patterning of the insulating film, [0095]) individually formed to receive the potentials (Fig. 2, 42p/42n is connected to the 40p/40n and 40p/40n having high-potential side and low-potential side, [0039-0041]).
Regarding Claim 6, JEON as modified by YAMAGUCHI teaches the power module of claim 5.
YAMAGUCHI further teaches the power module (Fig. 2, PM), wherein the first portion (Fig. 2, 24p/24n, via conductor) and the second portion (Fig. 2, 32p/32n, via conductor) are each connected to the plurality of patterns (Fig. 2, 42p/42n or 42#, patterning of the insulating film, [0095]) through a wire (Fig. 2, 38p/38n, the conductor).
Regarding Claim 7, JEON as modified by YAMAGUCHI teaches the power module of claim 5.
YAMAGUCHI further teaches the power module (Fig. 2, PM), wherein the plurality of patterns (Fig. 2, 42p/42n or 42#, patterning of the insulating film, [0095]) are connected to a signal lead (Figs. 2/16, bonding wires, G, KE, [0136]) transferring the received potentials to an outside (Fig2. 2/16, 68p/68n, terminals, [0136]) of the power module (Figs. 2/16, PM).
Regarding Claim 8, JEON as modified by YAMAGUCHI teaches the power module of claim 1.
JEON further teaches the power module (Fig. 2, 200, cooling power module), wherein the via spacer (Fig. 2, 251-1/251-2, first/second horizontal spacers, [0044]) receives a first current (Fig. 2, current flows from the positive electrode terminal, (+), 213-1 to the first output terminal, 263-1 of the upper-end terminal 260 through the first power semiconductor chip, 231, and the first horizontal spacer, 251-1, [0053]) passed through the semiconductor chip (Fig. 2, 231, first power semiconductor chip) through one of the first substrate (Fig. 2, 210, low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal) and transfers the received first current to another of the first substrate (Fig. 2, 210, low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal).
Regarding Claim 9, JEON as modified by YAMAGUCHI and JEON teaches the power module of claim 8.
YAMAGUCHI further teaches the power module (Fig. 2, PM), wherein the resistor portion (annotated Figure 2, 22p/22n, semiconductor chip, [0049]) receives a second current for sensing the first current, separately from the first current (Fig. 2, the sense terminal is provided to output a minute electric current that has a correlation with an electric current flowing between a pair of terminals of the switching element, Swp of semiconductor chip, 22p, [0137]).
Regarding Claim 10, , JEON as modified by YAMAGUCHI and JEON teaches the power module of claim 8.
YAMAGUCHI further teaches the power module (Fig. 2, PM), wherein the second current (Fig. 2, the sense terminal is provided to output a minute electric current, [0137]) includes a current value less than a current of the first current (Fig. 2, high-frequency current is equivalent to large current, [0141]).
Regarding Claim 11, JEON as modified by YAMAGUCHI teaches the power module of claim 1.
JEON teaches a power module (Fig. 2, 200, cooling power module), further including a chip spacer (Fig. 2, 251-1/251-2, horizontal spacer) connecting a first surface (annotated Figure 2) of the semiconductor chip (Fig. 1, 231, power semiconductor chip) to one of the first substrate (Fig. 2, 210 low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal) and a second surface (annotated Figure 2) of the semiconductor chip (Fig. 1, 231, power semiconductor chip) is connected to a remaining (annotated Figure 2) one of the first substrate (Fig. 2, 210 low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal).
Regarding Claim 12, JEON as modified by YAMAGUCHI teaches the power module of claim 11.
JEON teaches a power module (Fig. 2, 200, cooling power module), wherein the chip spacer (Fig. 2, 251-1/251-2, horizontal spacer) is connected to the first surface (annotated Figure 2) of the semiconductor chip (Fig. 1, 231, power semiconductor chip) and the one of the first substrate (Fig. 2, 210 low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal) by an adhesive (Fig. 2, solder) and the second surface (annotated Figure 2) of the semiconductor chip (Fig. 1, 231, power semiconductor chip) is connected to the remaining (annotated Figure 2) one of the first substrate (Fig. 2, 210 low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal) by the adhesive (Fig. 2, solder).
Regarding Claim 13, , JEON as modified by YAMAGUCHI teaches the power module of claim 1.
JEON teaches a power module (Fig. 2, 200, cooling power module), wherein the first substrate (Fig. 2, 210 low-end terminal) and the second substrate (Fig. 2, 260, upper-end terminal) includes additional metal layers (Fig. 2, 211/263, copper plate) arranged on opposite sides (annotated Figure 2) of the insulating layers (Fig. 2, 212/262, ceramic plate), facing an outside of the power module (annotated Figure 2).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20210359592 A1 – Figure 1
STATEMENT OF RELEVANCE – A connection structure, 10 of a snubber circuit within a semiconductor device, having a conductive spacer, 30, and an electrode 22 connected to the first substrate, 13 and the second substrate, 14.
US 10002821 B1 – Figure 5C
STATEMENT OF RELEVANCE – A cross-sectional side view representations, illustrating a spacer (53) is connected to the first substrate (51) and the second substrate (54) as a semiconductor chip package.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON T FLETCHER can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SESHA SAIRAMAN SRINIVASAN/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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