CTNF 18/389,613 CTNF 100436 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) submitted on 12/19/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner. Election/Restrictions Applicant’s election of species 1 with partial traverse in the reply filed on 5/15/2026 is acknowledged. The traversal is on the ground(s) that claims 16-19 are generic or pertain to species 1 Applicant substantively argues: “Claim 16 does not specify whether the electronic component is positioned in an overhang or extends from an upper surface of the interposer.” And “claim 19 recites, "wherein extending the conductive element between the contact pad of the substrate and the conductive structure includes extending a wire bond between the contact pad of the substrate and the conductive structure." Notably, this arrangement is illustrated in each of FIGS. 2, 6, 7C, 8C, and 9-11, which the Office identifies as being directed to Species 1” The Examiner finds these arguments to be fully persuasive . Therefore the Examiner will examine claims 1-8, 10, 11-12, 14, and 16-19. Claim Objections 07-29-01 AIA Claim 17 is objected to because of the following informalities: Claim 17 recites, “wherein securing the additional electronic component to the conductive structure including securing the additional electronic component to the conductive structure of the interposer on a first side of the interposer”. The Examiner believes the Applicant intended to recite, “wherein securing the additional electronic component to the conductive structure includes securing the additional electronic component to the conductive structure of the interposer on a first side of the interposer” in order for the claim to have correct grammar . Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: 07-08-aia AIA A person shall be entitled to a patent unless –(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA A person shall be entitled to a patent unless –(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-4, 6-7, and 10 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Lee et al US 20150115438 A1. Lee et al will be referenced to as Lee henceforth . Regarding Claim 1, Lee teaches: “A microelectronic device package comprising: a stack of semiconductor dies (semiconductor chip unit 200, [0039], FIG. 2) positioned over a substrate (base substrate 10, [0039], FIG. 2) ; an interposer structure coupled to the stack of semiconductor dies (insulating material layer 400, [0048], FIG. 2) ; and an electronic component directly coupled to the interposer structure (semiconductor chip 300, [0039], FIG. 2) and electrically coupled to the substrate through an electrical connection between the interposer structure and the substrate (third pad 302, third bonding wire 306, [0045], FIG. 2) .” Regarding Claim 2, Lee teaches: “The microelectronic device package of claim 1, wherein the electrical connection comprises a wire bond (bonding wire 306, [0045], FIG. 2) .” Regarding Claim 3, Lee teaches: “The microelectronic device package of claim 1, wherein the electrical connection comprises a direct connection ([0045]: 306 is directly connected to connection pad 18 which is on the substrate.) .” Regarding Claim 4, Lee teaches: “The microelectronic device package of claim 1, wherein the interposer structure is positioned between the stack of semiconductor dies and a microelectronic device (first semiconductor chip 100d, [0045], FIG. 2) .” Regarding Claim 6, Lee teaches: “The microelectronic device package of claim 1, wherein the stack of semiconductor dies defines an overhang region between the stack of semiconductor dies and the substrate (annotated FIG. 2 #1) .” PNG media_image1.png 294 546 media_image1.png Greyscale Annotated FIG. 2 #1 Regarding Claim 7, Lee teaches: “The microelectronic device package of claim 6, wherein the electronic component is positioned within the overhang region (annotated FIG. 2 #1) .” Regarding Claim 10, Lee teaches: “The microelectronic device package of claim 1, wherein the electronic component comprises one or more of a capacitor, an inductor, and a resistor ([0056]: 300 may be DRAM. DRAM comprises a capacitor to hold a bit of data.) . ” 07-15 AIA Claim s 1, 5 and 11-12 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by another interpretation of Lee US 20150115438 A1. The second interpretation of Lee et al will be referenced to as Lee #2 henceforth . Regarding Claim 1, Lee #2 teaches: “A microelectronic device package comprising: a stack of semiconductor dies (semiconductor chip unit 100, [0039], FIG. 2) positioned over a substrate (base substrate 10, [0039], FIG. 2) ; an interposer structure coupled to the stack of semiconductor dies (insulating material layer 400, [0048], FIG. 2) ; and an electronic component directly coupled to the interposer structure (semiconductor chip 300, [0039], FIG. 2) and electrically coupled to the substrate through an electrical connection between the interposer structure and the substrate (third pad 302, third bonding wire 306, [0045], FIG. 2) .” Regarding Claim 5, Lee #2 teaches: “The microelectronic device package of claim 1, wherein the interposer structure is positioned over the stack of semiconductor dies (FIG. 2) .” Regarding Claim 11, Lee #2 teaches: “An electronic system (FIG. 2) , comprising: an input device (input/output device 1220 (a keyboard), [0130], FIG. 31) ; an output device (input/output device 1220 (a display), [0130], FIG. 31) ; a processor device operably coupled to the input device and the output device (controller 1210 (the microprocessor), [0130], FIG. 31: the controller may comprise a microprocessor.) ; and a memory device operably coupled to the processor device and comprising (memory device 1230, [0131-0132], FIG. 31: 1230 is coupled to 1210 by a bus 1250) : at least one semiconductor die (semiconductor chip unit 100, [0039], FIG. 2) secured to a substrate (base substrate 10, [0039], FIG. 2) ; an interposer (insulating material layer 400, [0048], FIG. 2) including a conductive structure positioned over the at least one semiconductor die (third pad 302, [0045]) ; and an additional electronic component secured to the interposer (semiconductor chip 300, [0039], FIG. 2) , the additional electronic component operably coupled to the substrate through the conductive structure of the interposer (third bonding wire 306, connection pad 18, [0045]: 300 is connected to substrate 10 by 302, 306, and connection pad 18.) .” Regarding Claim 12, Lee #2 teaches: “The electronic system of claim 11, wherein the conductive structure of the interposer is coupled to the substrate through a wire bond (FIG. 2) .” 07-15-03-aia AIA Claim s 16-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Baek et al US 20240079380 A1. Baek et al will be referenced to as Baek henceforth . Regarding Claim 16, Baek teaches: “A method of assembling a stacked microelectronic device package, the method comprising: providing a microelectronic device (first chip stack CS1, [0017], FIG. 7A) ; coupling the microelectronic device to a substrate (base substrate 500, [0117], FIG. 7A) ; providing an interposer (die adhesive film 390, 326, [0038], [0050], FIG. 7D) including a conductive structure (connection lines 322, FIG. 7D) ; positioning the interposer over the microelectronic device (FIG. 7D) ; securing an additional electronic component to the conductive structure of the interposer (connection vias 324, [0038], FIG. 7D) ; and connecting the conductive structure of the interposer to a contact pad of the substrate (bonding wires 400, [0046], FIG. 7E) .” Regarding Claim 17, Baek teaches: “The method of claim 16, wherein securing the additional electronic component to the conductive structure including securing the additional electronic component to the conductive structure of the interposer on a first side of the interposer (FIG. 7E: The first side is the top side of the interposer.) ” Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 8, 14 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding Claim 8, Lee, Lee #2 and Baek fail to explicitly teach: “wherein the electronic component is suspended from the interposer structure” In view of the rest of the limitations of claim 1 . Lee, Lee #2 and Baek fail to explicitly teach the above limitation because the limitation cannot be found in the prior art of record . This is because in Lee, Lee #2 and Baek, that additional electronic component is over the interposer and not beneath it. Therefore, the additional electronic component cannot be suspended from the interposer. The Examiner did find art in which an electrical component is suspended from above such as: US 9761568 B2. However, the Examiner did not find it reasonable to consider the chips in the semiconductor stack to be interposers as that is not the purpose of those chips. The Examiner did not find prior art which one of ordinary skill in the art would use alone or would find obvious to combine with the invention of Lee, Lee #2 and Baek to reach all of the limitations of the claim. Regarding Claim 14, Lee, Lee #2 and Baek fails to explicitly teach : “wherein the conductive structure includes a first contact pad in a first surface of the interposer and a second contact pad in a second surface of the interposer opposite the first surface” In view of the rest of the limitations of claim 11. Lee, Lee #2 and Baek fail to explicitly teach the above limitation because the limitation cannot be found in the prior art of record . This is because the conductive structure of any one of Lee, Lee #2, and Baek does not extend to both sides of the interposer. The Examiner did not find prior art which one of ordinary skill in the art would use alone or would find obvious to combine with the invention of Lee, Lee #2 and Baek to reach all of the limitations of the claim. Regarding Claim 18, Lee, Lee #2 and Baek fails to explicitly teach : “wherein connecting the conductive structure of the interposer to the contact pad of the substrate includes extending a conductive element between the contact pad of the substrate and the conductive structure of the interposer on a second side of the interposer opposite the first side of the interposer” In view of the rest of the limitations of claim 18. Lee, Lee #2 and Baek fail to explicitly teach the above limitation because the limitation cannot be found in the prior art of record . This is because the conductive structure of any one of Lee, Lee #2, and Baek does not extend to both sides of the interposer. The Examiner did not find prior art which one of ordinary skill in the art would use alone or would find obvious to combine with the invention of Lee, Lee #2 and Baek to reach all of the limitations of the claim. Regarding Claim 19, this claim depends on claim 18 and is objectionable for the same reasons. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812 /William B Partridge/Supervisory Patent Examiner, Art Unit 2812 Application/Control Number: 18/389,613 Page 2 Art Unit: 2812 Application/Control Number: 18/389,613 Page 3 Art Unit: 2812 Application/Control Number: 18/389,613 Page 4 Art Unit: 2812 Application/Control Number: 18/389,613 Page 5 Art Unit: 2812 Application/Control Number: 18/389,613 Page 6 Art Unit: 2812 Application/Control Number: 18/389,613 Page 7 Art Unit: 2812 Application/Control Number: 18/389,613 Page 8 Art Unit: 2812 Application/Control Number: 18/389,613 Page 9 Art Unit: 2812 Application/Control Number: 18/389,613 Page 10 Art Unit: 2812 Application/Control Number: 18/389,613 Page 11 Art Unit: 2812 Application/Control Number: 18/389,613 Page 12 Art Unit: 2812
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