DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 4 as shown in fig. 64A,B (claims 1-6, 12-15 readable thereon) in the reply filed on 4/27/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 12, 14, and 15 recites the limitation “the channel layer” at the third from last line of the claim 12 and the first line of claims 14 and 15. Is it unclear as to what element said limitation is referring to.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 12-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamazaki et al. (US PGPub 2015/0348909; hereinafter “Yamazaki”).
Re claim 1: Yamazaki teaches (e.g. fig. 1) an integrated circuit (IC) structure, comprising: a front-side device (Tr1), comprising: a body (region of substrate 103 under Tr1; hereinafter “B”) of monocrystalline material (single crystal substrate 101; e.g. paragraph 176) adjacent to an isolation dielectric (103); a gate stack (113,115) adjacent to a sidewall (sidewall adjacent 103; hereinafter “S”) of the body (B), the gate stack (113,115) including a gate electrode (115) separated from the sidewall (S) by a gate dielectric (113); and a source (117b) and a drain (117a) coupled to the body (B) on opposite sides of the gate stack (113,115); a front-side interconnect metallization layer (171a) over a front-side (bottom surface of 101) of the body (B) and coupled to at least one of the source, drain (117a), or gate electrode; and a back-side device (Tr2), comprising: a back-side device layer (131,133a) over a back-side surface (upper surface of 101) of the body (B), opposite (171a is opposite upper surface of 101) the front-side interconnect metallization layer (171a), wherein the back-side device layer (131,133a) comprises an oxide semiconductor material (oxide semiconductor material; e.g. paragraph 153), or a metal chalcogenide material; and a back-side device terminal (161a) electrically coupled to the back-side device layer (131).
Re claim 2: Yamazaki teaches the IC structure of claim 1, wherein the back-side device (Tr2) is a transistor (transistor Tr2; e.g. paragraph 126) and the back-side device terminal is one of a source, drain (161a), or gate terminal of a transistor.
Re claim 3: Yamazaki teaches the IC structure of claim 2, wherein the transistor (Tr2 is formed form a semiconductor film 131; e.g. paragraph 128) is one of a thin film transistor (TFT) or a tunneling field effect transistor (TFET).
Re claim 4: Yamazaki teaches the IC structure of claim 3, wherein the back-side device (Tr2 is formed form a semiconductor film 131; e.g. paragraph 128) is a TFT and the back- side device layer (131,133a) comprises a metal (133a) and a chalcogen (131 is an oxide semiconductor and has oxygen).
Re claim 5: Yamazaki teaches the IC structure of claim 4, wherein the back-side device (Tr2 is formed form a semiconductor film 131; e.g. paragraph 128) is a TFT and back-side device layer (131,133a) comprises a metal (133a) and a chalcogen (131 is an oxide semiconductor and has oxygen).
Re claim 6: Yamazaki teaches the IC structure of claim 5, wherein the back-side device layer (131,133a) comprises oxygen, indium, gallium, and zinc (IGZO is a known oxide semiconductor).
Re claim 12: Yamazaki teaches (e.g. fig. 1) a vertically stacked integrated circuit (IC) device structure, comprising: a field effect transistor (FET) (Tr1), comprising: a monocrystalline silicon body (single crystal silicon substrate 101; e.g. paragraph 176) adjacent to an isolation dielectric (103); a gate stack (113,115) adjacent to a sidewall (sidewall adjacent 103; hereinafter “S”) of the body (B), the gate stack (113,115) including a gate electrode (115) separated from the sidewall (S) by a gate dielectric (113); and a source (117b) and a drain (117a) coupled to the body (B) on opposite sides of the gate stack (113,115); a front-side interconnect metallization layer (171a) over a front-side (bottom surface of 101) of the body (B) and coupled to at least one of the source, drain (117a), or gate electrode; and a thin film transistor (TFT) (Tr2), comprising: a channel material layer (131,133a) over a back-side surface (upper surface of 101) of the body (B), opposite (171a is opposite upper surface of 101) the front-side interconnect metallization layer (171a), wherein the channel layer (131,133a) comprises a metal and a chalcogen or comprises a metal and oxygen (oxide semiconductor material; e.g. paragraph 153); and a back-side device terminal (161a) electrically coupled to the channel material layer (131,133a).
Re claim 13: Yamazaki teaches the IC device structure of claim 12, wherein the source or drain (117a) are in direct contact with the back-side device terminal (161a).
Re claim 14: Yamazaki teaches the IC device structure of claim 13, wherein the channel layer (131,133a) comprises oxygen and at least one of indium, gallium, or zinc (IGZO is a known oxide semiconductor).
Re claim 15: Yamazaki teaches the IC device structure of claim 14, wherein the channel layer (131,133a) comprises oxygen, indium, gallium and zinc (IGZO is a known oxide semiconductor).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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