DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, US 2017/0358558.
Regarding Claim 1, Lee discloses a semiconductor package (1b; Fig. 7; ¶ 0058 “semiconductor package 1b”), comprising:
a base semiconductor chip (100; Fig. 7; ¶ 0026 “semiconductor chip 100”);
a connection semiconductor chip (200; Fig. 7; ¶ 0036 “semiconductor chip 200”) on the base semiconductor chip (Fig. 7; ¶ 0036 “mounted above the upper surface of the first semiconductor chip 100”);
an upper semiconductor chip (400; Fig. 7; ¶ 0038 “semiconductor chip 400”) on the connection semiconductor chip (Fig. 7; ¶ 0038 “mounted above”), the upper semiconductor chip comprising a trench (450; Fig. 7; ¶ 0063 “trench portions 450”);
a filling layer (510; Fig. 7; ¶ 0061 “layer 510”) in the trench (Fig. 7; ¶ 0061 “fill the fourth trench portions 450”); and
a mold layer (190; Fig. 7; ¶ 0041 “molding layer 190”) extending around the upper semiconductor chip (Fig. 7; ¶ 0041 “molding layer 190 may surround the side surfaces of the first to fourth semiconductor chips 100 to 400”).
Lee does not specifically disclose wherein a height of the trench extending into the upper semiconductor chip is larger than a width of the trench.
Lee states ¶ 0048 “the…trench…may have various shapes” and “the width of the…trench…may be variously adjusted”. Also, ¶ 0051 “trench portions…may have various shapes” and “trench portions…may have different shapes”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Lee to have wherein a height of the trench extending into the upper semiconductor chip is larger than a width of the trench, because “trench portions 450 increase a surface area of the upper surface of the fourth semiconductor chip 400 such that heat dissipating characteristics of the semiconductor package…may be improved” (Lee ¶ 0055), “thermal interface material layer 510 may help heat generated in the first to fourth semiconductor chips 100 to 400 be smoothly discharged” (Lee ¶ 0061), and “trench portions 450 in upper portions of the fourth semiconductor chip 400 may increase an area of a region where the fourth semiconductor chip 400 contacts the thermal interface material layer 510. Thus, the heat generated in the first to fourth semiconductor chips 100 to 400 may be effectively transmitted” (Lee ¶ 0063).
Regarding Claim 2, Lee discloses wherein the trench is in an upper portion of the upper semiconductor chip (Fig. 7; ¶ 0063 “trench portions 450 in upper portions of the fourth semiconductor chip 400”).
Regarding Claim 3, Lee discloses wherein the upper semiconductor chip comprises:
a lower pad (442; Fig. 7; ¶ 0039 “connection pads 442”) on the connection semiconductor chip (Fig. 7);
an interconnection structure (440; Fig. 7; ¶ 0039 “layer 420 having wire structures 440”) electrically connected to the lower pad (Fig. 7); and
an upper substrate (410; Fig. 7; ¶ 0039 “semiconductor substrate 410”) on the interconnection structure (Fig. 7),
wherein the trench is in the upper substrate (Fig. 7; ¶ 0063 “trench portions 450 in upper portions”).
Regarding Claim 4, Lee discloses wherein the upper substrate (410) comprises an upper portion (Fig. 7 in this instance the upper portion of upper substrate 410 that has trenches 450) and a lower portion (Fig. 7 in this instance the lower portion of upper substrate 410 that does not have trenches 450), wherein a side surface of the trench is in the upper portion (Fig. 7 the side surfaces of trenches 450 is in the upper portion), and a bottom surface of the trench is a top surface of the bottom portion (Fig. 7 the bottom surface of trenches 450 are a top surface of the bottom portion).
Regarding Claim 5, Lee discloses wherein the upper portion of the upper substrate comprises a flat side surface and a curved side surface (¶ 0056 “trench portions 450 may have substantially the same structure as the first trench portions 150 and 150a to 150c of the first semiconductor chip 100, which are described in connection with FIGS. 1 to 5”, ¶ 0047 “FIGS. 3 to 5 are schematic, plan views of the upper surface of the first semiconductor chip 100 illustrate structures of first trench portions 150a to 150c”, ¶ 0048 “FIG. 3 illustrates that the first trench portion 150a has a rectangular shape, but the first trench portion 150a may have various shapes such as a circle, an oval, a rectangle having rounded corners, or the like.”, in this instance trench 450 is “a rectangle having rounded corners” thereby comprising a flat side surface and a curved side surface in a plan view).
Regarding Claim 6, Lee discloses wherein the filling layer and the mold layer are connected to each other without any interface therebetween (Fig. 7; ¶ 0059 “layer 510…stacked on…an upper surface of the first molding layer 190”, in this instance the upper portion of filing layer 510 contacts mold layer 190), thereby forming a monolithic structure (Fig. 7).
Regarding Claim 7, Lee discloses wherein the filling layer comprises a flat side surface and a curved side surface (¶ 0056 “trench portions 450 may have substantially the same structure as the first trench portions 150 and 150a to 150c of the first semiconductor chip 100, which are described in connection with FIGS. 1 to 5”, ¶ 0047 “FIGS. 3 to 5 are schematic, plan views of the upper surface of the first semiconductor chip 100 illustrate structures of first trench portions 150a to 150c”, ¶ 0048 “FIG. 3 illustrates that the first trench portion 150a has a rectangular shape, but the first trench portion 150a may have various shapes such as a circle, an oval, a rectangle having rounded corners, or the like.”, in this instance the top surface of the filing layer within trench 450 is “a rectangle having rounded corners” thereby comprising a flat side surface and a curved side surface in a plan view).
Regarding Claim 8, Lee discloses wherein the filling layer is spaced apart from the mold layer (Fig. 7 in this instance filling layer 510 that is located within trench 450 is spaced apart from the mold layer 190 by portions of upper semiconductor chip 400).
Regarding Claim 9, Lee discloses wherein a top surface of the filling layer, a top surface of the upper semiconductor chip, and a top surface of the mold layer are coplanar (Fig. 7 in this instance a top surface of filling layer 510 located within trench 450, a top surface of the upper semiconductor chop 400, and a top surface of mold layer 190 are coplanar).
Regarding Claim 10, Lee discloses a semiconductor package (1b; Fig. 7; ¶ 0058 “semiconductor package 1b”), comprising:
a base semiconductor chip (100; Fig. 7; ¶ 0026 “semiconductor chip 100”);
a connection semiconductor chip (200; Fig. 7; ¶ 0036 “semiconductor chip 200”) on the base semiconductor chip (Fig. 7; ¶ 0036 “mounted above the upper surface of the first semiconductor chip 100”);
an upper semiconductor chip (400; Fig. 7; ¶ 0038 “semiconductor chip 400”) on the connection semiconductor chip (Fig. 7; ¶ 0038 “mounted above”);
a filling layer (510; Fig. 7; ¶ 0061 “layer 510”) in the upper semiconductor chip (Fig. 7; ¶ 0061 “fill the fourth trench portions 450”); and
a mold layer (190; Fig. 7; ¶ 0041 “molding layer 190”) extending around the upper semiconductor chip (Fig. 7; ¶ 0041 “molding layer 190 may surround the side surfaces of the first to fourth semiconductor chips 100 to 400”),
wherein the upper semiconductor chip comprises an inner side surface in contact with a side surface (Fig. 7; ¶ 0061 “layer 510…may fill the fourth trench portions 450” therefore filling layer 510 has a side surface) the filling layer (Fig. 7; ¶ 0061 “layer 510…may fill the fourth trench portions 450”, therefore an inner side surface of trench 450 of the upper semiconductor chip 400 is in contact with filling layer 510), a top surface in contact with a bottom surface of the filling layer (Fig. 7; ¶ 0059 “layer 510…stacked on the fourth semiconductor chip 400”; ¶ 0060; therefore the top surface of upper semiconductor chip 400 is in contact with a bottom surface of the filling layer 510), and an outer side surface in contact with the mold layer (Fig. 7; ¶ 0041 “molding layer 190 may surround the side surfaces of…400”, therefore the outer side surface of upper semiconductor chip 400 is in contact with mold layer 190).
Lee does not specifically disclose wherein a length of the inner side surface is longer than a length of the top surface.
Lee states ¶ 0048 “the…trench…may have various shapes” and “the width of the…trench…may be variously adjusted”. Also, ¶ 0051 “trench portions…may have various shapes” and “trench portions…may have different shapes”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Lee to have wherein a length of the inner side surface is longer than a length of the top surface, because “trench portions 450 increase a surface area of the upper surface of the fourth semiconductor chip 400 such that heat dissipating characteristics of the semiconductor package…may be improved” (Lee ¶ 0055), “thermal interface material layer 510 may help heat generated in the first to fourth semiconductor chips 100 to 400 be smoothly discharged” (Lee ¶ 0061), and “trench portions 450 in upper portions of the fourth semiconductor chip 400 may increase an area of a region where the fourth semiconductor chip 400 contacts the thermal interface material layer 510. Thus, the heat generated in the first to fourth semiconductor chips 100 to 400 may be effectively transmitted” (Lee ¶ 0063).
Regarding Claim 11, Lee discloses wherein the filling layer is surrounded by the mold layer (Fig. 7 in this instance the filling layer 510 that is located within trenches 450 is surrounded by the mold layer 190).
Regarding Claim 12, Lee discloses wherein the upper semiconductor chip (400) comprises a lower portion (Fig. 7 in this instance the lower portion of substrate 410 that does not have trenches 450), which is in contact with a bottom surface of the filling layer (Fig. 7 the lower portion is in contact with a bottom surface of the filling layer 510), and upper portions (Fig. 7 in this instance the upper portions of substrate 410 that have trenches 450), which are on the lower portion of the upper semiconductor chip (Fig. 7 the upper portions of 410 are on the lower portion of 410),
wherein the upper portions of the upper semiconductor chip are spaced apart from each other by the filling layer (Fig. 7 the upper portions of substrate 410 are spaced apart from each other by the filling layer 510).
Regarding Claim 13, Lee discloses wherein the upper portions of the upper semiconductor chip (upper portions of 410) comprises an outermost portion (Fig. 7 the leftmost and rightmost portions), which is in contact with the mold layer (Fig. 7 the left side and right side contact mold layer 190), and inner portions (Fig. 7 the leftmost side surface of left trench 450, and the rightmost side surface of right trench 450), which are surrounded by the outermost portion (Fig. 7),
wherein an outer side surface of the outermost portion is flat (¶ 0056 “trench portions 450 may have substantially the same structure as the first trench portions 150 and 150a to 150c of the first semiconductor chip 100, which are described in connection with FIGS. 1 to 5”, ¶ 0047 “FIGS. 3 to 5 are schematic, plan views of the upper surface of the first semiconductor chip 100 illustrate structures of first trench portions 150a to 150c”, in this instance the plan view of Fig. 3 discloses the outer side surface of the outermost portion is flat), and
wherein an inner side surface of the outermost portion is curved (¶ 0056 “trench portions 450 may have substantially the same structure as the first trench portions 150 and 150a to 150c of the first semiconductor chip 100, which are described in connection with FIGS. 1 to 5”, ¶ 0047 “FIGS. 3 to 5 are schematic, plan views of the upper surface of the first semiconductor chip 100 illustrate structures of first trench portions 150a to 150c”, ¶ 0048 “FIG. 3 illustrates that the first trench portion 150a has a rectangular shape, but the first trench portion 150a may have various shapes such as a circle, an oval, a rectangle having rounded corners, or the like.”, in this instance the trenches 450 are ”a circle” in a plan view therefore an inner side surface of the outermost portion is curved).
Regarding Claim 14, Lee discloses wherein the filling layer comprises a plurality of first straight portions (¶ 0056 “trench portions 450 may have substantially the same structure as the first trench portions 150 and 150a to 150c of the first semiconductor chip 100, which are described in connection with FIGS. 1 to 5”, ¶ 0047 “FIGS. 3 to 5 are schematic, plan views of the upper surface of the first semiconductor chip 100 illustrate structures of first trench portions 150a to 150c”, ¶ 0048 “FIG. 3 illustrates that the first trench portion 150a has a rectangular shape”, in this instance the trenches 450 are ”a rectangular shape” in a plan view and the first straight portions are the horizontal portions), which extend in a first direction (in this instance the two straight portions that extend horizontally in Fig. 3 plan view), and a plurality of second straight portions (¶ 0056 “trench portions 450 may have substantially the same structure as the first trench portions 150 and 150a to 150c of the first semiconductor chip 100, which are described in connection with FIGS. 1 to 5”, ¶ 0047 “FIGS. 3 to 5 are schematic, plan views of the upper surface of the first semiconductor chip 100 illustrate structures of first trench portions 150a to 150c”, ¶ 0048 “FIG. 3 illustrates that the first trench portion 150a has a rectangular shape”, in this instance the trenches 450 are ”a rectangular shape” in a plan view and the second straight portions are the vertical portions), which extend in a second direction transverse to the first direction (in this instance the two straight portions that extend vertically in Fig. 3 plan view).
Regarding Claim 15, Lee discloses wherein the inner side surface of the upper semiconductor chip is curved (¶ 0056 “trench portions 450 may have substantially the same structure as the first trench portions 150 and 150a to 150c of the first semiconductor chip 100, which are described in connection with FIGS. 1 to 5”, ¶ 0047 “FIGS. 3 to 5 are schematic, plan views of the upper surface of the first semiconductor chip 100 illustrate structures of first trench portions 150a to 150c”, ¶ 0048 “FIG. 3 illustrates that the first trench portion 150a has a rectangular shape, but the first trench portion 150a may have various shapes such as a circle, an oval, a rectangle having rounded corners, or the like.”, in this instance the trenches 450 are ”a circle” in a plan view therefore the inner side surface is curved), and
wherein the outer side surface of the upper semiconductor chip is flat ((¶ 0056 “trench portions 450 may have substantially the same structure as the first trench portions 150 and 150a to 150c of the first semiconductor chip 100, which are described in connection with FIGS. 1 to 5”, ¶ 0047 “FIGS. 3 to 5 are schematic, plan views of the upper surface of the first semiconductor chip 100 illustrate structures of first trench portions 150a to 150c”, in this instance the plan view of Fig. 3 discloses the outer side surface of the upper semiconductor chip is flat).
Regarding Claim 16, Lee discloses wherein the mold layer and the filling layer comprise the same material (¶ 0041 “molding layer 190 may include…epoxy”, ¶ 0061 “layer 510 may include…epoxy”, therefore the mold layer and the filling layer comprise the same material).
Regarding Claim 17, Lee discloses wherein the mold layer and the filling layer comprise respective different materials ((¶ 0041 “molding layer 190 may include…epoxy”, ¶ 0061 “layer 510 may include…particle filled epoxy”, therefore the mold layer comprises particle-free epoxy and the filling layer comprises particle filled epoxy and those are different materials).
Regarding Claim 19, Lee discloses a semiconductor package (1b; Fig. 7; ¶ 0058 “semiconductor package 1b”), comprising:
a base semiconductor chip (100; Fig. 7; ¶ 0026 “semiconductor chip 100”);
terminals (170; Fig. 7; ¶ 0034 “bumps 170”) connected to the base semiconductor chip (Fig. 7; ¶ 0034);
a connection semiconductor chip (200; Fig. 7; ¶ 0036 “semiconductor chip 200”) on the base semiconductor chip (Fig. 7; ¶ 0036 “mounted above the upper surface of the first semiconductor chip 100”);
an upper semiconductor chip (400; Fig. 7; ¶ 0038 “semiconductor chip 400”) on the connection semiconductor chip (Fig. 7; ¶ 0038 “mounted above”);
a filling layer (510; Fig. 7; ¶ 0061 “layer 510”) in the upper semiconductor chip (Fig. 7; ¶ 0061 “fill the fourth trench portions 450”); and
a mold layer (190; Fig. 7; ¶ 0041 “molding layer 190”) extending around the connection semiconductor chip and the upper semiconductor chip (Fig. 7; ¶ 0041 “molding layer 190 may surround the side surfaces of the first to fourth semiconductor chips 100 to 400”),
wherein the upper semiconductor chip (400) comprises:
a lower pad (442; Fig. 7; ¶ 0039 “connection pads 442”) in contact with the connection semiconductor chip (Fig. 7; ¶ 0038);
an interconnection structure (440; Fig. 7; ¶ 0039 “layer 420 having wire structures 440”) electrically connected to the lower pad (Fig. 7); and
an upper substrate (410; Fig. 7; ¶ 0039 “semiconductor substrate 410”) on the interconnection structure (Fig. 7),
wherein the upper substrate (410) comprises a lower portion (Fig. 7 in this instance the lower portion of upper substrate 410 that does not have trenches 450) and a plurality of upper portions (Fig. 7 in this instance the upper portions of upper substrate 410 that have trenches 450), and
wherein the plurality of upper portions of the upper substrate are spaced apart from each other by the filling layer (Fig. 7; ¶ 0061, the upper portions of the upper substrate are spaced apart from each other by the filling layer 510).
Lee does not specifically disclose a height of the plurality of upper portions of the upper substrate being larger than a distance at which the upper portions are spaced apart.
Lee discloses a distance at which the upper portions are spaced apart (Figs. 4-5, 7; ¶ 0049 “a trench portion 150_1 having a linear shape and extending along a portion of the edge of the first semiconductor chip…and a trench portion 150_2 that is bent around the corner of the…semiconductor chip”; ¶ 0050 “trench portions…may be spaced apart from one another”; ¶ 0051 “unit trench portions…are spaced apart from one another”).
In addition, Lee states ¶ 0051 “unit trench portions…may have various shapes” and “unit trench portions…may have different shapes”. Also, ¶ 0048 “the…trench…may have various shapes” and “the width of the…trench…may be variously adjusted”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Lee to have a height of the plurality of upper portions of the upper substrate being larger than a distance at which the upper portions are spaced apart, because “trench portions 450 increase a surface area of the upper surface of the fourth semiconductor chip 400 such that heat dissipating characteristics of the semiconductor package…may be improved” (Lee ¶ 0055), “thermal interface material layer 510 may help heat generated in the first to fourth semiconductor chips 100 to 400 be smoothly discharged” (Lee ¶ 0061), and “trench portions 450 in upper portions of the fourth semiconductor chip 400 may increase an area of a region where the fourth semiconductor chip 400 contacts the thermal interface material layer 510. Thus, the heat generated in the first to fourth semiconductor chips 100 to 400 may be effectively transmitted” (Lee ¶ 0063).
Regarding Claim 20, Lee discloses wherein a top surface of the lower portion of the upper substrate is in contact with a bottom surface of the filling layer (Fig. 7 a top surface of the lower portion is in contact with a bottom surface of the filling layer 510 located within trench 450), and
wherein a side surface of each of the plurality of upper portions of the upper substrate is in contact with a side surface of the filling layer (Fig. 7 a side surface of each of the plurality of upper portions is in contact with a side surface of the filling layer 510 located within trenches 450).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, US 2017/0358558, in view of Kim et al. (“Kim”), US 2016/0155724.
Regarding Claim 18, Lee does not disclose wherein a height of the upper semiconductor chip is larger than a height of the connection semiconductor chip.
Kim discloses wherein a height of the upper semiconductor chip (400; Figs. 4A, 7A; ¶ 0131 memory “semiconductor chip 400”, ¶ 0162 memory “semiconductor chip 400”) is larger than a height of the connection semiconductor chip (Figs. 4A, 7A; ¶ 0031 “semiconductor chip 400 may have a thickness greater than that of at least the first and second semiconductor chips 100a and 200a”, ¶ 0162 “semiconductor chip 400 may have a thickness greater than that of…semiconductor chips 100a and 200a”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Lee to have wherein a height of the upper semiconductor chip is larger than a height of the connection semiconductor chip, as taught by Kim, because it “reliably stores a large amount of data” (Kim ¶ 0183) and “improves yield” (Kim ¶ 0184) thereby improving the performance and reliability of the semiconductor package.
Response to Arguments
In their amendment and response dated 8/11/2026, the applicant states (page 7) that ”Lee fails to describe the limitation of "wherein a height of the trench extending into the upper semiconductor chip is larger than a width of the trench" as recited in independent claim 1.”
As discussed supra, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Lee to have wherein a height of the trench extending into the upper semiconductor chip is larger than a width of the trench.
The applicant states (page 8) that “Lee fails to describe the limitation of "the upper semiconductor chip comprises an inner side surface in contact with a side surface of the filling layer, a top surface in contact with a bottom surface of the filling layer, and an outer side surface in contact with the mold layer, wherein a length of the inner side surface is longer than a length of the top surface" as recited in independent claim 11.”
It is noted that Claim 11 of the pending application is not an independent claim.
Regarding independent Claim 10, Lee discloses the upper semiconductor chip comprises an inner side surface in contact with a side surface (Fig. 7; ¶ 0061 “layer 510…may fill the fourth trench portions 450” therefore filling layer 510 has a side surface) the filling layer (Fig. 7; ¶ 0061 “layer 510…may fill the fourth trench portions 450”, therefore an inner side surface of trench 450 of the upper semiconductor chip 400 is in contact with filling layer 510), a top surface in contact with a bottom surface of the filling layer (Fig. 7; ¶ 0059 “layer 510…stacked on the fourth semiconductor chip 400”; ¶ 0060; therefore the top surface of upper semiconductor chip 400 is in contact with a bottom surface of the filling layer 510), and an outer side surface in contact with the mold layer (Fig. 7; ¶ 0041 “molding layer 190 may surround the side surfaces of…400”, therefore the outer side surface of upper semiconductor chip 400 is in contact with mold layer 190), as discussed supra.
Also, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Lee to have wherein a length of the inner side surface is longer than a length of the top surface, as discussed supra.
The applicant states (page 8) that “Lee fails to describe the limitation of "a height of the plurality of upper portions of the upper substrate being larger than a distance at which the upper portions are spaced apart" as recited in independent claim 19.”
As discussed supra, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Lee to have a height of the plurality of upper portions of the upper substrate being larger than a distance at which the upper portions are spaced apart.
Independent Claims 1, 10, and 19 are rejected for at least the reasons stated supra. Dependent Claims 2-9, 11-18, and 20 are rejected for at least the reasons stated supra.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Rose Keagy whose telephone number is (571) 270-3455. The examiner can normally be reached Mon-Fri. 8am-5pm (CT).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights