Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to the newly amended claims claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-11 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 11195847 B2).
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CLAIM 1. Hung et al. teaches a semiconductor structure, comprising:
a stack structure comprising gate insulation layers 122 and gate layers 123 stacked alternatively in a first direction; and
a memory post 130[132+134+136] penetrating the stack structure in a corresponding channel along the first direction [Z] (Fig. 3B);
the memory post comprising a first channel structure 1301a, a second channel structure 1301b and an isolation section 142+136 (separates and isolates channel structures) that are disposed within the corresponding channel (Fig. 8A);
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the first channel structure 1301a and the second channel structure 1301b being disposed oppositely along a second direction [±Y] that is perpendicular to the first direction [±Z];
the isolation section 142+136 being located between the first channel structure and the second channel structure and isolating the first channel structure and the second channel structure within the corresponding channel (Hung Figs. 3A-3B & 8).
Isolation structures 1442/144 and dielectric pillar 136 are formed of the same dielectric material and perform identical isolation functions. Under MPEP 2144.04, consolidating separate elements into an integral, unitary structure—when each merely continues to perform its known operation in the same way—is a classic routine design expedient. To a PHOSITA, it would be entirely obvious to form these elements as a single unitary dielectric body. This consolidated structure inherently and predictably provides continuous isolation between the first and second channels, including within the arc of the pillar structure. Because forming the components as an integral unit versus a separable assembly yields the exact same expected results, merging isolation structure 142/144 and dielectric pillar 136 into a single unitary structure is merely a matter of obvious design choice.
CLAIM 2. Hung et al. teaches a semiconductor structure of claim 1, wherein each of the first channel structure and the second channel structure 130 comprises a channel layer134; and the isolation section 140/142 comprises two first isolation sections 140/142 and one second isolation section (Fig. 3A -Note: This limitation does not provide clearly defined boundaries. The term “section” is ambiguous and may be selected arbitrarily.);
the two first isolation sections are disposed oppositely in a third direction [±X] that is perpendicular to the first direction [±Z] and intersects the second direction [±Y] (The isolation structure is a 3D object thus extend in the recited directions. Further note, as the isolation structure travels along the XY plane, it extends in the recited directions. Hung Fig. 3A);
the second isolation section is located between (Hung Figs. 3A &3B):
the two first isolation sections, the channel layer of the first channel structure and the channel layer of the second channel structure (Hung Figs. 3A &3B).
CLAIM 3. Hung et al. teaches a semiconductor structure of claim 2, wherein a material for the first isolation section and a material for the second isolation section are same (Hung Figs. 3A &3B – The isolation structure is a integral structure, thus the same material.).
CLAIM 4. Hung et al. teaches a semiconductor structure of claim 2, wherein the channel layer of the first channel structure and the channel layer of the second channel structure comprise first end surfaces opposite to each other in the second direction, and the first isolation section covers the first end surfaces (Hung Figs. 3A &3B).
CLAIM 5. Hung et al. teaches a semiconductor structure of claim 4, wherein each of the first channel structure and the second channel structure further comprises a storage function layer 132 located between the channel layer 134 and the stack structure (Hung Figs. 3A &3B); and
the storage function layer 132 of the first channel structure and the storage function layer of the second channel structure comprise second end surfaces opposite to each other in the second direction, and the first isolation section further covers the second end surfaces (Hung Figs. 3A &3B).
CLAIM 6 Hung et al. teaches a semiconductor structure of claim 5, wherein the storage function layer comprises: a tunneling layer, a storage layer and a blocking layer away from the channel layer (Hung Figs. 3B & Col. 3 lines 30+ - ONO layers); and the first isolation section further covers the tunneling layer and the storage layer (Hung Figs. 3A &3B).
CLAIM 7. Hung et al. teaches a semiconductor structure of claim 2, however may be silent upon wherein a size of the first isolation section in the second direction is greater than or equal to one fourth of a size of the memory post in the second direction and less than or equal to a half of a size of the memory post in the second direction.
Hung discloses the isolation structure 142 as an integral structure that separates and isolates the channel structures. While Hung does not explicitly state the specific numerical ratio of the isolation section to the memory post, the adjustment of relative sizes would be considered routing Design Choice and Optimization to a PHOSITA.
The relative dimensions of the isolation section and the memory post are a mater of design choice. The MPEP (In re Aller) notes that the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.
One of ordinary skill in the art, seeking to optimize the isolation between channel structures while maintaining the structural integrity of the memory post 130, would naturally arrive at the recited relative dimensions. Adjusting the “size of the first isolation section” relative to the “size of the memory post” involves nothing more than the exercise of routine skill to achieve a desired level of electrical isolation and density.
As seen in Hung Fig. 3A, the isolation section 142 is clearly depicted with a width relative to the overall memory post. The claimed range (one-fourth to one-half) encompasses the proportions shown in the drawings of the prior art, where the isolation section must be wide enough to provide separation but narrow enough to allow for the channel layers.
Therefore, it would have been obvious to a PHOSITA at the time of the invention to size the isolation section of Hung within the recited range to ensure proper isolation of the channel structures. The selection of these specific ratios is a routine optimization of the semiconductor structure disclosed by Hung.
CLAIM 8. Hung et al. teaches a semiconductor structure of claim 7, wherein the size of the first isolation section in the second direction is equal to one third of the size of the memory post in the second direction (Hung Figs. 3A-3B – See regarding claim 7. The specifically recited dimension of 1/3 is a routine optimization of a result-effective variable, as it falls within the previously claimed range and represents a common design choice of balancing isolation width against channel volume in the memory post 130. A PHOSITA would have found it obvious to arrive at this specific value through routine experimentation to achieve the structural configuration depicted in Hung..
CLAIM 9. Hung et al. teaches a semiconductor structure of claim 1, wherein a surface perpendicular to the first direction [±Z] is defined as a reference surface [XY]; and
orthogonal projections of the first channel structure and the second channel structure on the reference surface are arcuate projections (The isolation structure divides the structures creating arcuate shapes. Note: Both the hollow square and circular pillars can be considered arcuate because they each define a curvilinear, bowed boundary that provides a continuous active channel for carrier flow around the isolation material within.) and opening directions of the two arcuate projections are opposite to each other in the second direction (Hung Fig. 3A & 8).
CLAIM 10. Hung et al. teaches a semiconductor structure of claim 1, wherein the first channel structure and the second channel structure are disposed symmetrically (Hung Figs. 3A &3B).
CLAIM 11. Hung et al. teaches a semiconductor structure of claim 1, wherein a number of the memory posts is plurality, the plurality of memory posts are successively arranged at intervals in a third direction [X] that is perpendicular to the first direction [±Z] and intersects the second direction; the semiconductor structure further comprises: a separation section comprising a plurality of sub-separation sections successively disposed at intervals in the third direction, the sub-separation sections penetrate the stack structure in the first direction and connect the isolation sections in two of the memory posts adjacent in the third direction (Hung Figs. 3A &3B – Note: The term “section” does not provide any clear boundaries. “Sections” may be arbitrarily selected to fit the description).
CLAIM 12. Hung et al. teaches a semiconductor structure of claim 11, wherein a material for the separation section and a material for the isolation section are same (Hung Figs. 3A &3B – The isolation structure 142 is shown as an integral structure, thus the material throughout is the same.).
CLAIM 20. Hung et al. teaches a memory system, comprising: a semiconductor structure, comprising:
a stack structure comprising gate insulation layers 122 and gate layers 123 stacked alternatively in a first direction [Z]; and
a memory post 130 penetrating the stack structure in a corresponding channel along the first direction [Z];
the memory post 130 comprising a first channel structure 1301a, a second channel structure 1301b and an isolation section 142/144 + 136 (separating the two channel sections) that are disposed within the corresponding channel (Fig. 8);
the first channel structure 134 and the second channel structure 134 being disposed oppositely in a second direction [Y] that is perpendicular to the first direction [Z];
the isolation section 142 being located between the first channel structure 134 and the second channel structure 134 and isolating the first channel structure 134 and the second channel structure within the corresponding channel 134; and
a controller coupled to the semiconductor structure (Col. 7 line 60+ - Hun discloses that the memory structures may be “independently controlled.” Because independent control of semiconductor memory structures necessitates a controller coupled thereto for the device to be operable, the controller is inherently disclosed by Hung’s description of controlled memory operations.).
Isolation structures 1442/144 and dielectric pillar 136 are formed of the same dielectric material and perform identical isolation functions. Under MPEP 2144.04, consolidating separate elements into an integral, unitary structure—when each merely continues to perform its known operation in the same way—is a classic routine design expedient. To a PHOSITA, it would be entirely obvious to form these elements as a single unitary dielectric body. This consolidated structure inherently and predictably provides continuous isolation between the first and second channels, including within the arc of the pillar structure. Because forming the components as an integral unit versus a separable assembly yields the exact same expected results, merging isolation structure 142/144 and dielectric pillar 136 into a single unitary structure is merely a matter of obvious design choice.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
2/29/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
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