Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bolotnikov et al. (US20170338314A1, hereinafter Bolotnikov).
Regarding claim 1, Bolotnikov discloses a SiC-based MOSFET device, comprising a semiconductor substrate, which is of a first doping type (Fig. 1A, par. 25 substrate 14 has “a drift region 16 having a first conductivity type”), and a cellular structure on a first surface of the semiconductor substrate, wherein the cellular structure comprises structural cells arranged in a preset array (Fig. 3 see plurality of square device cells 50), wherein the cellular structure comprises:
a drift region, located on the first surface of the semiconductor substrate (Fig. 1A drift region 16 on first surface of substrate 14);
a JFET region and well regions, formed in the drift region (Fig. 1A JFET region 29 and well regions 18 located in drift region 16), wherein the well regions are of a second doping type (Par. 25 teaches that the “well region 18 ha[s] a second conductivity type”), wherein the JFET region and the well regions are laterally adjacent along a top surface of the cellular structure (Fig. 1A JFET region 29 and well 18 are laterally adjacent to one another along a top surface of drift region 16);
source regions, each formed in one of the well regions (Fig. 1A source region 20 formed in well region 20);
a gate structure, wherein the gate structure comprises a gate oxide layer and a gate electrode located over the gate oxide layer (Fig. 1A gate dielectric layer 24 and gate electrode 26 located above gate dielectric layer 24), and the gate oxide layer is formed above the JFET region and partially covers each of the well regions (Fig. 1A gate dielectric layer 24 formed above JFET region 29 and partially covers well regions 18); and
shielding regions (Par. 39 “It may be noted that the presently disclosed body region extensions [94], when implanted during the termination step, may additionally or alternatively be referred to and described as “termination implant shield extensions.””), wherein each of the shielding regions is connected to one of the well regions and extends into the JFET region away from the respective well region along a diagonal direction of the cellular structure (Fig. 9 plurality of body region extensions 94 that extend into JFET region 29 along a diagonal between cells), an end portion of each of the shielding regions away from the respective source region is of a cylindrical shape extending along a depth direction of the cellular structure (Par. 40 states that “the body region extensions of the present approach may have other shapes (e.g., square, rounded, elongated or distorted shapes) without negating the effect of the present approach” and so Bolotnikov teaches a rounded, elongated shaped body region extension 94), and the shielding regions have a depth and a doping distribution substantially the same as those of the well regions (Par. 39 “the disclosed body region extensions may be formed using the same implantation step used to form the body region 39, in which case the body region extensions are substantially the same as the body region 39 in terms of doping concentration and depth”).
Regarding claim 2, Bolotnikov discloses the SiC-based MOSFET device according to claim 1,
wherein the preset array comprises one or more of a square array, a hexagonal array, and an octagonal array (Fig. 3 see plurality of square device cells 50 in a square array).
Regarding claim 3, Bolotnikov discloses the SiC-based MOSFET device according to claim 2,
wherein the structural cells are arranged in the square array (Fig. 3 see plurality of square device cells 50 in a square array), each of the shielding regions themselves is of the cylindrical shape extending along the depth direction of the cellular structure (Par. 40 states that “the body region extensions of the present approach may have other shapes (e.g., square, rounded, elongated or distorted shapes) without negating the effect of the present approach” and so Bolotnikov teaches a rounded, elongated shaped body region extension 94), and a cylindrical diameter of each of the shielding region does not exceed 1/3 of a maximum width of the JFET region (While Bolotnikov does not explicitly disclose the diameter of the body extension regions 94 as not having a width that exceeds 1/3 a maximum width of the JFET region 29, fig. 9 would reasonably disclose and suggest to a person of ordinary skill in the art a diameter of each of the body extension regions 94 does not exceed 1/3 of a maximum width of the JFET region 29, see MPEP 2125.I).
Regarding claim 4, Bolotnikov discloses the SiC-based MOSFET device according to claim 2,
wherein the structural cells are arranged in the square array (Fig. 3 see plurality of square device cells 50 in a square array), each of the shielding regions further comprises an elongated column section extending along the diagonal direction of the cellular structure, wherein the end portion of each of the shielding regions covers an end surface of the elongated column section (Par. 40 states that “the body region extensions of the present approach may have other shapes (e.g., square, rounded, elongated or distorted shapes) without negating the effect of the present approach” and so Bolotnikov teaches a rounded, elongated shaped body region extension 94), and a total lateral length of each of the shielding regions along the top surface of the cellular structure does not exceed 1/3 of the maximum width of the JFET region (While Bolotnikov does not explicitly disclose the diameter of the body extension regions 94 as not having a width that exceeds 1/3 a maximum width of the JFET region 29, fig. 9 would reasonably disclose and suggest to a person of ordinary skill in the art a diameter of each of the body extension regions 94 does not exceed 1/3 of a maximum width of the JFET region 29, see MPEP 2125.I).
Regarding claim 7, Bolotnikov discloses a method for manufacturing a SiC-based MOSFET device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface that are opposite to each other (Fig. 1A substrate 14 has top and bottom surface opposite each other);
forming a drift region (Fig. 1A drift region 16 on first surface of substrate 14) and a JFET region defined in the drift region over the semiconductor substrate (Fig. 1A JFET region 29 and well regions 18 located in drift region 16 and over substrate 14);
performing ion implantation of a second doping type in the drift region to simultaneously form well regions and shielding regions (Par. 39 “the disclosed body region extensions may be formed using the same implantation step used to form the body region 39, in which case the body region extensions are substantially the same as the body region 39 in terms of doping concentration and depth.” Par. 39 “It may be noted that the presently disclosed body region extensions [94], when implanted during the termination step, may additionally or alternatively be referred to and described as “termination implant shield extensions”), wherein the well regions are laterally adjacent to the JFET region (Fig. 1A JFET region 29 and well 18 are laterally adjacent to one another along a top surface of drift region 16), each of the shielding regions extends into the JFET region away from the respective well region along a diagonal direction of a cellular structure of the SiC-based MOSFET device (Fig. 9 plurality of body region extensions 94 that extend into JFET region 29 along a diagonal between cells);
performing ion implantation of a first doping type in the well regions to form source regions (Par. 7 “the method includes implanting a source region of the device cell into the semiconductor layer adjacent to the well region of the device cell”), wherein an end portion of each of the shielding regions away from a corresponding one of the source regions comprises an arc-shaped surface (Par. 40 states that “the body region extensions of the present approach may have other shapes (e.g., square, rounded, elongated or distorted shapes) without negating the effect of the present approach” which includes an arc-shaped surface); and
sequentially forming a gate oxide layer and a gate electrode over the semiconductor substrate (Fig. 1A gate dielectric layer 24 and gate electrode 26 located above gate dielectric layer 24).
Regarding claim 9, Bolotnikov discloses the method according to claim 7, further comprising:
forming source metals over the source regions (Fig. 1A, par. 27 “[t]he source contact 22 is generally a metallic interface comprising one or more metal layers”), and forming a drain metal on the second surface of the semiconductor substrate (Fig. 1A drain electrode 12), wherein the semiconductor substrate comprises a heavily doped substrate of the first doping type and a lightly doped epitaxial layer of the first doping type (Fig. 1A the substrate comprises lightly doped substrate 14 and heavily doped drift region 16).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Bolotnikov (US20170338314A1) in view of Banerjee et al. (US20180047844A1, hereinafter Banerjee).
Regarding claim 5, Bolotnikov teaches the SiC-based MOSFET device according to claim 1,
wherein the cellular structure further comprises contact regions (Fig. 1B source contact region 42 and contact 22 comprise a contact region), which are of the second doping type (Par. 32 “the doping of the source contact region 42 may be the same as the remainder of the source region 20”), wherein each of the contact regions is laterally adjacent to one of the source regions along the top surface of the cellular structure (Fig. 1B source contact region 42 and contact 22 are laterally adjacent to source region 20 along top surface of device layer 2), wherein the contact regions are further away from the JFET region than the source regions are from the JFET region (Fig. 1 B source contact region 42 and contact 22 are further away from JFET region 29 than source region 20).
Bolotnikov does not appear to teach
a depth of the contact regions is greater than a depth of the well regions.
Banerjee teaches
a depth of the contact regions is greater than a depth of the well regions (Fig. 10B contact region P+ disposed beneath ohmic contacts deeper than P-well and reaches N-drift region).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bolotnikov with the teachings of Banerjee because as both Bolotnikov and Banerjee teach a suitable contact region depths, it would have been obvious to substitute Bolotnikov’s shallow contact region with Banerjee’s deeper contact region to achieve the predictable result of forming a deeper contact region that reaches a drift region below.
Regarding claim 6, the combination of Bolotnikov and Banerjee teaches the SiC-based MOSFET device according to claim 5,
wherein the semiconductor substrate comprises a heavily doped substrate of the first doping type and a lightly doped epitaxial layer of the first doping type (Fig. 1A the substrate comprises lightly doped substrate 14 and heavily doped drift region 16), and the SiC-based MOSFET device further comprises: source metals and a drain metal (Fig. 1A, par. 27 “[t]he source contact 22 is generally a metallic interface comprising one or more metal layers” and drain electrode 12), wherein each of the source metals is in contact with one of the contact regions and the corresponding source region (Fig. 1A source contacts 22 are in contact with source contact regions 42 and source regions 20), and the drain metal is in contact with a second surface of the semiconductor substrate away from the lightly doped epitaxial layer (Fig. 1A drain electrode 12 is in contact with a bottom surface of substrate 14).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Bolotnikov (US20170338314A1) in view of Utsumi et al. (US20180301536A1, hereinafter Utsumi).
Regarding claim 8, Bolotnikov teaches the method according to claim 7, further comprising:
performing ion implantation of a second doping type in the well regions to form contact regions (Par. 27, fig. 1B “the portion of the source region 20 (e.g., n+ source region 20) of the MOSFET device 10 disposed below the contact 22 may be more specifically referred to herein as a source contact region 42”), wherein each of the contact regions is laterally adjacent to one of the source regions along a top surface of the cellular structure (Fig. 1B source contact region is laterally adjacent to source 20 along a top surface), wherein the contact regions are further away from the JFET region than the source regions are from the JFET region (Fig. 1B source contact region 42 is part of contact 22 and so it is further away from JFET region 29 than source region).
Bolotnikov does not appear to teach
performing pre-cleaning on the first surface of the semiconductor substrate; and
forming a protective film on the first surface of the semiconductor substrate, and
performing ion activation annealing in an argon atmosphere at a temperature of 1700°C to 1750°C.
Utsumi teaches
performing pre-cleaning on the first surface of the semiconductor substrate (Par. 37 “the base body is cleaned (RCA cleaning)”); and
forming a protective film on the first surface of the semiconductor substrate (Par. 56 “a sacrificial oxide film (not depicted) is formed and the sacrificial oxide film is removed by hydrofluoric acid, whereby a damage layer and impurities such as metal on the surface of the n-type silicon carbide layer 1 are removed”), and
performing ion activation annealing in an argon atmosphere at a temperature of 1700°C to 1750°C (Par. 36 “activation annealing is performed at a temperature of about 1700 degrees C. in an inert atmosphere containing, for example, argon”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention because the sacrificial oxide film helps protect the underlying layer to any damage that occurs during the annealing process (Utsumi par. 56). Additionally, as Bolotnikov is silent as to the specifics of ion implantation and activation, this would motivation a person of ordinary skill in the art to seek out references such as Utsumi who do explicitly teach details such as temperature and atmosphere.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Bolotnikov (US20170338314A1) in view of Ohoka et al. (US20170125575A1, hereinafter Ohoka).
Regarding claim 10, Bolotnikov teaches the method according to claim 7.
Bolotnikov does not appear to teach wherein forming the gate oxide layer comprises:
performing thermal oxidation on a surface of the epitaxial layer,
wherein the heavily doped substrate and the lightly doped epitaxial layer are made of 4H-SiC.
Ohoka teaches
performing thermal oxidation on a surface of the epitaxial layer (Par. 104 “gate insulating film 107a is formed by thermal oxidation”),
wherein the heavily doped substrate and the lightly doped epitaxial layer are made of 4H-SiC (Par. 92 “semiconductor substrate 101 is an n type 4H-SiC off-cut substrate”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bolotnikov with the teachings of Ohoka because as Bolotnikov is silent as to the specifics of their SiC substrate’s properties or details of forming the gate insulating layer, this would motivate a person of ordinary skill in the art to seek out references such as Ohoka who explicitly teaches both.
Conclusion
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/COLE LEON LINDSEY/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812