DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 recites (last limitation) recites “the magnetic tunnel junction” which lacks further antecedent basis. Further this creates duplication with dependent claim 3.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-8 and 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Robustelli (US 9,627,055).
Regarding claim 1, Robustelli discloses an apparatus comprising: a memory cell comprising a reversible resistance-switching memory element (see Figure 2B, 210) coupled in series with an ovonic threshold selector element (212) that comprises a threshold voltage; and a control circuit (214 for example) coupled to the memory cell, the control circuit configured to: use a first pulse (see Figure 6c, 602) comprising a first polarity to first access the memory cell; and use a second pulse (604) comprising the first polarity to second access the memory cell and read the memory cell, wherein the first pulse is configured to reduce a rate of threshold voltage drift of the ovonic threshold selector element, over repeated read operations, thereby reducing read variability without altering a stored data state (this limitation is drawn to the intended outcome of the application of an electric pulse and is not thought to impart any particular structure to the claimed apparatus—nevertheless, Robustelli teaches this in column 4 lines 45+) of the magnetic tunnel junction memory element (see column 8, line 66+).
Regarding claim 2, Robustelli discloses the apparatus of claim 1, wherein the reversible resistance-switching memory element comprises a magnetic memory element (see above).
Regarding claim 3, Robustelli discloses the apparatus of claim 1, wherein the reversible resistance-switching memory element comprises a magnetic tunnel junction (see above).
Regarding claim 4, Robustelli discloses the apparatus of claim 1, wherein the ovonic threshold selector element comprises a threshold selector device (see abstract).
Regarding claim 6, Robustelli discloses the apparatus of claim 1, wherein the ovonic threshold selector element comprises a threshold voltage that drifts at an increasing rate with time (see column 4, line 43).
Regarding claim 7, Robustelli discloses the apparatus of claim 1, wherein the ovonic threshold selector element may be selectively turned ON (e.g. for reading).
Regarding claim 8, Robustelli discloses the apparatus of claim 1, wherein the first pulse and the second pulse each turn ON the ovonic threshold selector element (see column 5, lines 46+).
Regarding claim 11, Robustelli discloses the apparatus of claim 1, wherein the second pulse comprises a RESET pulse (the terms set and reset are arbitrarily defined and impart no particular definition to characterize the apparatus).
Regarding claim 12, Robustelli discloses the apparatus of claim 1, wherein the first pulse is configured to turn ON the ovonic threshold selector element without disturbing a data state of the reversible resistance-switching memory element (see column 5, lines 31+).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Robustelli.
Regarding claim 13, Robustelli discloses the apparatus of claim 1, wherein the control circuit is further configured to use the first pulse to first access the memory cell but fails to teach that the access is less than about 100 nsec before using the second pulse to second access the memory cell.
However, absent a showing of criticality, one of ordinary skill is generally motivated to speed a read process in order to conserve time and therefore would have found it obvious to apply the read pulse as quickly as possible after the pre read pulse. Finding the optimal value of the time between pulses requires only routine skill in the art since it results directly in its effect on the read operation.
Claim(s) 9, 10, 14, and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Robustelli in view of Tran (US 11,398,262).
Regarding claim 14, Robustelli discloses an apparatus comprising: a cross-point memory array (see column 8, lines 62+) comprising a plurality of memory cells, each memory cell comprising a magnetic tunnel junction memory element coupled in series with an ovonic threshold selector element (see column 8, line 66+ the the alternative embodiment comprising STTMRAM for example); a control circuit coupled to cross-point memory array (see rejection of claim 1 above), the control circuit configured to prior to a read operation apply a pre-read pulse to reset a threshold voltage of the corresponding selector element, wherein the pre-read pulse is configured to reduce a rate of threshold voltage drift of the ovonic threshold selector element across the array (see rejection of claim 1 above), thereby reducing bit error rate during the sequence of self-referenced read operations (this is drawn to the intended result of the pulse application and does not impart any particular structure to the claimed apparatus, however Robustelli teaches the pulse reduces drift and therefore error rate).
Robustelli fails to teach details regarding the MRAM specific read operation and therefore fails to teach a self-referenced read operation of each of the plurality of memory cells. However, this is a known technique of reading MRAM cells at the time of filing (see for example, Tran column 16 lines 39+). Therefore, it would have been obvious to one having ordinary skill at the time of filing to include the known self reference read since this was a known technique and yields a predictable result of a data read in MRAM.
Regarding claim 17, Robustelli discloses the apparatus of claim 14, wherein each ovonic threshold selector element comprises a threshold voltage that drifts at an increasing rate with time (see rejection above).
Regarding claim 18, Robustelli discloses the apparatus of claim 14, wherein the pre-read pulse is configured to reduce a bit error rate of the plurality of memory cells (drawn to intended result, but reduces drift and therefore BER).
Regarding claim 19, Robustelli as modified above teaches the reading steps of the claim (see rejections of claims 1 and 14). Robustelli fails to teach that a bit error rate is actively determined (although Tran mentions error rate, reading and checking for errors). However, one of ordinary skill would have been motivated at the time of filing to evaluate the performance of a memory device by testing for error rate in order to increase data integrity by reading and checking for errors and noting the rate of error occurrence.
Regarding claim 20, Robustelli discloses wherein the magnetic memory elements each comprise a magnetic tunnel junction (see rejection above).
Regarding claim 9, Robustelli discloses the apparatus of claim 1, wherein the control circuit is further configured to perform a first read and a second read of the reversible resistance-switching memory element after the second pulse (in view of the teachings of Tran see above—the self referenced read is a two read process).
Regarding claim 10, Robustelli discloses the apparatus of claim 1, wherein the control circuit is further configured to perform a destructive read of the reversible resistance-switching memory element after the second pulse (in view of the teachings of Tran see above—the self referenced read is a destructive read process).
Response to Arguments
Applicant’s remarks have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Due to the art now of record, the Examiner has vacated any previous indications of allowable features of the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS KING whose telephone number is (571)272-2311. The examiner can normally be reached M-F: 9:00AM-5:30PM.
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/DOUGLAS KING/Primary Examiner, Art Unit 2824