Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
To facilitate consideration of any amendment that may be presented in response to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application that clearly support the amendment.
DETAIL ACTION
Claims 1--20 are pending in this application. Claims 1 , 14 and 19 are independent.
Information Disclosure Statement
The Information Disclosure Statements (IDS) submitted on 108/24, 5/12/25 and 7/08/25 by the applicant have been received and fully considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1–20 are rejected under 35 U.S.C. § 103 as being obvious over Scheuerlein (US 2013/0135925 A1) in view of Gupta (US 10,079,056 B2).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claims 1, 14 and method claim 19-20:
An apparatus comprising: a memory cell comprising a reversible resistance-switching memory element coupled in series with a selector element that comprises a threshold voltage; and a control circuit coupled to the memory cell, the control circuit configured to: use a first pulse comprising a first polarity to first access the memory cell; and use a second pulse comprising the first polarity to second access the memory cell and read the memory cell, wherein the first pulse is configured to reduce a rate of threshold voltage drift of the selector element.
Scheuerlein (¶ [32]–[41], Figs. 2–4) shows a memory cell comprising a resistance-switching element (memristor 110) in series with a threshold selector 120. The selector has a characteristic threshold voltage Vth (¶ [43]). Control circuitry (¶ [50]–[56]) applies read and write pulses of selectable polarity across the cell.
Gupta (Col. 5 l. 24 – Col. 6 l. 10; Figs. 4–6) teaches that a first pre-read or “refresh” pulse can be applied prior to the main read pulse to restore the selector’s threshold and reduce drift rate, without altering the data state. The first and second pulses are of the same polarity (see waveform 60, Fig. 5).
It would have been obvious to a skilled artisan to incorporate Gupta’s pre-read pulse technique into Scheuerlein’s array to mitigate the known problem of selector-threshold drift and thereby improve read accuracy (KSR rationale: predictable use of known method to improve similar device performance).
As for claims 2-3, The apparatus of claim 1, wherein the reversible resistance-switching memory element comprises a magnetic memory element and wherein the reversible resistance-switching memory element comprises a magnetic tunnel junction.
Gupta (Col. 8 l. 15 – 25) discloses that the resistive element may be a magnetic tunnel junction (MTJ) or other spin-based variable resistor.
Scheuerlein already provides generic resistive elements;
Therefore, substituting MTJ variants is an obvious material choice within the same art of semiconductor.
As for claims 4-6. The apparatus of claim 1,
wherein the selector element comprises a threshold selector device.
wherein the selector element comprises an ovonic threshold switch.
wherein the selector element comprises a threshold voltage that drifts at an increasing rate with time.
Scheuerlein ¶ [40]–[44] explicitly discusses threshold drift in the OTS selector and its increase with time/temperature.
Gupta’s pre-pulse method addresses that exact phenomenon (Col. 5 l. 25 – 45).
Hence, the combination disclosed all limitations suggested.
As for claims 7-8. The apparatus of claim 1,
wherein the selector element may be selectively turned ON.
wherein the first pulse and the second pulse each turn ON the selector element.
Scheuerlein Fig. 3 shows the selector switching “ON” when voltage exceeds Vth;
Gupta’s first and second pulses both exceed Vth momentarily (Fig. 5), thereby turning the selector ON twice.
As for claims 9-10. The apparatus of claim 1,
wherein the control circuit is further configured to perform a first read and a second read of the reversible resistance-switching memory element after the second pulse.
wherein the control circuit is further configured to perform a destructive read of the reversible resistance-switching memory element after the second pulse.
Gupta Col. 6 l. 20 – 40 teaches successive reads—normal and verify (or destructive)—after the main pulse.
If combined with Scheuerlein’s control circuit (¶ [50]), the limitations of claims 9-10 are met.
As for claim 11-13. The apparatus of claim 1,
wherein the second pulse comprises a RESET pulse.
wherein the first pulse is configured to turn ON the selector element without disturbing a data state of the reversible resistance-switching memory element.
wherein the control circuit is further configured to use the first pulse to first access the memory cell less than about 100 nsec before using the second pulse to second access the memory cell.
All the above limitations are described in Gupta references:
Gupta Fig. 6, waveform 70, shows the RESET pulse of same polarity applied within tens of nanoseconds;
Gupta (Col. 6 l. 35 – 45) specifies sub-100 ns intervals for selector stabilization.
As for independent claim 14,
An apparatus comprising: a cross-point memory array comprising a plurality of memory cells, each memory cell comprising a magnetic tunnel junction memory element coupled in series with a selector element; a control circuit coupled to cross-point memory array, the control circuit configured to: perform a self-referenced read operation of each of the plurality of memory cells; and prior to each self-referenced read operation, apply a pre-read pulse to reset a threshold voltage of the corresponding selector element.
(See the rejection of claim 1 above).
Also, Scheuerlein Figs. 2–3 disclose the cross-point array;
Gupta Col. 7 l. 15–35 describes a self-referenced read using internal reference current and pre-read conditioning. The combination therefore disclose all limitations.
As for claims 15-17. The apparatus of claim 14,
wherein each selector element comprises a threshold selector device.
wherein each selector element comprises an ovonic threshold switch.
wherein each selector element comprises a threshold voltage that drifts at an increasing rate with time.
As for claim 18. The apparatus of claim 14, wherein the pre-read pulse is configured to reduce a bit error rate of the plurality of memory cells.
Gupta Abstract; (Col. 8 l. 30 – 45): applying pre-read pulses lowers BER in array tests—exactly as recited.
As for claims 19-20,
A method comprising: determining a bit error rate of a plurality of memory cells, each comprising an ovonic threshold switch coupled in series with a magnetic memory element, by: performing a sequence of self-referenced read operations of each of the memory cells, each self-referenced read operation comprising a RESET pulse comprising a first polarity; and prior to each self-referenced read operation, applying to the memory cells a pulse comprising the first polarity to turn ON the ovonic threshold switch without disturbing a data state of the corresponding magnetic memory element, wherein the pre-read pulses are configured to reduce the bit error rate of the plurality of memory cells.
(See the rejection of claim 1 above).
Gupta Figs. 4–6 and accompanying text describe method steps of
(1) determining BER via repeated self-referenced reads,
(2) applying same-polarity pre-read pulses, and
(3) reducing BER.
Scheuerlein provides the hardware platform (as discussed in claim 1).
Thus, the method is fully rendered obvious by the combined teachings
Citation of Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Applicants are directed to consider additional pertinent prior art included on the Notice of References Cited (PTOL 892) attached herewith.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEN N NGUYEN whose telephone number is (571)272-1879. The examiner can normally be reached Monday- Friday 9am-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
HIEN N. NGUYEN
Primary Examiner
Art Unit 2824
/HN/
September 29, 2025
/HIEN N NGUYEN/Primary Examiner, Art Unit 2824
Prosecution Insights