DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-10 (invention group II) in the reply filed on 04/22/2026 is acknowledged.
Claims 11-14 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/22/2026.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d).
Information Disclosure Statement
The information disclosure statement filed on 12/20/2023 has been acknowledged and a signed copy of the PTO-1449 is attached herein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Levy et al. (US 2015/0279969 A1, hereinafter “Levy”) in view of Lin et al. (US 2018/0130903 A1, hereinafter “Lin”).
In regards to claim 1, Levy discloses (See, for example, Fig. 1) a semiconductor device comprising:
a first conductivity type substrate (201);
a second conductivity type semiconductor layer (220) formed over the substrate (201);
a second conductivity type drift region (215) formed at a surface portion of the semiconductor layer (220);
a second conductivity type drain region (242) formed at the drift region (215);
a first conductivity type body region (204) formed adjacent to the drift region (215) at the surface portion of the semiconductor layer (220);
a second conductivity type source region (241) formed at the body region (204); and
a first conductivity type resurf layer (254).
However, Levy fails to explicitly teach that a first conductivity type resurf layer that expands from a center of the drain region to both sides in a lateral direction along a main surface of the semiconductor device to entirely cover the drift region (drain centric LDMOS 220 (see in Fig. 6); symmetry drain-centric extended-drain device 450 in which the drain is surrounded on both sides. See Figs. 12 and 13).
Lin while disclosing a semiconductor device teaches (See, for example, Fig. 1) a first conductivity type resurf layer (66) that expands from a center of the drain region (38) to both sides in a lateral direction along a main surface of the semiconductor device to entirely cover the drift region (42).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to provide the first conductivity type resurf layer covering the drift region as taught by Lin because this would help deplete the drift region in both vertical and lateral directions to reduce the electric field near the of-state breakdown voltage of the device.
In regards to claim 2, Levy as modified above discloses (See, for example, Fig. 1, Lin) that wherein a side portion of the resurf layer (66) and a side portion of the drift region (42) are continuous in a thickness direction of the substrate (26).
In regards to claim 3, Levy as modified above discloses (See, for example, fig. 1, Lin) that wherein the side portion of the resurf layer (66) and the side portion of the drift region (42) are flush with each other.
In regards to claim 4, Levy as modified above discloses (See, for example, Fig. 1) wherein the resurf layer (254) is in contact with the drift region (215/252).
In regards to claim 5, Levy as modified above discloses (See, for example, Fig. 3) that wherein the resurf layer (254) is separated (See, for example, Fig. 3(J)/3(S)) from the drift region (252).
In regards to claim 6, Levy as modified above discloses (See, for example, Fig. 1) that further comprising: a second conductivity type buried layer (250) formed below the resurf layer (254).
In regards to claim 8, Levy as modified above discloses (See, for example, Fig. 1) that further comprising: a stacked structure of the buried layer (250), the resurf layer (254), and the drift region (254), in a thickness direction of the substrate (201).
In regards to claim 9, Levy as modified above discloses (See, for example, Fig. 1) that wherein the drift region (215/252) and the body region (204) are in contact with each other.
In regards to claim 10, Levy as modified above loses (See, for example, Fig. 1, Lin) that wherein the drift region (42) and the body region (40) are separated from each other.
Claims 1-6 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Levy in view of Lin as applied to claim 6 above, and further in view of Shirai (US 2013/0313639 A1, hereinafter “Shirai”).
In regards to claim 7, Levy as modified above discloses all limitations of claim 6 except that wherein a side portion of the buried layer and a side portion of the resurf layer are flush with each other.
Shirai while disclosing a semiconductor device teaches (See, for example, Fig. 1) a side portion of the buried layer (11) and a side portion of the resurf layer (12) are flush with each other.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to provide the second conductivity type buried layer with a side portion flush with the side portion of the resurf layer in the vertically stacked buried layer/resurf arrangement as taught by Shirai because this would help relax the source-drain electric field and thereby increase the breakdown voltage of the lateral DMOS.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893
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