DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 contains the language “invoke performance a first emulation… ”. It is unknown to the examiner what is meant when using the disclosed terms as this is not standard language. Because it is unknown to examiner what is meant by the disclosed language, it is determined as indefinite. To overcome 112b rejection, examiner suggest clearly defining the above.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Specifically, representative Claim 1 recites:
A method of determining power consumption of a circuit design, the method comprising: determining toggle data associated with each of a first plurality of flip-flops disposed in the circuit design by applying a stimulus to the circuit design during one or more time intervals; selecting a subset of the first plurality of flip-flops based on their toggle data; performing a first hardware emulation of the circuit design after instrumenting each of the subset of the first plurality of flip-flops; identifying a plurality of time periods during which a sum of toggle data associated with the instrumented flip-flops exceeds a threshold count; performing a second hardware emulation of the circuit for each of the plurality of time periods after instrumenting a second plurality of flip-flops disposed in the circuit design; storing waveform data associated with each of the second plurality of flip-flops in a first memory; and determining the power consumption of the circuit design from the stored waveform data.
The claim limitations in the abstract idea have been highlighted in bold above; the remaining limitations are “additional elements”.
Under Step 1 of the eligibility analysis, we determine whether the claims are to a statutory category by considering whether the claimed subject matter falls within the four statutory categories of patentable subject matter identified by 35 U.S.C. 101: Process, machine, manufacture, or composition of matter. The above claim is considered to be in a statutory category (process).
Under Step 2A, Prong One, we consider whether the claim recites a judicial exception (abstract idea). In the above claim, the highlighted portion constitutes an abstract idea because, under a broadest reasonable interpretation, it recites limitations that fall into/recite an abstract idea exception. Specifically, under the 2019 Revised Patent Subject matter Eligibility Guidance, it falls into the grouping of subject matter when recited as such in a claim limitation, that covers mental processes.
For example, steps of “determining the power consumption of the circuit design from the stored waveform data” are treated by the Examiner as belonging to mental process grouping.
Similar limitations comprise the abstract ideas of Claims 13 and 20.
Next, under the Step 2A, Prong Two, we consider whether the claim that recites a judicial exception is integrated into a practical application.
In this step, we evaluate whether the claim recites additional elements that integrate the exception into a practical application of that exception.
The above claims comprise the following additional elements:
In Claim 13: a memory storing instructions, processor.
In Claim 20: a non-transitory computer readable medium; processor.
The additional element of a memory string instructions, non-transitory readable medium and processor (generic processor) are generally recited and are not qualified as particular machines.
With respect to Claim 1, the limitations “performing a first hardware emulation of the circuit design after instrumenting each of the subset of the first plurality of flip-flops;
performing a second hardware emulation of the circuit for each of the plurality of time periods after instrumenting a second plurality of flip-flops disposed in the circuit design; storing waveform data associated with each of the second plurality of flip-flops in a first memory,” are defined by MPEP 2106.05(f) and (g) as mere instructions to apply an exception and insignificant extra solution activity.
In conclusion, the above additional elements, considered individually and in combination with the other claim elements do not reflect an improvement to other technology or technical field, and, therefore, do not integrate the judicial exception into a practical application. Therefore, the claims are directed to a judicial exception and require further analysis under the Step 2B.
However, the above claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception (Step 2B analysis).
The claims, therefore, are not patent eligible.
With regards to the dependent claims, claims 2-12 and 14-19 provide additional features/steps which are part of an expanded algorithm, so these limitations should be considered part of an expanded abstract idea of the independent claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 8-9, 13-16, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu (US20090271167A1, 2009-10-29), in view Tseng et al. (US6009256, 1999-12-28) herein referred to Tseng.
Regarding Claim 1, Zhu teaches a method of determining power consumption of a circuit design [Abstract], the method comprising: determining toggle data associated with each of a first plurality of flip-flops disposed in the circuit design by applying a stimulus to the circuit design during one or more time intervals ([0075]: In the first step 1104, the design runs in the emulation system with an application environment to give instructions on how to operate the design. While the design runs, the DUT activities will be recorded in two files. The first file is a .phy file, which includes DUT's input/output pins values, sequential elements (such as flip flops) output pins, memory output values in each clock cycle, special signals' force/release/set values in asserted clock cycles. The second file is a .tc file, which includes a set of given instances' weighted toggle count, unweighted toggle count, and duty count per clock cycle (Examiner’s Note: the stimulus is considered obvious, due to the outputted toggle count and special signals. A signal/stimulus has to be applied to the flip flop to count a toggle); selecting a subset of the first plurality of flip-flops based on their toggle data [0023; 0097]; performing a first hardware emulation of the circuit design after instrumenting each of the subset of the first plurality of flip-flops [Abstract; Fig. 1; 0077]; identifying a plurality of time periods during which a sum of toggle data associated with the instrumented flip-flops exceeds a threshold count [0048; 0053; 0062; 0075; 0097]; performing a second hardware emulation of the circuit for each of the plurality of time periods after instrumenting a second plurality of flip-flops disposed in the circuit design [Fig. 1]; storing waveform data associated with each of the second plurality of flip-flops in a first memory [0049]; and determining the power consumption of the circuit design from the stored waveform data [Fig. 3 (316)]. Although, the examiner believes Zhu teaches all of the limitations (specifically “by applying a stimulus to the circuit design”) of Claim 1, an additional reference is cited to assist in progression. Tseng teaches the application of a stimulus to circuit for simulation purposes [Step 304: Step 304 generates a software model for all HDL components regardless of component type. With the appropriate user interface, the user is capable of simulating the entire circuit design using the complete software model. Test-bench processes are used to drive the stimulus input, test vector patterns, control the overall simulation, and monitor the simulation process].Therefore, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Zhu to incorporate the teachings of Tseng by including: limitation above in order to verify electronic systems.
Regarding Claim 2, the combination further teaches the method of claim 1 wherein the stimulus is applied by a logic simulation software to simulate the circuit design during the one or more time intervals (Tseng: Step 304, (53), (66), (70): As explained above, user test-bench stimulus and test vector data as well as other test-bench resources 235 are applied to the general purpose processor or workstation 240 for simulation purposes. Furthermore, the user can perform emulation of the circuit design via software control. The reconfigurable hardware boards 250 contain the user's emulated circuit design. This SEmulation system has the ability to let the user selectively switch between software simulation and hardware emulation, as well as stop either the simulation or emulation process at any time, cycle-by-cycle, to inspect values from every component in the model, whether register or combinationa).
Regarding Claim 3, the combination further teaches the method of claim 1 wherein the stimulus is applied by a hardware emulation system to emulate the circuit design during the one or more time intervals Tseng: Step 304, (53), (66), (70): As explained above, user test-bench stimulus and test vector data as well as other test-bench resources 235 are applied to the general purpose processor or workstation 240 for simulation purposes. Furthermore, the user can perform emulation of the circuit design via software control. The reconfigurable hardware boards 250 contain the user's emulated circuit design. This SEmulation system has the ability to let the user selectively switch between software simulation and hardware emulation, as well as stop either the simulation or emulation process at any time, cycle-by-cycle, to inspect values from every component in the model, whether register or combinational ).
Regarding Claim 4, the combination further teaches the method of claim 1 wherein the first plurality of flip-flops comprises an entirety of flip-flops disposed in the circuit design, and wherein the second plurality of flip- flops comprises the entirety of flip-flops disposed in the circuit design (Zhu: [0017]).
Regarding Claim 8, Zhu further teaches the method of claim 1, wherein the toggle data of each of the selected subset of the first plurality of flip-flops is above a threshold toggle data [0053; 0077: In the second step 1106, the time windows of interest are divided into segments based on some criteria such as power modes (for CPF compliant designs only), threshold of transition activity level. Transition activity level is a measurement of the toggle count of all design nodes in the DUT or the selected functional block(s). Those time durations with low transition activity levels can be filtered out by assigning number of segment to zero for the given time window].
Regarding Claim 9, Zhu further teaches the method of claim 1, wherein the selected subset of the first plurality of flip-flops has a highest toggle data of all the first plurality of flip-flops [0023: identifying one or more nodes of the DUT with high power consumption in the one or more peak-power segments. The highest power consumption correlates to the high toggle count].
Regarding Claim 13, Zhu teaches a hardware emulation system [0015] comprising: a memory storing instructions; and a processor, coupled with the memory and to execute the instructions [0024], the instructions when executed cause the processor to: receive toggle data associated with each of a first plurality of flip-flops disposed in the circuit design [0075]; select a subset of the first plurality of flip flops based on their toggle data [0023; 0097]; invoke performance a first emulation run of the circuit design while each of the subset of the first plurality of flip-flops is instrumented [Abstract; Fig. 1; 0077]; identify a plurality of time periods during which a sum of toggle data associated with the instrumented flip-flops exceeds a threshold value [0048; 0053; 0062; 0075; 0097]; invoke performance of a second emulation of the circuit for the plurality of time periods while a second plurality of flip-flops disposed in the circuit design are instrumented [Fig. 1]; and store waveform data associated with each of the second plurality of flip-flops in a first memory [0049].
Regarding Claim 14, Zhu further teaches the hardware emulation system of claim 13 wherein the toggle data is determined by logic simulation software configured to simulate the circuit design during the one or more time intervals [0015].
Regarding Claim 15, Zhu further teaches the hardware emulation system of claim 13, wherein the toggle data is determined by the hardware emulation system during one or more time intervals [Abstract; 0015].
Regarding Claim 16, Zhu further teaches the hardware emulation system of claim 13, wherein the first plurality of flip-flops comprises an entirety of flip-flops disposed in the circuit design, and wherein the second plurality of flip-flops comprises the entirety of flip-flops disposed in the circuit design [0017].
Regarding Claim 19, Zhu further teaches the hardware emulation system of claim 13, wherein the toggle data of each of the selected subset of the first plurality of flip-flops is above a threshold toggle data [0053; 0077: In the second step 1106, the time windows of interest are divided into segments based on some criteria such as power modes (for CPF compliant designs only), threshold of transition activity level. Transition activity level is a measurement of the toggle count of all design nodes in the DUT or the selected functional block(s). Those time durations with low transition activity levels can be filtered out by assigning number of segment to zero for the given time window].
Regarding Claim 20, Zhu teaches a non-transitory computer readable medium comprising stored instructions [0024], which when executed by a processor, cause the processor to: receive toggle data associated with each of a first plurality of flip-flops disposed in the circuit design [0075]; select a subset of the first plurality of flip flops based on their toggle data [0023; 0097]; invoke performance a first emulation run of the circuit design while each of the subset of the first plurality of flip-flops is instrumented [Abstract; Fig. 1; 0077]; identify a plurality of time periods during which a sum of toggle data associated with the instrumented flip-flops exceeds a threshold value [0048; 0053; 0062; 0075; 0097]; invoke performance of a second emulation of the circuit for the plurality of time periods while a second plurality of flip-flops disposed in the circuit design are instrumented [Fig. 1]; and store waveform data associated with each of the second plurality of flip-flops in a first memory [0049].
Claims 5 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu and Tseng in view of Wilson (US20170344682A1, 2017-11-30).
Regarding Claim 5, Zhu teaches the method of Claim 1. Although Zhu teach wherein the toggle data associated with each of the subset of the first plurality of flip-flops comprises a toggle count of the flip-flop [0017-0019], he fails to specifically teach and a fanout of the flip flop.
However, in a related field, Wilson teaches wherein the toggle data associated with each of the subset of the first plurality of flip-flops comprises a toggle count of the flip-flop and a fanout of the flip-flop [0072]. Therefore, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Zhu to incorporate the teachings of Wilson by including: the limitation above in order to increase the accuracy of the power consequences attributed to the clock gate.
Regarding Claim 17, Zhu teaches the hardware emulation system of claim 13. although Zhu teach wherein the toggle data associated with each of the subset of the first plurality of flip-flops comprises a toggle count of the flip-flop [0017-0019], he fails to specifically teach and a fanout of the flip flop.
However, in a related field, Wilson teaches wherein the toggle data associated with each of the subset of the first plurality of flip-flops comprises a toggle count of the flip-flop and a fanout of the flip-flop [0072]. Therefore, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Zhu to incorporate the teachings of Wilson by including: the limitation above in order to increase the accuracy of the power consequences attributed to the clock gate.
Claims 6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu and Tseng in view of Tonks et al. (TW 89107630A, 2000-05-27) herein referred to as Tonks.
Regarding Claim 6, the combination further teaches the method of claim 1 further comprising configuring the hardware emulation system to form and a storage control logic [0046]. The combination teaches a toggle count [0046], but fails to specifically teach a plurality of toggle detectors, a plurality of toggle counters, a toggle accumulator.
However, in a related field, Tonks teaches a plurality of toggle detectors (42) Fig. 3, a plurality of toggle counters (50) (52) (pairs) Fig. 4, a toggle accumulator (57) Fig. 4. Therefore, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Zhu and Tseng to incorporate the teachings of Tonks by including: the limitations above in order to determine operational mode values from the emulation data and a selection of operational modes that characterize circuit behavior in the one or more time windows.
Regarding Claim 18, the combination further teaches the hardware emulation system of claim 13 further comprising configuring the hardware emulation system to form and a storage control logic [0046]. The combination teaches a toggle count [0046], but fails to specifically teach a plurality of toggle detectors, a plurality of toggle counters, a toggle accumulator.
However, in a related field, Tonks teaches a plurality of toggle detectors (42) Fig. 3, a plurality of toggle counters (50) (52) (pairs) Fig. 4, a toggle accumulator (57) Fig. 4. Therefore, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Zhu and Tseng to incorporate the teachings of Tonks by including: the limitations above in order to determine operational mode values from the emulation data and a selection of operational modes that characterize circuit behavior in the one or more time windows.
Allowable Subject Matter
Claims 7, 10-12 would be allowable if written overcome the 101 rejection set forth in this office action.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 7, Zhu, along with all other references fail to teach the method of claim 1 further comprising: stopping the second hardware emulation of the circuit design when the first memory is full; transferring the waveform data stored in the first memory to a second memory after stopping the second hardware emulation; and resuming the second hardware emulation after the waveform data is transferred from the first memory to the second memory. It is for this reason Claim 7 would be allowed.
Regarding Claim 10, Zhu, along with all other references fail to teach the method of claim 1 further comprising: performing the second hardware emulation of the circuit after instrumenting a first plurality of nodes disposed in the circuit design, wherein said first plurality of nodes is distinct from the first plurality of flip-flops; storing waveform data associated with each of the first plurality of nodes in the first memory; and determining the power consumption of the circuit design from the stored waveform data. It is for this reason Claim 10, and all of its dependencies would be allowed.
Conclusion
The prior art made record and not relied upon is considered pertinent to applicant’s disclosure.
Potapov et al. (Dedicated Reconfigurable IP For Emulation-based Power Estimation, 2021-10-05) teaches A power usage estimation system for a design emulated on a field programmable gate array (FPGA) comprising a periodic dump unit implementing statistical data sampling to generate a periodic dump without emulation stops and interactions with a host, and without affecting the emulation performance.
Larzul et al. (Efficient Power Analysis, 2016-04-07) teaches the emulation of circuits and tracking states of signals in an emulated circuit for performing power analysis. A host system incorporates power analysis logic into a design under test (DUT). An emulator emulates the DUT along with the incorporated power analysis logic. Based on the power analysis logic, during a power analysis clock cycle, the emulator selects a signal from a plurality of signals of the DUT. The emulator determines whether a state event is detected for the selected signal. If the state event is detected, a state count is updated for the selected signal that indicates a number of state events detected for the selected signal during emulation of the DUT. If the state count reaches a threshold number based on the update, the emulator transmits a count update signal to the host system indicating that the state count reached the threshold number.
Elmufdi et al. teaches a method and apparatus for modeling a flip-flop of a user's circuit design when that circuit design is mapped in a hardware functional verification system including a plurality of interconnected emulation chips, or in a single emulation chip. The flip flop can be modeled in the emulation chip as two stages using only a single instruction, and may be configured by programming a register set. A data block, enable block, and LUT block are provided to model the flip flop, and may operate in one of several modes, including combined and uncombined modes. The data block includes a data array to store and provide previous data inputs and previous states of the modeled flip flop. The disclosed embodiments allow a more efficient use of LUTs for modeling flip flops, including options for resets and global enables, operating in several modes.
Chou (Power Computation Logic, 2018-05-03) teaches a method includes receiving, by the computer, a first data representative of a first design of an integrated circuit, when the computer is invoked to configure the verification system, and transforming, using the computer, the first data into a second data representative of a second design. The second design includes a functionality of the first design, and a first circuit adapted to compute a third data representative of a power consumption of a first portion of the first design when the hardware verification system is configured with the second data and run. The first circuit is programmable without reconfiguring the second design.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J SINGLETARY whose telephone number is (571)272-4593. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Catherine Rastovski can be reached at 571-270-0349. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL J SINGLETARY/Examiner, Art Unit 2857
/Catherine T. Rastovski/Supervisory Primary Examiner, Art Unit 2857
