Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
1. Claims 1-20 are rejected under 35 U.S.C. 102(a2) as being anticipated by Majhi et al. (US 2023/0197612; hereinafter Majhi).
Regarding claim 1, Majhi, in fig. 3, discloses a semiconductor device, comprising: an electrical pathway connecting a frontside of the semiconductor device to a backside of the semiconductor device; the electrical pathway including: a backside wire 144a disposed within a backside interconnect layer 144a; a first deep via 124a connecting to the backside wire144a, the first deep via 124a extending through a front end of line (FEOL) region (Device Layer 106); and a local interconnect 114-q that connects to and extends transversely to the first deep via 124a to connect the backside wire 144a to a frontside component 104b.
Regarding claim 2, Majhi discloses wherein the local interconnect 114-q is disposed within a layer that includes middle of line contacts 130a-a (fig. 3).
Regarding claim 3, Majhi discloses wherein the local interconnect 114-q extends over a FEOL structure (Device Layer 106) (fig. 3).
Regarding claim 4, Majhi discloses further comprising a second deep via 130a connecting the backside wire 124a to a FEOL structure (fig. 3).
Regarding claim 5, Majhi discloses wherein the second deep via 130a is disposed between gate structures (104a/104b/104c/104d) of FEOL structures in the FEOL region 106 (fig. 3).
Regarding claim 6, Majhi discloses wherein the first deep via 124a is disposed between gate structures (104a/104b/104c/104d) of FEOL structures in the FEOL region 106 (fig. 3).
Regarding claim 7, Majhi discloses wherein the backside wire 144a is disposed transversely to a longitudinal axis of the gate structures (104a/104b/104c/104d) (fig. 3).
Regarding claim 8, Majhi discloses wherein the backside wire 144a is disposed between power nets within the backside interconnect layer (fig. 3 & [0044]).
Regarding claim 9, Majhi discloses wherein the frontside component includes an M1 metal line 110 (fig. 3).
Regarding claim 10, Majhi, in fig. 3, discloses a semiconductor device 100, comprising: front end of line (FEOL) structures (Device Layer 106) disposed between a frontside 110 and a backside 120/140 of the semiconductor device; and an electrical pathway connecting the frontside to the backside, the electrical pathway including: a backside wire 144b disposed within a backside interconnect layer 140; a first deep via 124b (left end) connecting to a first end portion of the backside wire 144b; and a second deep via 124b (right end) connecting to a second end portion the backside wire 144b opposite the first end portion; wherein the first deep via 124b and the second deep via 124b extend between the FEOL structures (124b extend between the gate structures (104a/104b/104c/104d) of the FEOL structures 106) to connect the backside wire 144b to the frontside 110 of the semiconductor device 100.
Regarding claim 11, Majhi discloses wherein the first deep via 124b connects to the frontside 110 by a local interconnect 114 that extends transversely to the first deep via 124b (fig. 3).
Regarding claim 12, Majhi discloses wherein the local interconnect 114 extends over a source/drain region of one of the FEOL structures (fig. 3).
Regarding claim 13, Majhi discloses wherein the first and second deep vias 124b are disposed between gate structures (104a/104b/104c/104d) of the FEOL structures 106 (fig. 3).
Regarding claim 14, Majhi discloses wherein the backside wire 144b is disposed transversely to a longitudinal axis of the gate structures (104a/104b/104c/104d) (fig. 3).
Regarding claim 15, Majhi discloses wherein the backside wire 144b is disposed between power nets within the backside interconnect layer (fig. 3 & [0044]).
Regarding claim 16, Majhi discloses wherein the frontside component includes an M1 metal line 110 (fig. 3).
Regarding claim 17, Majhi, in fig. 3, discloses a semiconductor device 100, comprising: front end of line (FEOL) structures (Device Layer 106) disposed between a frontside 110 and a backside 120/140 of the semiconductor device; a frontside contact layer 114 including frontside contacts 114 to connect to the FEOL structures (gate structures (104a/104b/104c/104d)) from the frontside 110; a backside contact layer 120/140 including backside contacts 124b to connect to the FEOL structures (gate structures (104a/104b/104c/104d)) from the backside 120/140; a backside wire 144b disposed within a backside interconnect layer 144b; a first deep via 130b (left end) extending through the FEOL structures 106 and connecting to the backside wire 144b using the backside contacts 124b; and a second deep via 130b (right end) extending through the FEOL structures 106 and connecting to the backside wire 144b using the backside contacts 124b; wherein the first deep via 130b and the second deep via 130b connect the backside wire 144b to the frontside 110 of the semiconductor device 100 using the frontside contacts 114.
Regarding claim 18, Majhi discloses wherein the first deep via 130b connects to the frontside 110 by a local interconnect 114 that extends transversely to the first deep via 130b over a source/drain region of one of the FEOL structures (fig. 3).
Regarding claim 19, Majhi discloses wherein the first and second deep vias 130b are disposed between gate structures (104a/104b/104c/104d) of the FEOL structures 106 and the backside wire 144b is disposed transverse to the gate structures (104a/104b/104c/104d) (fig. 3).
Regarding claim 20, Majhi discloses wherein the backside wire 144b is disposed between power nets within the backside interconnect layer 144b (fig. 3 & [0044]).
Conclusion
2. Any inquiry concerning this communication or earlier communications from the examiner should be directed to David Vu whose telephone number is (571) 272-1798. The examiner can normally be reached on Monday-Friday from 8:00am to 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempt to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke H can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/DAVID VU/
Primary Examiner, Art Unit 2818