CTNF 18/390,425 CTNF 83782 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-25-01 AIA Applicant’s election without traverse of Group I, Species 1, Embodiment I, Figs. 1-9, Sub-species 1, Figs. 1-4, item 100, claims 1-3 , in the reply filed on April 27, 2026 is acknowledged. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-35 AIA Claim s 1-2 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1, 5 and 7 of copending Application No. 18/438,024 . Although the claims at issue are not identical, they are not patentably distinct from each other because : In regards to claim 1 , 18/438,024 (claim 1) discloses a semiconductor device, comprising: a first electrode; a first semiconductor region located on the first electrode, the first semiconductor region being of a first conductivity type; a second semiconductor region located on the first semiconductor region, the second semiconductor region being of a second conductivity type; a third semiconductor region selectively located on the second semiconductor region, the third semiconductor region being of the first conductivity type; a second electrode located on the third semiconductor region, the second electrode being electrically connected with the third semiconductor region; a third electrode arranged with the second semiconductor region in a second direction and a third direction, the second direction being perpendicular to a first direction, the first direction being from the first electrode toward the second electrode, the third direction being perpendicular to the first and second directions; a first insulating part located between the second semiconductor region and the third electrode in the second and third directions; a fourth electrode arranged with the first semiconductor region and the third electrode in the second and third directions; a second insulating part located between the first semiconductor region and the fourth electrode and between the third electrode and the fourth electrode in the second and third directions; and a fourth semiconductor region located under the third electrode, the fourth semiconductor region being electrically connected with the second electrode, the fourth semiconductor region being of the second conductivity type. In regards to claim 2 , 18/438,024 (claim 5) discloses the device according to claim 1, wherein a lower end of the fourth semiconductor region is positioned lower than a lower end of the fourth electrode . This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. 08-35 AIA Claim 1 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1 and 7 of copending Application No. 18/437,906 . Although the claims at issue are not identical, they are not patentably distinct from each other because : In regards to claim 1 , 18/437,906 (claims 1 and 7) discloses a semiconductor device, comprising: a first electrode; a first semiconductor region located on the first electrode, the first semiconductor region being of a first conductivity type; a second semiconductor region located on the first semiconductor region, the second semiconductor region being of a second conductivity type; a third semiconductor region selectively located on the second semiconductor region, the third semiconductor region being of the first conductivity type; a second electrode located on the third semiconductor region, the second electrode being electrically connected with the third semiconductor region; a third electrode arranged with the second semiconductor region in a second direction and a third direction, the second direction being perpendicular to a first direction, the first direction being from the first electrode toward the second electrode, the third direction being perpendicular to the first and second directions; a first insulating part located between the second semiconductor region and the third electrode in the second and third directions; a fourth electrode arranged with the first semiconductor region and the third electrode in the second and third directions; a second insulating part located between the first semiconductor region and the fourth electrode and between the third electrode and the fourth electrode in the second and third directions; and a fourth semiconductor region located under the third electrode, the fourth semiconductor region being electrically connected with the second electrode, the fourth semiconductor region being of the second conductivity type . This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. 08-35 AIA Claim s 1-2 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1, 4, 7 and 8 of copending Application No. 18/437,854 . Although the claims at issue are not identical, they are not patentably distinct from each other because : In regards to claim 1 , 18/437.854 (claims 1, 7) discloses a semiconductor device, comprising: a first electrode; a first semiconductor region located on the first electrode, the first semiconductor region being of a first conductivity type; a second semiconductor region located on the first semiconductor region, the second semiconductor region being of a second conductivity type; a third semiconductor region selectively located on the second semiconductor region, the third semiconductor region being of the first conductivity type; a second electrode located on the third semiconductor region, the second electrode being electrically connected with the third semiconductor region; a third electrode arranged with the second semiconductor region in a second direction and a third direction, the second direction being perpendicular to a first direction, the first direction being from the first electrode toward the second electrode, the third direction being perpendicular to the first and second directions; a first insulating part located between the second semiconductor region and the third electrode in the second and third directions; a fourth electrode arranged with the first semiconductor region and the third electrode in the second and third directions; a second insulating part located between the first semiconductor region and the fourth electrode and between the third electrode and the fourth electrode in the second and third directions; and a fourth semiconductor region located under the third electrode, the fourth semiconductor region being electrically connected with the second electrode, the fourth semiconductor region being of the second conductivity type. In regards to claim 2 , 18/437.854 (claims 4, 8) discloses The device according to claim 1, wherein a lower end of the fourth semiconductor region is positioned lower than a lower end of the fourth electrode . This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ichinoseki et al. (Ichinoseki) (US 2021/0083108 A1 now 11,322,612 B2) in view of Ding et al. (Ding) (US 2015/0060936 A1) . In regards to claim 1 , Ichinoseki (Figs. 2-4, 10 and associated text) discloses a semiconductor device (items 100, 110) , comprising: a first electrode (item 11) ; a first semiconductor region (item 1) located on the first electrode (item 11) , the first semiconductor region (item 1) being of a first conductivity type (n-type, paragraphs 24, 25) ; a second semiconductor region (item 2) located on the first semiconductor region (item 1) , the second semiconductor region (item 2) being of a second conductivity type (p-type, paragraphs 24, 25) ; a third semiconductor region (item 3) selectively located on the second semiconductor region (item 2) , the third semiconductor region (item 3) being of the first conductivity type (n-type, paragraphs 24, 25) ; a second electrode (item 13) located on the third semiconductor region (item 3) , the second electrode (item 13) being electrically connected with the third semiconductor region (item 3) ; a third electrode (item 10) arranged with the second semiconductor region (item 2) in a second direction (D2 or D3, Fig. 4) and a third direction (D2 or D3, Fig. 4) , the second direction (D2 or D3, Fig. 4) being perpendicular to a first direction (D1, Fig. 4) , the first direction (D1) being from the first electrode (item 11) toward the second electrode (item 13) , the third direction (D2 or D3, Fig. 4) being perpendicular to the first and second directions (D1 and D3 or D1 and D2, Fig. 4) ; a first insulating part (item 10a) located between the second semiconductor region (item 2) and the third electrode (item 10) in the second and third directions (D2 and D3) ; a fourth electrode (item 12) arranged with the first semiconductor region (item 1) and the third electrode (item 10) in the second and third directions (D2 and D3) ; a second insulating part (item 12a) located between the first semiconductor region (item 1) and the fourth electrode (item 12) and between the third electrode (item 10) and the fourth electrode (item 12) in the second and third directions (D2 and D3) ; and a fourth semiconductor region (item 1b, Figs. 10) located under the third electrode (item 10) , the fourth semiconductor region (item 1b, Figs. 10) being electrically connected with the second electrode (item 13) . It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of various embodiments/modification of Ichinoseki for the purpose of reducing the ON-resistance and increase breakdown voltage (paragraphs 68, 69, 75) . Ichinoseki does not specifically disclose the fourth semiconductor region being of the second conductivity type. Ding (paragraphs 31, 32, Figs. 2E-2F-1 and associated text) discloses trench-bottom p-type dopant region (item 130, second conductivity type) dispose below the bottom surface of trench 120 and beneath oxide layers (items 115/125) . Ding explains that the p-type regions function as RESURF regions that improve break-down voltage capability at the bottom (paragraph 31) . Therefore it would have been obvious to one ordinary skill in the art before the effective filing date to incorporate the teachings of Ding for the purpose of maximizing break-down voltage blocking capability (paragraph 31) . In regards to claim 2 , Ichinoseki (Figs. 2-4, 10 and associated text) as modified by Ding (paragraphs 31, 32, Figs. 2E-2F-1 and associated text) discloses wherein a lower end of the fourth semiconductor region (item 1b, Ichinoseki, item 130, Ding) is positioned lower than a lower end of the fourth electrode (item 12) . In regards to claim 3 , Ichinoseki (Figs. 2-4, 10 and associated text) discloses further comprising: a fifth semiconductor region (item 5) located on the second semiconductor region (item 2) and arranged with the third electrode (item 510) in the second and third directions (D2 and D3) , the fifth semiconductor region (item 5) being of the second conductivity type (p-type, paragraph 31) , the fourth semiconductor region (item 1b) being electrically connected with the second electrode (item 13) via the second and fifth semiconductor regions (items 2 and 5) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See all references listed in 892 . Examiner notes that all references listed in 892 could be have been used as primary and/or secondary references. Examiner suggests that the Applicant review each piece of prior art before responding in order to overcome the references listed, but not applied in the above rejection. Examiner also suggests that the Applicant review the prior art from the Office letter, when available, in regards co-pending application 18/437,854, which has been posted, but not mailed yet. All suggestions mentioned above will assist with compact prosecution . Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TELLY D. GREEN Examiner Art Unit 2898 /TELLY D GREEN/Primary Examiner, Art Unit 2898 June 10, 2026 Application/Control Number: 18/390,425 Page 2 Art Unit: 2898 Application/Control Number: 18/390,425 Page 3 Art Unit: 2898 Application/Control Number: 18/390,425 Page 4 Art Unit: 2898 Application/Control Number: 18/390,425 Page 5 Art Unit: 2898 Application/Control Number: 18/390,425 Page 6 Art Unit: 2898 Application/Control Number: 18/390,425 Page 7 Art Unit: 2898 Application/Control Number: 18/390,425 Page 8 Art Unit: 2898 Application/Control Number: 18/390,425 Page 9 Art Unit: 2898 Application/Control Number: 18/390,425 Page 10 Art Unit: 2898 Application/Control Number: 18/390,425 Page 11 Art Unit: 2898
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