DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mishra et al. (US 2019/0001139; hereinafter “Mishra”).
Regarding claim 1, Mishra discloses an electrical stimulation device, comprising: a control circuit; a power supply circuit, providing a first power supply signal; and an electrical stimulation circuit, controlled by the control circuit to generate an electrical stimulation signal according to the first power supply signal, wherein the electrical stimulation signal comprises a first burst signal and a second burst signal; a burst duty cycle of the first burst signal ranges from 0.0005% to 50%, and a burst frequency of the first burst signal ranges from 0.1 Hz to 200 Hz (e.g. ¶¶ 251); the first burst signal is a first monophasic burst signal, the first monophasic burst signal comprises a plurality of first pulses, the second burst signal is a second monophasic burst signal, and the second monophasic burst signal comprises a plurality of second pulses (e.g. ¶¶ 403); and the first pulses have a polarity opposite to that of the second pulses, the first pulses have a first pulse frequency, the second pulses have a second pulse frequency, the first pulse frequency and the second pulse frequency both range from 1000 Hz to 10 million Hz, and the first pulses have a pulse duty cycle ranging from 0.01% to 50% (e.g. ¶¶ 249, 251, etc.).
Regarding claim 18, Mishra discloses an electrical stimulation device, comprising: a control circuit; a power supply circuit, providing a first power supply signal; and an electrical stimulation circuit, controlled by the control circuit to generate an electrical stimulation signal according to the first power supply signal, wherein the electrical stimulation signal comprises a first burst signal and a second burst signal; a burst duty cycle of the first burst signal ranges from 0.0005% to 50%, and a burst frequency of the first burst signal ranges from 0.1 Hz to 200 Hz (e.g. ¶¶ 251); each of the first burst signal and the second burst signal is a biphasic burst signal, and the biphasic burst signal comprises a plurality of first pulses and a plurality of second pulses occurring alternately (e.g. ¶¶ 403); and the first pulses have a polarity opposite to that of the second pulses, the first pulses have a first pulse frequency, the second pulses have a second pulse frequency, the first pulse frequency and the second pulse frequency both range from 1000 Hz to 10 million Hz, and the first pulses have a duty cycle ranging from 0.01% to 50% (e.g. ¶¶ 249, 251, etc.).
Regarding claims 2 and 19, Mishra discloses the first burst signal and the second burst signal occur alternately and are spaced apart by a period of time, and the period of time ranges from 0 seconds to 5 seconds (e.g. ¶¶ 397).
Regarding claim 3, Mishra discloses when charges accumulated by the first monophasic burst signal or the second monophasic burst signal are greater than 20 pC, an electrical stimulation performed by the electrical stimulation signal is an electrical stimulation with sensation (e.g. ¶¶ 249).
Regarding claim 4, Mishra discloses the first burst signal has a burst width ranging from 25x10-9 seconds to 5 seconds, and each of the first pulses has a pulse width ranging from 25x10-16 seconds to 5x10-3 seconds (e.g. ¶¶ 323).
Regarding claim 5, Mishra discloses the first power supply signal has a power ranging from 0.1 milliwatts to 30 milliwatts (e.g. ¶¶ 203).
Regarding claims 6 and 20, Mishra discloses the first power supply signal has a power ranging from 0.1 milliwatts to 30 watts (e.g. ¶¶ 203).
Regarding claims 7 and 21, Mishra discloses the electrical stimulation circuit comprises:a boost circuit, controlled by the control circuit to boost the first power supply signal to generate a second power supply signal, wherein the second power supply signal has a voltage ranging from 0.1 volts to 200 volts (e.g. ¶¶ 392).
Regarding claim 8, Mishra discloses the voltage ranging of the second power supply signal is from 0.1 volts to 100 volts (e.g. ¶¶ 392).
Regarding claim 9, Mishra discloses a first electrode and a second electrode with opposite polarities, wherein the electrical stimulation circuit further comprises: a first output circuit, controlled by the control circuit to generate the first pulses at the first electrode and the second electrode according to the second power supply signal; and a second output circuit, controlled by the control circuit to generate the second pulses at the first electrode and the second electrode according to the second power supply signal (e.g. ¶¶ 249, 251, etc.).
Regarding claim 10, Mishra discloses the first output circuit comprises: a first driving circuit, controlled by the control circuit to emit a first driving signal; a first pulse circuit, receiving the second power supply signal according to the first driving signal and transmitting the second power supply signal to the first electrode; and a second pulse circuit, transmitting the second power supply signal from the second electrode to a reference ground terminal according to the first driving signal, wherein the control circuit controls, according to the first pulse frequency and the pulse duty cycle of the first pulses, the first driving circuit to emit the first driving signal, to enable the first output circuit to generate the first pulses at the first electrode and the second electrode (e.g. ¶¶ 243-249).
Regarding claim 11, Mishra discloses the first pulse circuit comprises: a first transistor having a first input capacitor, wherein the first transistor comprises a first control terminal, a first input terminal, and a first output terminal, the first input capacitor is between the first control terminal and the first input terminal, the first control terminal receives the first driving signal, the first input terminal receives the second power supply signal, and the first output terminal transmits the second power supply signal to the first electrode; and a first resistor, connected in parallel to the first input capacitor, wherein a product of a first resistance value of the first resistor and a first capacitance value of the first input capacitor is less than half of a pulse width of each of the first pulses (e.g. ¶¶ 244).
Regarding claim 12, Mishra discloses the second pulse circuit comprises: a second transistor having a second input capacitor, wherein the second transistor comprises a second control terminal, a second input terminal, and a second output terminal, the second input capacitor is between the second control terminal and the second input terminal, the second control terminal receives the first driving signal, the second input terminal receives the second power supply signal from the second electrode, and the second output terminal transmits the second power supply signal to the reference ground terminal; a second resistor, connected in parallel to the second input capacitor; and a third resistor, located between the first driving circuit and the second control terminal, wherein a product of a third resistance value of the third resistor and a second capacitance value of the second input capacitor is less than half of a pulse width of each of the first pulses (e.g. ¶¶ 243-249).
Regarding claim 13, Mishra discloses the second output circuit comprises: a second driving circuit, controlled by the control circuit to emit a second driving signal; a third pulse circuit, receiving the second power supply signal according to the second driving signal and transmitting the second power supply signal to the second electrode; and a fourth pulse circuit, transmitting the second power supply signal from the first electrode to a reference ground terminal according to the second driving signal, wherein the control circuit controls, according to the second pulse frequency and the pulse duty cycle of the second pulses, the second driving circuit to emit the second driving signal, to enable the second output circuit to generate the second pulses at the first electrode and the second electrode (e.g. ¶¶ 243-249).
Regarding claim 14, Mishra discloses the third pulse circuit comprises: a third transistor having a third input capacitor, wherein the third transistor comprises a third control terminal, a third input terminal, and a third output terminal, the third input capacitor is between the third control terminal and the third input terminal, the third control terminal receives the second driving signal, the third input terminal receives the second power supply signal, and the third output terminal transmits the second power supply signal to the second electrode; and a fifth resistor, connected in parallel to the third input capacitor, wherein a product of a fifth resistance value of the fifth resistor and a third capacitance value of the third input capacitor is less than half of a pulse width of each of the second pulses (e.g. ¶¶ 243-249).
Regarding claim 15, Mishra discloses the fourth pulse circuit comprises: a fourth transistor having a fourth input capacitor, wherein the fourth transistor comprises a fourth control terminal, a fourth input terminal, and a fourth output terminal, the fourth input capacitor is between the fourth control terminal and the fourth input terminal, the fourth control terminal receives the second driving signal, the fourth input terminal receives the second power supply signal from the first electrode, and the fourth output terminal transmits the second power supply signal to the reference ground terminal; a sixth resistor, connected in parallel to the fourth input capacitor; and a seventh resistor, located between the second driving circuit and the fourth control terminal, wherein a product of a seventh resistance value of the seventh resistor and a fourth capacitance value of the fourth input capacitor is less than half of a pulse width of each of the second pulses (e.g. ¶¶ 249).
Regarding claim 16, Mishra discloses the boost circuit comprises: a third changeover switch, wherein the control circuit controls a changeover state of the third changeover switch; an inductor, performing energy storage or release according to the changeover state and the first power supply signal, and generating a first charging signal to serve as the second power supply signal when the changeover state is off, wherein an inductance value of the inductor is in a positive correlation with the first pulse frequency and the second pulse frequency, and an impedance value of the inductor is in a negative correlation with the first pulse frequency and the second pulse frequency; a charging capacitor, performing charging according to the first charging signal, and generating a second charging signal to serve as the second power supply signal when the changeover state is on, wherein a charging capacitance value of the charging capacitor is in a positive correlation with the first pulse frequency and the second pulse frequency; and a blocking switch, located between a node between the third changeover switch and the inductor and the charging capacitor (e.g. ¶¶ 243-249).
Regarding claim 17, Mishra discloses an electrode detection circuit, located between the electrical stimulation circuit and a reference ground terminal and generating a detection signal according to the electrical stimulation signal, wherein the control circuit maintains operating of the electrical stimulation circuit in response to the detection signal and turns off the electrical stimulation circuit when the detection signal is not received (e.g. ¶¶ 91).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michael D’Abreu whose telephone number is (571) 270-3816. The examiner can normally be reached on 7AM-4PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, David Hamaoui can be reached at (571) 270-5625. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL J D'ABREU/Primary Examiner, Art Unit 3796