DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 6-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Watanabe et al. (US 2021/0225424 A1).
Regarding claim 6, Watanabe teaches a method of operating a memory device, the method comprising:
applying a read voltage to a selected word line (Fig. 7, read voltage DR applied to selected work line); and
applying a first pass voltage to adjacent word lines adjacent to the selected word (VREAD is a first pass voltage);
wherein the first pass voltage becomes low when the read voltage becomes high (VREAD voltage is low comparing to voltage applied to WL-SEL. During the period t11 to t12, VREAD is low when the read voltage DR becomes high).
Regarding claim 7, Watanabe further teaches the method of claim 6, wherein the read voltage is applied to the selected word line after the first pass voltage is applied to the adjacent word lines.
Regarding claim 7, Watanabe further teaches the method of claim 6, wherein the read voltage (DR, figure 7) is applied to the selected word line (WL_sel, figure 7) after the first pass voltage (VREAD, figure 7) is applied to the adjacent word lines (W_usel, figure 7) .
Regarding claim 8, Watanabe further teaches the method of claim 6, wherein th voltage (DR,figure 7) becomes low. In figure 7, between period t13-t14, the read voltage DR become low, when the pass voltage VREAD goes high.
Regarding claim 9, Watanabe further teaches the method of claim 6, wherein a variation of the first pass voltage (VREAD,figure 7) increases when a variation of the read voltage (DR, figure 7) increases. In figure 7, between t11 and t12, the variation of VREAD increases when a variation of the read voltage DR increases.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe as applied to claim 6 above, and further in view of Watanabe et al. (US 10,872,673),hereinafter will be referenced Watanabe2 .
Regarding claim 10, Watanabe is silent in teaching wherein a variation of the first pass voltage decreases when a variation of the read voltage decreases.
Watanabe2 disclose a device, wherein a variation of the first pass voltage (VREAD, figure 6) decreases when a variation of the read voltage (CR, figure 6) decreases (In figure 6, after t41, both read voltage CR and pass voltage VREAD decrease).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Watanabe to control the voltages (read voltage and pass voltage) applied the selected word line and the unselected word line, wherein a variation of the first pass voltage decreases when a variation of the read voltage decreases, so as to control the read operation of a memory device as taught by Watanabe2.
Allowable Subject Matter
Claims 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 1-5, 12-19 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
After further search and consideration it is determined that the prior art of record neither anticipated nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach, the following limitation(s) in combination with the remaining claimed limitation:
Claim 1, wherein the first pass voltage is set higher than a reference pass voltage when the read voltage is lower than a reference voltage, and the first pass voltage is set lower than the reference pass voltage when the read voltage is higher than the reference voltage.
Claim 12, a control circuit configured to select main voltage codes in response to a read command, generate offset codes according to the main voltage codes, and output operation codes including the main voltage codes and the offset codes; and a voltage generator configured to output read voltages and pass voltages in response to the operation codes, wherein the voltage generator is configured to output the pass voltages to which an offset voltage is applied according to the offset codes.
Claim 16, voltage generator configured to generate main voltage signals and trimming signals in response to the operation codes, and output read voltages and pass voltages in response to the main voltage signals and the trimming signals, wherein the voltage generator is configured to: output the read voltages in response to the main voltage signals; and apply an offset voltage to the pass voltages in response to the trimming signals
Response to Arguments
Applicant's arguments filed on 10/29/2025 have been fully considered but they are not persuasive.
Applicant’s representative argues at the bottom of page 8 “Meanwhile, claim 6 of the present application discloses a feature in which the first pass voltage becomes low when the read voltage becomes high for the selected word line, thereby describing a correlation between the read voltage and the first pass voltage. However, Watanabe does not disclose any such correlation, and FIG. 7 of Watanabe only illustrates a pattern in which both the read voltage and the pass voltage increase together. Accordingly, Watanabe fails to suggest the above-described technical feature of the presently claimed invention.”
In response, claim 6 uses the phrase “first pass voltage becomes low” and “read voltage becomes high.” The claim did not give a range or a definition what would make a voltage consider low or high. Watanabe teaches WL_usel will bring the voltage at t12 to VREAD which is considered low comparing to the high voltage applied to WL_sel at t12. The claim uses the phrase “when” which defines a point of time where events happening at the time something else occurs. In this case, at time t12, the first pass voltage becomes low (VREAD) when the read voltage becomes high (DR+DK) which is higher than VREAD. Watanabe still teaches the claimed invention. Therefore, the rejection is maintained.
Relevant art:
Lee (US 2022/0366989 A1) teaches a read operation (Fig. 9), first pass voltage becomes low when the read voltage becomes high (during PEQ the unselected WL becomes low comparing to the previous level when selected WL becomes high comparing to the previous level).
Min et al. (US 2024/0192857 A1) teaches a read operation (Fig. 6A), first pass voltage becomes low when the read voltage becomes high (Vpass_1 becomes low and goes down to Vpass_2) when the read voltage becomes high to level VR3)
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM).
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/Khamdan N. Alrobaie/Primary Examiner, Art Unit 2824
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