DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The 112(b) rejection of claims 1, 2, 5, 13 and 20 is withdrawn in view of Applicant’s amendment.
Claims 1, 2, 5, 13 and 20 have been amended; and claims 1-20 are currently pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-13, 15, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over LEE (US 2020/0152691 A1, hereinafter “LEE”) in view of OH et al. (US 2018/0323236 A1, hereinafter “OH”).
In regards to claim 1, LEE discloses (See, for example, Figs. 8 and 10) An optical semiconductor element, comprising:
a substrate (100, See Fig. 10B); and
a first cell (LES1) and a second cell (LES2) formed on the substrate (100),
wherein the first cell (LES1) includes at least a first semiconductor layer (102),
the second cell (LES2) is configured to generate or detect light (See, for example, Par [0125]),
a first electrode (CVP/PT3 is arranged on the top surface of LES1) electrically connected
to the first semiconductor layer (for example, 102) is arranged on a top surface (through
CPD at portion PT3 is arranged on top surface (passivation layer PVT), See for example,
Par [0132], [0134]-[0136]) of the first cell (LES1),
the first cell (LES1) and the second cell (LES2) are electrically connected to each other
by a first wiring layer (CPD includes first portion PT1, second portion PT2, and third portion PT3, See for example, Par [0136]) extending from the top surface of the first cell (LES1) to the second cell (LES2),
a first insulating layer (PVT) is arranged on the top surface of the first cell (LES1), and
the first electrode (CVP/PT3) is exposed to outside through an opening formed in the first insulating layer (DES, See, for example, Pars [0132], [0136]),
the first wiring layer (CPD, portions PT1) is spaced apart from the first electrode (CPV)
on the top surface of the first cell (LES1), and is electrically connected to the first
electrode (CPV) via the first semiconductor layer (for example, 102, See Par [0153]),
a portion of the first wiring layer (for example PT1) arranged on the top surface of the
first cell (LES1) includes a contact region (VP5, VP6) in contact with the first
semiconductor layer (102, thru CVP), and
a width of the contact region (VP5, VP6) in a predetermined direction along a width
direction of the first wiring layer (CPD) is equal to or greater than a width of the opening
(Openings for VP5, VP6) in the predetermined direction.
While LEE does not explicitly teach that the contact region width equals or exceeds the
opening width, Lee teaches that the pads are designed with sufficient area for electrical
contact and bonding (See, Pars [0075]-[0076], and [0080]-[0082]) to be electrically
stable.
Therefore, it would have been obvious to one having ordinary skill in the art before the
effective filing date of the invention to configure the contact region width to be equal or
greater than the opening width as a matter of routine design optimization to ensure
reliable electrical contact and current carrying capacity. See MPEP §2144.05 (II)(A).
LEE fails to explicitly teach that the first wiring layer is spaced apart from the first electrode on
the top surface of the first cell, is not directly connected to the first electrode, and is electrically
connected to the first electrode via the first semiconductor layer.
OH while disclosing a highly reliable light emitting diode teaches (See, for example, Figs. 1, 2 and 4E) the first wiring layer is spaced apart
from the first electrode on the top surface of the first cell (the connector 35ab and the first pad
metal 35a are separated metal features disposed on the lower insulation layer 33 over the last
light emitting cell C4; OH states that the first and second pad metal layers 35a, 35b do not
connect the light emitting cells to each other, are therefore distinguished from the connector
35ab, and are spaced apart from the connector(s). The first pad metal layer 35a is limitedly
disposed in an upper region of the second conductivity type semiconductor layer 27 of the last
light emitting cell C4, whereas the connector 35ab extends across the cell isolation (ISO) region
toward the adjacent light emitting cell C3),
is not directly connected to the first electrode (the connector 35ab and the first pad metal layer
35a are patterned as discrete features at the same level on the lower insulation layer 33 and
nowhere contact one another; the upper insulation layer 37 subsequently covers and seals the
upper and side surfaces of the connector 35ab, See also Figs. 4E-4F),
and is electrically connected to the first electrode via the first semiconductor layer (within the
last light emitting cell C4, the first pad metal layer 35a is electrically connected to, and may
directly contact, the first conductivity type semiconductor layer 23 through a first opening 33a of
the lower insulation layer 33; the connector 35ab is separately electrically connected to, and
may directly contact, the same first conductivity type semiconductor layer 23 through another
first opening 33a exposing the layer 23 in a bay 30a formed through the second conductivity type
semiconductor 27 and the active layer 25. Accordingly, the sole conductive path between the
connector 35ab and the first pad metal layer 35a is through the first conductivity type
semiconductor layer 23 of the light emitting cell C4).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective
filing date of the invention to configure the wiring layer of LEE to be laterally separated from,
and not in direct contact with, the electrode, as taught by OH because this would help prevent
short-circuit failure caused by probe or particle damage to the overlying insulation layer.
In regards to claim 2, LEE discloses (See, for example, Figs. 8 and 10) an entire width of a
portion of the first wiring layer (CPD) extending from the top surface of the first cell (LES1) to
the second cell (LES2) is equal to or greater than the width of the opening in the predetermined direction (the second portion PT2 and third portion PT3 of common pad CPD have a second width W2, greater that W1. See, Par [0136], and See also Fig. 8B).
In regards to claim 3, LEE discloses (See, for example, Figs. 8 and 10) the first electrode includes a planned contact region with which solder (conductive parts CP1-CP4, See, for example, Fig. 15) comes into contact when being electrically connected to an external member
(MSUB).
Though LEE is silent about the specific shapes of the planned contact region having a circular shape when viewed from a thickness direction of the substrate, LEE teaches VP1-VP6 are shown with circular cross-sections in top views (See, for example, Fig. 8B … shows circular through pattern openings).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to provide a circular shape regions for uniform current distribution and compatibility with spherical solder balls, and also because changes in shape are generally recognized as a matter of design choice. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also §2144.04(IV)(B).
In regards to claim 4, LEE discloses (See, for example, Figs. 8 and 10) the first electrode (CVP/PT3) includes a first layer (CVP) and a second layer (PT3) arranged on a side of the substrate with respect to the first layer (CVP).
In regards to claim 5, LEE discloses (See, for example, Figs. 8 and 10) the width of the contact region (where PT3 contacts CVP) in the predetermined direction is equal to or greater than a width of the first layer (CVP) in the predetermined direction.
In regards to claim 6, LEE discloses (See, for example, Figs. 8 and 10) the first wiring layer (CPD) has the same layer structure as the second layer (PT3) of the first electrode (CVP/PT3).
In regards to claim 7, LEE discloses (See, for example, Figs. 8 and 10) the first electrode (CVP/PT3) is formed of a material containing metal (See, for example, Par [0149])
However, LEE is silent about the first electrode being formed of a material containing at least Au.
It is well known in the art to use Au as electrode material for semiconductor devices due to gold’s properties of excellent conductivity, corrosion resistance, and reliable ohmic contact formation.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to form the first electrode of a material containing at least Au because it is well known in the art to use Au as electrode material for semiconductor devices due to gold’s properties of excellent conductivity, corrosion resistance, and reliable ohmic contact formation.
In regards to claim 8, LEE discloses (See, for example, Figs. 8 and 10) the second cell (LES2) includes an optical layer that is an active layer for generating light or an absorption layer for absorbing light (LE1, LE2, LE3 each include active layers 104, 204, and 304) for generating
light (See, Pars [0064 and [0065]), a second semiconductor layer arranged on a side opposite to the substrate with respect to the optical layer (106, 206, 306), and a third semiconductor layer (102, 202, 302) arranged on a side of the substrate with respect to the optical layer
In regards to claim 9, LEE discloses (See, for example, Fig. 13A) a layer structure of the first cell (LES1) is different from a layer structure of the second cell (LES2).
In regards to claim 10, LEE discloses (See, for example, Figs. 8 and 10) a layer structure of the first cell (LES1) is the same as a layer structure (See, for example, Pars [0125]-[0127]) of the second cell (LES2).
In regards to claim 11, LEE discloses (See, for example, Figs. 9A) each of the first cell (LES1) and the second cell (LES2) has a mesa structure including a side surface inclined with respect to a thickness direction of the substrate (See, Mesa structures with etched portions having first width W1, second width W2, and third width W3, creating a stepped/inclined side surfaces. Figs. 9A-9C and Pars [0146]-[0147]).
In regards to claim 12, LEE discloses (See, for example, Figs. 8 and 10) a second insulating layer (DES) is arranged between the first wiring layer (CPD) and a side surface of the first cell (LES1), and the second insulating layer is provided so as to reach the top surface of the first cell (LES1).
In regards to claim 13, LEE discloses (See, for example, Figs. 9) a third cell formed on the substrate (additional light emitting structures can be formed , See Fig. 9C and Pars [0157]-[0159]) , wherein the third cell is configured to generate or detect light and is electrically connected to the second cell by a second wiring layer (See, Par [0159]).
While LEE does not explicitly teach that the width of the contact region in the predetermined direction is larger than a width of a portion of the second wiring layer between the second cell and the third cell, Lee teaches that the pads are designed with sufficient area for electrical contact and bonding (See, Pars [0075]-[0076], and [0080]-[0082]) to be electrically stable.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to configure the contact region width to be equal or greater than the opening width as a matter of routine design optimization to ensure reliable electrical contact and current carrying capacity. See MPEP §2144.05 (II)(A).
In regards to claim 15, LEE discloses (See, for example, Figs. 8 and 10) the first wiring layer (CPD including PT1, PT2, and PT3) includes an extending portion (PT2) that extends so as to
surround an outer edge of the second cell (LES2) when viewed from a thickness direction of the substrate (100).
In regards to claim 17, LEE discloses (See, for example, Figs. 8 and 10) the first cell (LES1) and the second cell (LES2) are spaced apart from each other by a groove portion (where DES is placed) formed in the substrate (100).
In regards to claim 18, LEE discloses (See, for example, Figs. 8 and 10) the first cell (LES1) has the same shape as the second cell (LES2) when viewed from a thickness direction of the substrate (100).
In regards to claim 19, LEE discloses (See, for example, Figs. 7C and 8, See also Pars [0113]-[0115]) the first electrode (CVP) includes a planned contact region (CP4 is place, See Fig. 7C, See also Pars [0086] and [0121]) with which solder (CP4) comes into contact when being electrically connected to an external member (MSUB), a third insulating layer (PVT2, See, Fig. 7C) is arranged on the first insulating layer (PVT1), and the first electrode (CVP/PT3) is exposed to outside through an opening formed in the third insulating layer (PVT2), and the planned contact region is formed by a portion of the first electrode (CVP/PT3) exposed from the opening formed in the third insulating layer (PVT2).
In regards to claim 20, LEE discloses (See, for example, Figs. 8 and 10) a distance from a portion of the first wiring layer (PT1, CPD) arranged on the top surface of the first cell (LES1) to the first electrode (for example, CVP/PT3) is smaller than a width of the opening in the predetermined direction.
Allowable Subject Matter
Claims 14 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-30423042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893
