DETAILED ACTION
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/29/2026 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Kim ‘669 (US 20200365669 A1)
Regarding claim 1, Kim ‘669 discloses (Fig. 4, below) a device, comprising:
a first pixel (X, Fig. 4) having:
a first emission area (EA1, Fig. 5);
a second emission area (EA2, Fig. 5) surrounds the first emission area;
a first non-emission area (NEA1, Fig. 5) between the first emission area and the second emission area, the first non-emission area surrounds the first emission area;
a second non-emission area (NEA2) around the pixel, the first non-emission area spaced from the second non-emission area by the second emission area, the second non-emission area including: a pattern (features in NEA2 and outside the immediate first pixel, Fig. 4) that includes a first portion spaced from a second portion by a distance;
a second pixel (Fig. 3) spaced from the first pixel by the second non-emission area;
(Fig. 4) a substrate (SUB), the first emission area and the second non-emission area being on the substrate; and
(Fig. 4) a transistor structure (TR) in the first emission area, the transistor structure including an electrode (E1) on the substrate, wherein the pattern includes a spacer structure (Bank) that overlaps at least a portion of the electrode.
Regarding claim 2, Kim ‘669 discloses (Fig. 4) the device of claim 1 wherein the first portion of the pattern is a spacer (Bank) and the second portion of the pattern is a metal pattern (AE).
Regarding claim 3, Kim ‘669 discloses the device of claim 1, comprising (Fig. 4 above):
a first protective layer (INF);
a second protective layer (INS) on the first protective layer;
a plurality of first electrodes (E1);
a bank (Bank) on the second protective layer,
a common organic layer (EL) in an area including the plurality of first electrodes (E1) and the bank (Bank), the common organic layer being connected to the plurality of first electrodes.
Regarding claim 5, Kim ‘669 discloses (Fig. 4 reproduced and annotated, below) the device of claim 3 wherein the second protective layer has a plurality of first openings (H1, exposed by INS), the plurality of first electrodes being on the plurality of first openings, the bank having a second opening (H2) in an area between the two adjacent first electrodes among the plurality of first electrodes, the first and second portions of the pattern being a metal pattern (auxiliary electrode AE, E1).
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Claims 21-24, 26 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Cho (US 20160126304 A1)
Regarding claim 21, Cho discloses (Fig. 5 below) a device, comprising:
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a substrate (100);
a first protective layer (150) on the substrate;
a second protective layer (170) on the first protective layer;
a plurality of first electrodes (210) on the second protective layer;
a bank (180) on the second protective layer (170), the bank having a first curved portion (annotated first bank portion) on the first protective layer (150) and on the second protective layer and a second curved portion (annotated second bank portion) on the second protective layer;
a common organic layer (221, ¶¶ [0075, 0080]) on the first protective layer, on the first curved portion of the bank, and on the second curved portion of the bank, and an emission layer (222) on the common organic layer (221), the emission layer having an opening (OP2) that exposes the second curved portion of the ba
Regarding claim 22, Cho discloses (Fig. 5 above) the device of claim 21, comprising a pattern (352) on the second protective layer, the pattern including a first portion (353) that aligns with a non-curved portion of the bank.
Regarding claim 23, Cho discloses (Fig. 5 above) the device of claim 22 wherein the pattern includes a second portion (532) that aligns with an end of the first curved portion of the bank, the second portion of the pattern being a conductive material (352 is auxiliary line to connect to the external power source, Fig. 2).
Regarding claim 24, Cho discloses (Fig. 5 above) the device of claim 23 wherein the device of claim 21 wherein the first curved portion is spaced from the second curved portion by a first electrode (anode 210) of the plurality of first electrodes.
Regarding claim 26, Cho discloses (Fig. 5 above) the device of claim 21 wherein the emission layer (222) is partially overlapping the first portion of the curved bank (annotated first curved bank).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Kim ‘669 (US 20200365669 A1) in view of Kim ‘498 (US 20160126498 A1).
Regarding claim 4, Kim ‘669 discloses the device of claim 3 and is silent to the spacer being on the bank.
Kim ‘498, in the same field of endeavor, discloses (Fig. 2, ¶ [0074] a bank (244) and a spacer (245) in the non-emission area wherein the spacer is optional to maintain a desired gap or distance between the substrates. Such, one of ordinary skill in the art before the filing date of the invention would have added the spacer acting as a distance adjustment between the substrates as taught by Kim ‘498 to the device of Kim ‘669 to maintain a desired gap between the substrates.
Claim 6, 13-15, 18-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kim ‘669 (US 20200365669 A1) in view of Cho (US 20160126304 A1).
Regarding claim 6, Kim ‘669 discloses the device of claim 5 but silent regarding the common organic layer is on the metal pattern.
Cho, in the same field of endeavor, discloses (Fig. 5) an organic layer (first intermediate layer 221, ¶ [0072]) extended to be on the metal pattern (CH).
The extension of common organic layer 221 to opening OP2 allowing cathode (230) to contact with the auxiliary line 530 in the contact region CNT (¶ [0083]) and eventually connect to the main power lines (510, 520, ¶ [0045], Fig. 2).
Hence one of ordinary skill in the art before the filling date of the invention would have applied the extended common organic layer of Cho to the display device of Kim ‘669 to tie both organic layer and the cathode to the external power source.
Regarding claim 13, Kim ‘669 discloses the display of claim 1 but is silent regarding the non-emission area including a planarization layer wherein a first curved bank portion and a second curved bank portion formed between a first opening on it and an organic layer formed on the bank portions and the first opening.
Cho discloses (Fig. 5) a planarization layer (170) on an insulation layer (150) wherein bank curved portions (180) are formed between openings (OP2) and organic layers (221, 222, ¶¶ [0075-0076]) extending from the emission area to cover the banks and the openings.
The use of the planarization layer would ensure the levelness of the surface for laying light emitting elements and enhance overall performance of the device.
Therefore, one of ordinary skill in the art before the before the filing date of the invention would have adapted the planarization of Cho to the protective layer of Kim ‘669 to achieve a planar surface for leveling light emitting components for better performance. The modification of Cho to Kim ‘669 would result in a planarization on the second protective layer. Moreover, skilled artisans would have appreciated the benefits of extending the organic layer from the emission area to cover the openings in the non-emission area of Cho to connect the organic layer with external power source. One of ordinary skill in the art before the filling date of the invention would have applied the voltage-connecting-to- organic-layer practice of Cho to the device of Kim ‘669 to get a voltage control over the organic layer.
Regarding claim 14, Kim ‘669 discloses (Fig. 4 above, Fig. 1) a display apparatus, comprising:
a first protective layer disposed on a substrate (INF);
a second protective layer located on the first protective layer (INS), the second protective layer having a plurality of first openings (H4) and a second opening (H2);
a plurality of first electrodes (E1) located on the plurality of first openings;
a bank (BANK, PAS) covering the second protective layer, the bank having a plurality of third openings (H1) exposing the plurality of first electrodes and a fourth opening (H3) overlapping the second opening (H2);
a common organic layer (EL) located in an area including the plurality of first electrodes and the bank, the common organic layer being disposed along a surface curve of the plurality of third openings (H1), and an emission layer (EL) on the common organic layer (EL)
Kim ‘669 is silent to the organic layer including on the metal pattern (fourth opening) and emission layer having an opening that exposes the bank around the metal pattern (fourth opening).
Cho, in the same field of endeavor, discloses (Fig. 5) an organic layer (first intermediate layer 221, ¶ [0072]) extended to be on the metal pattern (532) in the opening (OP2) that exposes the bank around the metal pattern (532)
The extension of common organic layer 221 to opening OP2 allowing cathode (230) to contact with the auxiliary line 530 in the contact region CNT (¶ [0083]) and eventually connecting to main power lines (510, 520, ¶ [0045], Fig. 2). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the metal pattern opening of Kim ‘669 with the metal pattern opening of Cho, extending the organic layer to the metal pattern opening that exposes the bank around the metal pattern. Doing so would allow for the cathode to connect to the main power lines.
Regarding claim 15, Kim ‘669 in view of Cho discloses the display apparatus of claim 14, comprising:
a first pixel element (EA1 of first pixel, Fig. 1); a second pixel element (EA1 of second pixel adjacent to the first pixel, Fig. 1); and a pattern (BANK, PAS, AE) on the second protective layer (BANK on INS, Fig. 4), the pattern including a plurality of portions (BANK, AE) between the first pixel element and the second pixel element (between EA1 of respective first and second pixel elements, Fig. 1).
Regarding claim 18, Kim ‘669 in view of Cho discloses (Fig. 4 above) the display apparatus of claim 14, wherein the bank (PAS) around the fourth opening (H3) covers an inclined surface the second protective layer exposed through the second opening (H2).
Regarding claim 19, Kim ‘669 in view of Cho discloses (Fig. 4 above) the display apparatus of claim 14, wherein the second opening (H2) is disposed on an outer periphery of each of two neighboring first electrodes among the plurality of first electrodes (H2 is disclosed in NEA2 between the respective adjacent pixels according to Fig. 1).
Regarding claim 20, Kim ‘669 in view of Cho discloses (Fig. 4 above) the display apparatus of claim 14, wherein each of the plurality of first electrodes includes an inclined portion disposed on an inclined surface of the second protective layer exposed by the first opening and configured to reflect light.
Claim 7-12 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kim ‘669 (US 20200365669 A1) in view of Cho (US 20160126304 A1) and Omoto (US 20120187425 A1).
Regarding claim 7, Kim ‘669 in view of Cho discloses the device of claim 6 but is silent to the metal patterns being grounded.
Omoto discloses (Fig. 12, ¶ [0120-0121]) an organic EL display wherein the charge injection layer 214 (organic layer) is connected to the metal interconnection 90 to suppress the induced current caused by the rapid change in the potential of a driven pixel to a lower potential than the anode potential.
Omoto further discloses in ¶ [0125] the potential of 90 is set to be any potential as long as it lower than the anode potential.
While Omoto is silent of potential of interconnection 90 to be set to zero, Omoto discloses the potential to be set to any value below a threshold (anode potential), such that where the general conditions of a claim are disclosed in the prior art (potential levels), it is not inventive to discover the optimum or workable ranges (zero) by routine optimization. MPEP 2144.05
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to ground the metal portion as taught by Omoto, to ensure unintended pixels not being turned on for better color performance.
Regarding claim 8, Kim ‘669 in view of Cho and Omoto discloses (reproduced Fig. 4 above) the device of claim 7, wherein the second protective layer includes a third opening (H3) overlapping the second opening (H2), and at least a portion of the metal pattern is on the first protective layer exposed by the third opening.
Regarding claim 9, Kim ‘669 in view of Cho discloses (reproduced Fig. 4 above) the device of claim 8, wherein the bank (BANK, PAS) covers an inclined surface of the second protective layer exposed by the third opening.
Regarding claim 10, Kim ‘669 in view of Cho discloses (Fig. 4 above) the device of claim 9, wherein the metal pattern is located on a same layer as the first electrode (both on INF).
Regarding claim 11, Kim ‘669 in view of Cho discloses (Fig. 4 above) the device of claim 10, wherein the metal pattern surrounds the first electrode while being spaced apart from an outside of the first electrode.
Regarding claim 12, Kim ‘669 in view of Cho discloses (Fig. 4 above) the device of claim 11, wherein each of the plurality of first electrodes includes an inclined portion on an inclined surface of the second protective layer exposed by the first opening and configured to reflect light (EA1).
Claim 16-17 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kim ‘669 (US 20200365669 A1) in view of Cho (US 20160126304 A1) and Kim ‘498 (US 20160126498 A1).
Regarding claim 16, Kim ‘669 in view of Cho discloses the display apparatus of claim 15 and is silent to a first portion of the pattern being a dielectric (polyimide) spacer on the bank.
Kim ‘498, in the same field of endeavor, discloses (Fig. 2, ¶ [0074] a bank (244) and a spacer (245) in the non-emission area wherein the spacer optionally maintains a desired gap or distance between the substrates. Such, one of ordinary skill in the art before the filing date of the invention would have added the spacer acting as a distance adjustment between the substrates as taught by Kim ‘498 to the modified device of Kim ‘669 by Cho to maintain a desired gap between the substrates.
Regarding claim 17, Kim ‘669 in view of Cho discloses the display of claim 16, Kim ‘669 further discloses (reproduced Fig. 4 above) the second portion of the pattern (BANK, PAS, AE) is a metal pattern (AE).
Claims 27-32, 35-36 are rejected under 35 U.S.C. 103 as being unpatentable by Cho (US 20160126304 A1) in view of Kim ‘498 ((US 20160126498 A1).
Regarding claim 27, Cho discloses (Fig. 5 above) a device, comprising:
a non-emission area of a pixel (outer area from anode 210) the non-emission area including:
a planarization layer (170);
a first bank portion (annotated first bank portion) on the planarization layer;
a second bank portion (annotated second bank portion) on the planarization layer;
a first opening (annotated first opening) between the first bank portion and the second bank portion;
a common organic layer (hole transport layer 221, ¶¶ [0075, 0080]), on the first bank portion, the second bank portion, and the first opening (OP2),
a substrate (100), the non-emission area being on the substrate; an emission area (222) on the substrate and surrounded by the non-emission area; and a transistor structure (TFT) in the emission area, the transistor structure including an electrode (210) on the substrate.
Cho is silent regarding wherein the non-emission area further includes a pattern structure having a spacer structure that overlaps at least a portion of the electrode.
Kim ‘498, in the same field of endeavor, discloses (Fig. 2, ¶ [0074] a bank (244) and a spacer (245) in the non-emission area wherein the spacer is optional to maintain a desired gap or distance between the substrates. Such, one of ordinary skill in the art before the filing date of the invention would have added the spacer acting as a distance adjustment between the substrates as taught by Kim ‘498 to the device of Cho to maintain a desired gap between the substrates.
Regarding claim 28, Cho in view of Kim ‘498 discloses (Fig. 5 above) the device of claim 27 wherein the first and second bank portions are curved portions.
Regarding claim 29, Cho in view of Kim ‘498 discloses the device of claim 28 wherein the pattern structure (532) interacts with the first bank portion and the second bank portion.
Regarding claim 30, Cho in view of Kim ‘498 discloses the device of claim 29. The modified structure of Cho including the spacer in the non-emission area which is on the first bank portion.
Regarding claim 31, Cho in view of Kim ‘498 discloses the device of claim 30. Cho further discloses (Fig. 5 above) a metal structure (352) aligned with the second bank portion (annotated second bank portions).
Regarding claim 32, Cho in view of Kim ‘498 discloses the device of claim 28. Cho further discloses wherein the planarization layer includes a first portion (portion on left side of contact hole 532) separated from a second portion (portion on right side of contact hole 532) by the first opening.
Regarding claim 35, Cho in view of Kim ‘498 discloses (Fig. 5 above) the device of claim 27 wherein the non-emission area includes an electrode layer (532) that overlaps a first portion (annotated NEA1) of the planarization layer, is in the first opening, and overlaps a second portion (annotated NEA) of the planarization layer.
Regarding claim 36, Cho in view of Kim ‘498 discloses (Fig. 5 above) the device of claim 35 wherein the non-emission area includes a second opening (CH in NEA1) in the electrode layer that is on the first portion of the planarization layer and a third opening (CH in NEA) in the electrode layer that is on the second portion of the planarization layer.
Claim 37-39 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Cho (US 20160126304 A1) in view of in view of Kim ‘498 ((US 20160126498 A1) and Kim ‘669 (US 20200365669 A1)
Regarding claim 37, Cho in view of Kim ‘498 discloses the device of claim 27. Cho further discloses (Fig. 5 above) comprising:
an active layer (310 between gate insulating layer 130 and gate electrode 320, ¶ [0067]) on the substrate, the active layer being partially in the emission area,
wherein the planarization layer (170) on the substrate;
wherein the first bank portion (annotated first bank portion) is spaced from the second bank portion (annotated second bank portion) by the emission area;
wherein the pattern structure (532) that interacts with the first bank portion.
Cho is silent regarding the active layer being partially in the emission area and partially in the non-emission area;
Kim ‘669, an analogous art, discloses an active layer (ACT, Fig. 4 above) of the transistor expanding under the gate and the source/drain region to cover both emission and non-emission areas.
One of ordinary skill in the art would have incorporated the transistor of Kim ‘669 into the transistor of Cho as a matter of design options supported by routine optimization. As such, it would have been obvious to a person of ordinary skill in art before the filing date of the invention to substitute the transistor of Cho with the transistor of Kim ‘669 through the routine experiment.
The substitution of Cho transistor for Kim ‘669 transistor would result for the transistor to overlap the emission area and the non-emission area.
Regarding claim 38, Cho in view of Kim ‘498 and Kim ‘669 discloses the device of claim 37. Cho’s active layer as modified by Kim ‘669 expanding the emission and non-emission area. The spacer of Kim ‘498 is located in the non-emission area close to the emission area. Adding the spacer of Kim ‘498 to the modified device of Cho would result for the spacer overlapping the active area in the non-emission area.
Regarding claim 39, Cho in view of Kim ‘669 and Kim ‘498 discloses the device of claim 38. Cho further discloses comprising a trench (first opening, Cho Fig. 5 above) in the planarization layer, wherein the spacer aligns with the trench and aligns with the end of the active layer.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee (US 9000428 B2) and Kim ‘669 (US 20170279079 A1) disclose the extension of the cathode forming curved bank portions in the non-emission area of each pixel.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T HOANG whose telephone number is (571)272-5622. The examiner can normally be reached M-F 8:00 - 5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DTH/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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