Prosecution Insights
Last updated: April 19, 2026
Application No. 18/390,639

LIGHT-EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME

Non-Final OA §102§103
Filed
Dec 20, 2023
Examiner
WALL, VINCENT
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Anhui San'an Optoelectronics Co., Ltd.
OA Round
1 (Non-Final)
62%
Grant Probability
Moderate
1-2
OA Rounds
2y 8m
To Grant
87%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allow Rate
488 granted / 793 resolved
-6.5% vs TC avg
Strong +25% interview lift
Without
With
+25.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
52 currently pending
Career history
845
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
48.9%
+8.9% vs TC avg
§102
16.9%
-23.1% vs TC avg
§112
27.2%
-12.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 793 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on December 20, 2023 considered by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3, 5, 7, 9-16, 18, and 20 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Nagata et al. (US 2018/0019374 A1) (“Nagata”). Regarding claims 1, and 18, Nagata teaches at least in figures 1-2: a first type semiconductor (130) layer having an upper surface (top surface of 130); a stress relief layer (150) that is disposed on said upper surface of said first type semiconductor layer (130) and that includes at least one first repeating unit (figure 2 shows 150 is a repeating structure) containing a first well layer (151) and a first barrier layer (152) being alternately stacked (they are so stacked); an active layer (160) that is disposed on said stress relief layer (150) opposite to said first type semiconductor layer (130) and that includes at least one second repeating unit (figure 2 shows 160 is a repeating structure) containing a second well layer (161) and a second barrier layer (163) being alternately stacked (they are so stacked); a second type semiconductor layer (172) disposed on said active layer (160) opposite to said stress relief layer (150); a first electrode (N1) electrically connected to said first type semiconductor layer (130); and a second electrode (P1) electrically connected to said second type semiconductor layer (172), wherein, said first well layer (151) is made of a material including In (¶ 0156); said second well layer (161) is made of a material including In (¶ 0044); and Regarding the limitation, said stress relief layer has an average energy bandgap that is smaller than an average energy bandgap of said active layer. The above limitation can be considered a characteristic of the claimed materials above. Because the prior art teaches the claimed materials it would be inherent that it would have the same characteristic. MPEP 2112. Additionally, or alternatively, because the prior art teaches the same claimed materials it would have been obvious to one of ordinary skill in the art that the prior art would have the claimed characteristic of said materials. MPEP 2112. See MPEP 2112(III). Regarding claim 2, Nagata teaches at least in figures 1-2: wherein said first well layer (151) has an energy bandgap that is greater than an energy bandgap of said second well layer (161) (This claim is rejected for the same reasons as claim 1 above in that the prior art teaches the same claimed materials and there it would be inherent, or obvious, that the prior art would have this same characteristic.). Regarding claim 3, Nagata teaches at least in figures 1-2: wherein said first barrier layer (152) has an energy bandgap that is smaller than an energy bandgap of said second barrier layer (163) (This claim is rejected for the same reasons as claim 1 above in that the prior art teaches the same claimed materials and there it would be inherent, or obvious, that the prior art would have this same characteristic.). Regarding claim 5, Nagata teaches at least in figures 1-2: wherein the material for making said first well layer (151) is represented by a chemical formula of Inx1Gal-x1N (151 is InGaN. InGaN is a known way to generically write the claimed formula), and a material for making said first barrier layer (152) is represented by a chemical formula of Aly1Inz1Ga(1-y1-z1)N (152 is GaN, which is the result when y1=0 and z1=0). Regarding claim 7, Nagata teaches at least in figures 1-2: wherein the material for making said second well layer (161) is represented by a chemical formula of Inx2Ga1-x2N (¶ 0043, where 161 is InGaN; InGaN is a known way to generically write the claimed formula), and the material for making said second barrier layer (163) is represented by a chemical formula of Aly2Inz2Ga1-y2-z2N (¶¶ 0043, where 163 is AlGaN, when z=0; AlGaN is a generic way to write AlInGaN when In is zero.). Regarding claim 9, Nagata teaches at least in figures 1-2: wherein said stress relief unit (150) includes a plurality of first repeating units each containing said first well layer (151) and said first barrier layer (152), said first well layers (151) and said first barrier layers (152) in said stress relief unit being alternately stacked on one another This is so shown in figure 2). Regarding claim 10, Nagata teaches at least in figures 1-2: wherein said active layer (160) includes a plurality of second repeating units each containing said second well layer (161) and said second barrier layer (163), said second well layers (161) and said second barrier layers (163) in said active layer being alternately stacked on one another (this is shown in figure 2). Regarding claim 11, Nagata teaches at least in figures 1-2: wherein each of said first well layer (151), said first barrier layer (152) and said second well layer (161) is independently formed as one of a single-layer structure and a multi-layered structure having multiple sub-layers (this is a product-by-process limitation as can be seen in figure 1 elements 150 and 160 are single layer structures formed by multi-layers shown in figure 2). Regarding claim 12, Nagata teaches at least in figures 1-2: wherein said second barrier layer (163) is formed with multiple sub-layers (this is a product-by-process limitation, as shown in figure 2 there are multiple sub-layers of 163), said sub-layers of each of said first well layer (151), said first barrier layer (152), said second well layer (161) and said second barrier layer (163) having an energy bandgap that is different from one another (this would have been inherent, or obvious, based upon the material each of the layers are made of). Regarding claims 13, and 20, Nagata teaches at least in figures 1-2: wherein said upper surface of said first type semiconductor layer (130) has an electrode contact region (region where N1 is) which is spaced apart from said stress relief layer (150) and which has a doping concentration that is greater than 8 x 1018cm-3 (¶ 0037, where the doping concentration can be higher than 1x1018cm-3. This means it can be higher than 8 x 1018cm-3), said first electrode (N1) being disposed on said electrode contact region (region where N1 is). Regarding claim 14, Nagata teaches at least in figures 1-2: further comprising an electron blocking layer (171) disposed between said second type semiconductor layer (172) and said active layer (160). Regarding claim 15, Nagata teaches at least in figures 1-2: further comprising a contact resistance reducing layer (180) disposed between said second type semiconductor layer (172) and said second electrode (P1). Regarding claim 16, Nagata teaches at least in figures 1-2: further comprising a current spreading layer (190) disposed between said second type semiconductor layer (172) and said second electrode (P1). Claim(s) 4, 6, 8, 19 is/are rejected under 35 U.S.C. 103 as obvious over Nagata. Regarding claim 4, Nagata teaches at least in figures 1-2: wherein said first well layer (151) has an indium (In) content that is smaller than an indium (In) content of said second well layer (161) (¶¶ 0051-62, where one can adjust the concentration of In in 151; See also figures 9-10. Based upon this it would have been obvious that one of ordinary skill in the to optimize the amount of In in the first well layer 151 such that it would be lower than the amount of In in layer 161. This is because as shown in the above figures the amount of In can be lowered along a range of values. As such, it would have been obvious that following the directions of Nagata that one would obviously arrive at the claimed feature. Regarding claim 6, Nagata does not expressly teach: wherein x1 ranges from 0.02 to 0.2. However, this would have been obvious to one of ordinary skill in the art to optimize the amount of In in the well layer 151 to optimize the superlattice structure. Regarding claim 8, Nagata does not expressly teach: Where x2 ranges from 0.15 to 0.35. However, this would have been obvious to one of ordinary skill in the art to optimize the amount of In in the second well layer 161 to optimize the performance of the light-emitting layer. Regarding claim 19, wherein an energy bandgap of the stress relief layer and the active layer is adjustable by changing material species, dopant concentrations or thickness of the stress relief layer and the active layer (¶ 0043, where one can change the thickness of the active layer by the number of layers used; ¶ 0041, where one can change the thickness of stress relief layer by adding more sub-layers. Based upon this, it would have been obvious to one of ordinary skill in the art that the bandgap would change based upon the number of layers used in the formation of said layers). Claim(s) 17 is/are rejected under 35 U.S.C. 103 as obvious over Nagata, in view of Pan et al. (US 2012/0273814 A1) (“Pan”). Regarding claim 17, Nagata does not teach: further comprising a current blocking layer disposed between said second type semiconductor layer and said current spreading layer. Pan teaches at least in figure 1: further comprising a current blocking layer (201) disposed between said second type semiconductor layer (104) and said current spreading layer (200). It would have been obvious to one of ordinary skill in the art to add the current blocking layer of Pan to the device of Nagata because Pan teaches it may “suppress or reduce the carrier transport and their combination light emission in the active layer underneath the metal electrodes.” ¶ 0028 Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT WALL whose telephone number is (571)272-9567. The examiner can normally be reached Monday to Thursday at 7:30am to 2:30pm PST. Interviews can be scheduled on Tuesday thru Thursday at 10am PST or 2pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VINCENT WALL/Primary Examiner, Art Unit 2898
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Prosecution Timeline

Dec 20, 2023
Application Filed
Jan 28, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
62%
Grant Probability
87%
With Interview (+25.4%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 793 resolved cases by this examiner. Grant probability derived from career allow rate.

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