Prosecution Insights
Last updated: October 04, 2026
Application No. 18/390,639

LIGHT-EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME

Non-Final OA §DP
Filed
Dec 20, 2023
Priority
Mar 27, 2020 — CN 202010228719.6 +1 more
Examiner
WALL, VINCENT
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Anhui San'an Optoelectronics Co., Ltd.
OA Round
3 (Non-Final)
62%
Grant Probability
Moderate
3-4
OA Rounds
0m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allowance Rate
517 granted / 827 resolved
-5.5% vs TC avg
Strong +24% interview lift
Without
With
+24.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
47 currently pending
Career history
874
Total Applications
across all art units

Statute-Specific Performance

§101
2.5%
-37.5% vs TC avg
§103
52.8%
+12.8% vs TC avg
§102
16.3%
-23.7% vs TC avg
§112
24.7%
-15.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 827 resolved cases

Office Action

§DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. At least one of claims 1 and 18 are rejected on the ground of nonstatutory double patenting as being unpatentable over at least one of claims 1-2, 5-6, 8 and 19 of U.S. Patent No. 11,862,753. Although the claims at issue are not identical, they are not patentably distinct from each other because an infringement of the claims of the current application will lead to an infringement of the claims of the U.S. Patent, and vice versa. Current Application ‘753 Patent (Parent Application) A light-emitting diode, comprising: a first type semiconductor layer having an upper surface; a stress relief layer that is disposed on said upper surface of said first type semiconductor layer and that includes at least one first repeating unit containing a first well layer and a first barrier layer being alternately stacked; an active layer that is disposed on said stress relief layer opposite to said first type semiconductor layer and that includes at least one second repeating unit containing a second well layer and a second barrier layer being alternately stacked; a second type semiconductor layer disposed on said active layer opposite to said stress relief layer; a first electrode electrically connected to said first type semiconductor layer; and a second electrode electrically connected to said second type semiconductor layer, wherein said first well layer is made of a material including In, said second well layer is made of a material including In, said first well layer has an In content that is smaller than an In content of said second well layer, said second barrier layer is made of a group III nitride-based compound semiconductor, and a mole fraction of Al based on a total mole fraction of all group III elements in the group III nitride-based compound semiconductor ranges from 15% to 35%, and said stress relief layer has an average energy bandgap that is smaller than an average energy bandgap of said active layer. A light-emitting diode, comprising: a first type semiconductor layer having an upper surface; a stress relief layer that is disposed on said upper surface of said first type semiconductor layer and that includes at least one first repeating unit containing a first well layer and a first barrier layer being alternately stacked; an active layer that is disposed on said stress relief layer opposite to said first type semiconductor layer and that includes at least one second repeating unit containing a second well layer and a second barrier layer being alternately stacked; a second type semiconductor layer disposed on said active layer opposite to said stress relief layer; a first electrode electrically connected to said first type semiconductor layer; and a second electrode electrically connected to said second type semiconductor layer, wherein, said first well layer is made of a material including In; said second well layer is made of a material including In; (The ‘753 patent allows for the first well layer or second well layer to have different or the same In content) (See also claim 5) said second barrier layer is formed with multiple sub-layers, each of said sub-layers being made of a material including Al. (This is taught in claims 6 and 8, where the mol fraction can be determined from the ratios of Al in the claimed stoichiometric ratios). (claim 2) Claim 1 of the current Application would have been obvious based upon claims 2, 5-6 and 8 of the ‘753 patent. In addition, the comprising language of claim 1 of the prior art allows for other elements such as the elements contained within its dependent claims, and nothing is explicitly excluded from the claims. Potentially Allowable Subject Matter Claims 1-3, and 5-20 are potentially allowed. The following is an examiner’s statement of reasons for allowance: The prior art does not teach the first well and second well have different levels of In content, nor does the prior art teach the mole content of the second barrier layer. While the prior art does teach that one can adjust the In levels in the wells, it is not teach that one wants to make the first well and second well have different In levels. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT WALL whose telephone number is (571)272-9567. The examiner can normally be reached Monday to Thursday at 7:30am to 2:30pm PST. Interviews can be scheduled on Tuesday thru Thursday at 10am PST or 2pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VINCENT WALL/Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Dec 20, 2023
Application Filed
Feb 06, 2026
Non-Final Rejection mailed — §DP
Apr 27, 2026
Response Filed
Jun 11, 2026
Final Rejection mailed — §DP
Sep 09, 2026
Request for Continued Examination
Sep 15, 2026
Response after Non-Final Action
Sep 23, 2026
Non-Final Rejection mailed — §DP (current)

Precedent Cases

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Patent 12745427
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
62%
Grant Probability
87%
With Interview (+24.4%)
2y 9m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 827 resolved cases by this examiner. Grant probability derived from career allowance rate.

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