Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 19, and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-11 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (U.S. 2023/0030489 A1, hereinafter refer to Jang) in view of Yamashita et al. (U.S. 2024/0038815 A1, hereinafter refer to Yamashita) and HA et al. (U.S. 2021/0143191 A1, hereinafter refer to HA).
Regarding Claim 1: Jang discloses an image sensor (see Jang, Figs.3 and 6 as shown below and ¶ [0002]) comprising:
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a first structure and a second structure, each having at least one pixel and sequentially stacked in a vertical direction (see Jang, Fig.6 as shown above),
each of the pixels (see Jang, Figs.3 and 6 as shown above) comprising
a photodiode portion (PD) in the first structure (see Jang, Fig.6 as shown above); and
a pixel circuit portion (RX, SF, DX, and SX) connected to the photodiode portion (PD) in the first structure (360) (see Jang, Figs.3 and 6 as shown above),
the photodiode portion (PD) (see Jang, Figs.3 and 6 as shown above) comprising
a photoelectric conversion region (note: the Jang’s PD region is equivalent to the claimed limitation of regions “photodiode portion” and “photoelectric conversion region” because it refers to exactly identical structure) in a first substrate (310) of the first structure (see Jang, Fig.6 as shown above and ¶ [0035]);
a floating diffusion region (FD) spaced apart from the photoelectric conversion region (PD) (see Jang, Fig.6 as shown above);
a gate (TG) including a transfer channel between the photoelectric conversion region (PD) and the floating diffusion region (FD) (see Jang, Fig.6 as shown above); and
a device isolation layer (360) surrounding the photoelectric conversion region (PD) (see Jang, Fig.6 as shown above) (see Jang, Fig.6 as shown above).
Jang is silent upon explicitly disclosing wherein the device isolation layer comprising a first isolation layer, surrounding the photoelectric conversion region, and a second isolation layer, having a smaller depth than the first isolation layer and adjacent to only a side of the floating diffusion region, when viewed in plan view.
Before effective filing date of the claimed invention the disclosed device isolation layer were known to comprise a first isolation layer, surrounding the photoelectric conversion region, and a second isolation layer, having a smaller depth than the first isolation layer and adjacent to only a side of the floating diffusion region, when viewed in plan view in order to electrically and optically isolates the pixels adjacent to each other in a two-dimensional plane.
For support see Yamashita, which teaches wherein the device isolation layer (110) comprising a first isolation layer (110a2), surrounding the photoelectric conversion region (PD), and a second isolation layer (110a1), having a smaller depth than the first isolation layer (110a2) and adjacent to only a side of the floating diffusion region (FD), when viewed in plan view (see Yamashita, Figs.51 and 53 as shown below and ¶ [0532]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Jang and Yamashita to enable the Jang device isolation layer to comprise a first isolation layer, surrounding the photoelectric conversion region, and a second isolation layer, having a smaller depth than the first isolation layer and adjacent to only a side of the floating diffusion region, when viewed in plan view as taught by Yamashita in order to isolate each unit pixel in the pixel region in order to electrically and optically isolates the pixels adjacent to each other in a two-dimensional plane.
The combination of Jang and Yamashita is silent upon explicitly disclosing wherein the first isolation layer and the second isolation layer including different materials.
For support see HA, which teaches wherein the first isolation layer (212) and the second isolation layer (211/215) including different materials (see HA, Fig.2, ¶ [0054]- ¶ [0056]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Jang, Yamashita, and HA to enable the combination of Jang’s and Yamashita’s first isolation layer and second isolation layer to be include different materials as taught by HA in order to electrically separate the conductive connection pattern from the conductive isolation pattern.
Regarding Claim 2: Jang as modified teaches an image sensor as set forth in claim 1 as above. The combination of Jang and Yamashita further teaches wherein the first substrate (102) has a first surface and a second surface opposing the first surface, the first isolation layer (110a2) is a deep trench isolation layer penetrating through the first surface and the second surface, and the second isolation layer (110a1) is a shallow trench isolation layer depressed by a depth from the first surface (see Yamashita, Figs.51 and 53 as shown above).
Regarding Claim 3: Jang as modified teaches an image sensor as set forth in claim 2 as above. The combination of Jang and Yamashita further teaches a ground voltage or a negative voltage is applied to the first isolation layer (110a2) (see Yamashita, Figs.51 and 53 as shown above).
Note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Regarding Claim 4: Jang as modified teaches an image sensor as set forth in claim 2 as above. The combination of Jang and Yamashita further teaches the first isolation layer (110a2) and the second isolation layer (110a1) are stacked in the vertical direction in a region adjacent to the floating diffusion region (FD), and only the first isolation layer (110a2) is in a region other than the region adjacent to the floating diffusion region (FD) (see Yamashita, Figs.51 and 53 as shown above).
Regarding Claim 5: Jang as modified teaches an image sensor as set forth in claim 1 as above. The combination of Jang and Yamashita further teaches wherein each of the pixels comprises a plurality of transistors (see Jang, Figs.3 and 6 as shown above), and
the photodiode portion comprises a portion of the plurality of transistors, and the pixel circuit portion comprises a remaining portion of the plurality of transistors (see Jang, Figs.3 and 6 as shown above).
Regarding Claim 6: Jang as modified teaches an image sensor as set forth in claim 5 as above. The combination of Jang and Yamashita further teaches wherein the photodiode portion comprises a transfer transistor (TG), and the gate is a transfer gate (see Jang, Figs.3 and 6 as shown above).
Regarding Claim 7: Jang as modified teaches an image sensor as set forth in claim 6 as above. The combination of Jang and Yamashita further teaches wherein the transfer gate (TG) is a vertical transfer gate formed in a recess extending inwardly of the first substrate (310) from a first surface of the first substrate (310) (see Jang, Figs.3 and 6 as shown above).
Regarding Claim 8: Jang as modified teaches an image sensor as set forth in claim 6 as above. The combination of Jang and Yamashita further teaches wherein the gate (TR) is a planar transfer gate on a first surface of the substrate with a gate insulating layer interposed therebetween (see Yamashita, Figs.51 and 53 as shown above).
Regarding Claim 9: Jang as modified teaches an image sensor as set forth in claim 6 as above. The combination of Jang and Yamashita further teaches wherein the pixel circuit portion comprises at least one of a reset transistor, a source follower transistor, a select transistor, or a dual conversion gain transistor (see Jang, Figs.3 and 6 as shown above).
Regarding Claim 10: Jang as modified teaches an image sensor as set forth in claim 1 as above. The combination of Jang and Yamashita further teaches wherein a bonding portion (610) connecting the first structure and the second structure to each other (see Jang, Fig.6 as shown above and Fig.12C).
Regarding Claim 11: Jang as modified teaches an image sensor as set forth in claim 10 as above. The combination of Jang and Yamashita further teaches wherein the bonding portion (610) comprises copper-copper bonding (see Jang, Fig.6 as shown above, Fig.12C, and ¶ [0068]).
Regarding Claim 14: Jang as modified teaches an image sensor as set forth in claim 5 as above. The combination of Jang and Yamashita further teaches wherein a third structure stacked to oppose the first structure with the second structure interposed therebetween (see Jang, Fig.6 as shown above).
Regarding Claim 15: Jang as modified teaches an image sensor as set forth in claim 14 as above. The combination of Jang and Yamashita further teaches wherein the third structure comprises a logic circuit (130) connected to the first structure and the second structure to drive transistors of each of the pixels (see Jang, Fig.6 as shown above and ¶ [0084]).
Regarding Claim 16: Jang as modified teaches an image sensor as set forth in claim 15 as above. The combination of Jang and Yamashita further teaches wherein at least a portion of the remaining transistors, other than a transfer transistor, is provided in the third structure (see Jang, Fig.6 as shown above).
Regarding Claim 17: Jang as modified teaches an image sensor as set forth in claim 14 as above. The combination of Jang and Yamashita further teaches wherein the second structure comprises a second substate (210), a conductive pattern provided on the second substrate (210), and a through-via (510 or 520) penetrating through the second substrate (210), and the first structure and the third structure are connected to each other through the through-via (510 or 520) (see Jang, Fig.6 as shown above and Fig.9).
Regarding Claim 18: Jang as modified teaches an image sensor as set forth in claim 1 as above. The combination of Jang and Yamashita further teaches wherein a ground region provided between the gate (TG) and the device isolation layer (360) (see Jang, Fig.6 as shown above and ¶ [0035]),
wherein the ground region (310) includes impurities of a first conductivity type, and the photoelectric conversion region and the floating diffusion region include impurities of a second conductivity type opposite to the first conductivity type (see Jang, Fig.6 as shown above and ¶ [0035]).
Regarding Claim 19: Jang discloses an image sensor (see Jang, Figs.3 and 6 as shown above and ¶ [0002]) comprising:
a photoelectric conversion region (PD) in a first substrate (310) having a first surface and a second surface (see Jang, Fig.6 as shown above);
a floating diffusion region (FD) in the first substrate (310) to be spaced apart from the photoelectric conversion region (PD) (see Jang, Fig.6 as shown above);
a gate of a transfer transistor (TG) on a side of the first surface of the first substrate (310) as a transfer channel between the photoelectric conversion region (PD) and the floating diffusion region (FD) (see Jang, Fig.6 as shown above); and
a device isolation layer (360) surrounding the photoelectric conversion region (FD) (see Jang, Fig.6 as shown above).
Jang is silent upon explicitly disclosing wherein the device isolation layer comprising a first isolation layer, surrounding the photoelectric conversion region, and a second isolation layer, having a smaller depth than the first isolation layer and adjacent to only a side of the floating diffusion region, when viewed in plan view.
Before effective filing date of the claimed invention the disclosed device isolation layer were known to comprise a first isolation layer, surrounding the photoelectric conversion region, and a second isolation layer, having a smaller depth than the first isolation layer and adjacent to only a side of the floating diffusion region, when viewed in plan view in order to electrically and optically isolates the pixels adjacent to each other in a two-dimensional plane.
For support see Yamashita, which teaches wherein the device isolation layer (110) comprising a first isolation layer (110a2), surrounding the photoelectric conversion region (PD), and a second isolation layer (110a1), having a smaller depth than the first isolation layer (110a2) and adjacent to only a side of the floating diffusion region (fd), when viewed in plan view (see Yamashita, Figs.51 and 53 as shown above and ¶ [0532]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Jang and Yamashita to enable the Jang device isolation layer to comprise a first isolation layer, surrounding the photoelectric conversion region, and a second isolation layer, having a smaller depth than the first isolation layer and adjacent to only a side of the floating diffusion region, when viewed in plan view as taught by Yamashita in order to electrically and optically isolates the pixels adjacent to each other in a two-dimensional plane.
The combination of Jang and Yamashita is silent upon explicitly disclosing wherein the first isolation layer and the second isolation layer including different materials.
For support see HA, which teaches wherein the first isolation layer (212) and the second isolation layer (211/215) including different materials (see HA, Fig.2, ¶ [0054]- ¶ [0056]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Jang, Yamashita, and HA to enable the combination of Jang’s and Yamashita’s first isolation layer and second isolation layer to be include different materials as taught by HA in order to electrically separate the conductive connection pattern from the conductive isolation pattern.
Regarding Claim 20: Jang discloses an image sensor (see Jang, Figs.3 and 6 as shown above and ¶ [0002]) comprising:
a pixel comprising a plurality of transistors (see Jang, Figs.3 and 6 as shown above),
a first structure, a second structure, and a third structure sequentially stacked in vertical direction, the first structure comprising a transfer transistor (TG) among the plurality of transistors, the second structure comprising remaining transistors other than the transfer transistor, and the third structure a logic circuit (130) (see Jang, Figs.3 and 6 as shown above), the first structure comprising
a device isolation layer (360) surrounding an active region in a first substrate (310) having a first surface and a second surface (see Jang, Figs.3 and 6 as shown above);
a photoelectric conversion region (PD) in the active region (see Jang, Figs.3 and 6 as shown above);
a floating diffusion region (FD) in the active region and spaced apart from the photoelectric conversion region (PD) (see Jang, Figs.3 and 6 as shown above); and
a gate of the transfer transistor (TG) in the active region on a side of the first surface of the first substrate (310) as a transfer channel between the photoelectric conversion region (PD) and the floating diffusion region (FD) (see Jang, Figs.3 and 6 as shown above).
Jang is silent upon explicitly disclosing wherein the device isolation layer comprising a first isolation layer, surrounding the photoelectric conversion region, and a second isolation layer, having a smaller depth than the first isolation layer, when viewed in plan view, the first isolation layer and the second isolation layer stacked in a vertical direction in a first region adjacent to the floating diffusion region, and the second isolation layer is in the vertical direction in a region other than the first region.
Before effective filing date of the claimed invention the disclosed device isolation layer were known to comprise a first isolation layer, surrounding the photoelectric conversion region, and a second isolation layer, having a smaller depth than the first isolation layer, when viewed in plan view, the first isolation layer and the second isolation layer stacked in a vertical direction in a first region adjacent to the floating diffusion region, and the second isolation layer is in the vertical direction in a region other than the first region in order to electrically and optically isolates the pixels adjacent to each other in a two-dimensional plane.
For support see Yamashita, which teaches wherein the device isolation layer (110) comprising a first isolation layer (110a2), surrounding the photoelectric conversion region (PD), and a second isolation layer (110a1), having a smaller depth than the first isolation layer (110a2), when viewed in plan view, the first isolation layer (110a2) and the second isolation layer (110a1) stacked in a vertical direction in a first region adjacent to the floating diffusion region (FD), and the second isolation layer (110a1) is in the vertical direction in a region other than the first region (see Yamashita, Figs.51 and 53 as shown above and ¶ [0532]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Jang and Yamashita to enable the Jang device isolation layer to comprise a first isolation layer, surrounding the photoelectric conversion region, and a second isolation layer, having a smaller depth than the first isolation layer and adjacent to only a side of the floating diffusion region, when viewed in plan view as taught by Yamashita in order to electrically and optically isolates the pixels adjacent to each other in a two-dimensional plane.
The combination of Jang and Yamashita is silent upon explicitly disclosing wherein the first isolation layer and the second isolation layer including different materials.
For support see HA, which teaches wherein the first isolation layer (212) and the second isolation layer (211/215) including different materials (see HA, Fig.2, ¶ [0054]- ¶ [0056]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Jang, Yamashita, and HA to enable the combination of Jang’s and Yamashita’s first isolation layer and second isolation layer to be include different materials as taught by HA in order to electrically separate the conductive connection pattern from the conductive isolation pattern.
Claim(s) 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (U.S. 2023/0030489 A1, hereinafter refer to Jang), Yamashita et al. (U.S. 2024/0038815 A1, hereinafter refer to Yamashita), and HA et al. (U.S. 2021/0143191 A1, hereinafter refer to HA) as applied to claim 1 above, and further in view of JIN et al. (U.S. 2022/0406825 A1, hereinafter refer to JIN).
Regarding Claim 12: Jang as modified teaches an image sensor as applied to claim 1 above. The combination of Jang and Yamashita is silent upon explicitly disclosing wherein each of the pixels comprises a first pixel and a second pixel adjacent to each other, and
the floating diffusion region is shared by the first pixel and the second pixel.
Before effective filing date of the claimed invention the disclosed each of the pixels comprises a first pixel and a second pixel adjacent to each other, and the floating diffusion region is shared by the first pixel and the second pixel in order to obtain an image sensor with increased integration.
For support see JIN, which teaches wherein each of the pixels comprises a first pixel and a second pixel adjacent to each other (see JIN, Figs. 2B and 7 as shown below and ¶ [0002]), and
the floating diffusion region (CFD) is shared by the first pixel and the second pixel (see JIN, Figs. 2B and 7 as shown below and ¶ [0002]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Jang, Yamashita, and JIN to enable each of the pixels of the combination of Jang’s and Yamashita’s to comprises a first pixel and a second pixel adjacent to each other, and the floating diffusion region to be shared by the first pixel and the second pixel as taught by JIN in order to obtain an image sensor with increased integration.
Regarding Claim 13: Jang as modified teaches an image sensor as set forth in claim 12 as above. The combination of Jang, Yamashita, HA, and JIN further teaches wherein the first pixel and the second pixel are symmetrically provided with the first isolation layer (PIS), between the first pixel and the second pixel, interposed therebetween (see JIN, Fig.6 as shown above).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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