Prosecution Insights
Last updated: April 19, 2026
Application No. 18/390,772

PACKAGE WITH LOW-WARPAGE CARRIER

Non-Final OA §103
Filed
Dec 20, 2023
Examiner
BOWEN, ADAM S
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Infineon Technologies AG
OA Round
1 (Non-Final)
96%
Grant Probability
Favorable
1-2
OA Rounds
1y 11m
To Grant
99%
With Interview

Examiner Intelligence

Grants 96% — above average
96%
Career Allow Rate
678 granted / 704 resolved
+28.3% vs TC avg
Minimal +2% lift
Without
With
+2.5%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
22 currently pending
Career history
726
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
45.1%
+5.1% vs TC avg
§102
36.1%
-3.9% vs TC avg
§112
5.8%
-34.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 704 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 12/20/2023 was filed before the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Leitgeb et al. (2023/0298987) in view of the following reasons. Re claim 15, Leitgeb teaches a package (Fig. 1), comprising: a carrier (100) comprising a first component mounting region (“left side”) and a second component mounting region (“right side”) with a slot in between (Fig. 1); at least one first electronic component (112) mounted on the first component mounting region (“left side”); and at least one second electronic component (114) mounted on the second component mounting region (“right side”); Leitgeb further teaches a carrier with low warpage [80], yet remains explicitly silent to wherein warpage of the carrier in a mounting plane is less than 50 µm. However, Applicant has not shown wherein warpage of the carrier in a mounting plane is less than 50 µm has a specific, disclosed criticality that is unexpected and would not have been determined through routine experimentation of one having ordinary skill in the art. Therefore, it would have been obvious to adjust the warpage of the carrier so as to customize, optimize, or otherwise meet customer space and design requirements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Re claim 16, Leitgeb teaches the package according to claim 15, comprising at least one of the following features: wherein the warpage of the carrier in the mounting plane is less than 15 µm, in particular less than 10 µm; wherein the carrier comprises a leadframe structure; wherein the carrier comprises a plurality of lead structures, in particular electrically coupled with at least one of the at least one first electronic component, the at least one second electronic component, the first component mounting region and the second component mounting region. Leitgeb does not explicitly teach wherein the warpage of the carrier in the mounting plane is less than 15 µm, in particular less than 10 µm. However, Applicant has not shown wherein the warpage of the carrier in the mounting plane is less than 15 µm, in particular less than 10 µm has a specific, disclosed criticality that is unexpected and would not have been determined through routine experimentation of one having ordinary skill in the art. Therefore, it would have been obvious to adjust the warpage of the carrier so as to customize, optimize, or otherwise meet customer space and design requirements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Re claim 17, Leitgeb teaches the package according to claim 15, wherein at least part of a surface of the carrier is covered with a plating structure, in particular at least one of the group consisting of nickel, silver, and NiNiP [32, 66, 83]. Re claim 18, Leitgeb teaches the package according to claim 15. Leitgeb does not explicitly teach wherein a thickness of at least one of the first component mounting region and the second component mounting region is in a range from 0.2 mm to 1.5 mm. However, Applicant has not shown wherein a thickness of at least one of the first component mounting region and the second component mounting region is in a range from 0.2 mm to 1.5 mm has a specific, disclosed criticality that is unexpected and would not have been determined through routine experimentation of one having ordinary skill in the art. Therefore, it would have been obvious to adjust the thickness of at least one of the first component mounting region and the second component mounting region so as to customize, optimize, or otherwise meet customer space and design requirements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Re claim 19, Leitgeb teaches the package according to claim 15, comprising a connection structure (102) in form of an intermetallic compound [60], in particular at least one of the group of AuSnCu, AuSnNi, AuSnAg, NiSn and CuSn, connecting the carrier with at least one of the at least one first electronic component and the at least one second electronic component [60]. Re claim 20, Leitgeb teaches the package according to claim 19. Leitgeb does not explicitly teach wherein the connection structure has a thickness in a range from 1 µm to 10 µm. However, Applicant has not shown wherein the connection structure has a thickness in a range from 1 µm to 10 µm has a specific, disclosed criticality that is unexpected and would not have been determined through routine experimentation of one having ordinary skill in the art. Therefore, it would have been obvious to adjust the thickness of connection structure so as to customize, optimize, or otherwise meet customer space and design requirements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Prior art of record Re claim 1, Waidhas et al. (2022/0199562) teaches a method of manufacturing a package (Figs. 4A-D), wherein the method comprises: providing a carrier (450) with at least one component mounting region (“left side”) for mounting at least one electronic component (425A); providing the at least one electronic component (425A), wherein the at least one electronic component (425A) comprises at least one first electrode (423) on a first surface (Fig. 4D) and at least one second electrode (424) on a second surface (Fig. 4D), wherein the second surface is opposite to the first surface (“opposite sides of component 425A, Fig. 4D”); mounting the at least one electronic component (425A) with the second surface on the at least one component mounting region by a solder structure [47]. Waidhas does not explicitly teach wherein the carrier is pre-warped in accordance with an initial curvature direction; and applying ambient conditions to the carrier and to the at least one electronic component during mounting so that the carrier is re-warped to thereby at least partially reduce warpage of the carrier in a mounting plane. Allowable Subject Matter The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not anticipate or make obvious the method of claim 1, including each of the limitations and specifically wherein the carrier is pre-warped in accordance with an initial curvature direction; and applying ambient conditions to the carrier and to the at least one electronic component during mounting so that the carrier is re-warped to thereby at least partially reduce warpage of the carrier in a mounting plane, for the same reasons as mentioned for claim 1 in the prior art of record above. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Gupta et al. (2023/0066652), Figs. 1-9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897 /ADAM S BOWEN/Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Dec 20, 2023
Application Filed
Mar 06, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
96%
Grant Probability
99%
With Interview (+2.5%)
1y 11m
Median Time to Grant
Low
PTA Risk
Based on 704 resolved cases by this examiner. Grant probability derived from career allow rate.

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