DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Office acknowledges receipt on 31 July 2026 of Applicants’ amendments in which claims 1, 4, 10, 13, and 20 are amended. The Office withdraws the drawing objections and section 112(b) rejections identified in the Office Communication dated 6 May 2026 in view of the amendments.
Response to Arguments
Applicants’ arguments with respect to claim(s) 1, 4, 10, 13, and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 8-10, 12-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US20170236747A1) in view of Wang et al. (US20190164823A1).
Regarding claim 1, as interpreted in view of the indefiniteness rejection, Chen teaches in Fig. 10 a semiconductor device comprising:
an active pattern (110) extending in a first direction (horizontal) {[0015]};
a gate structure (M, 132, 142, 5) comprising a gate electrode (14 and/or 16) extending in a second direction (vertical) and a gate spacer (132 and/or 142) on the active pattern (110), wherein the gate electrode (14 and/or 16) and the gate spacer (132 and/or 142) are spaced apart from each other in the first direction (horizontal) {[0016, 0018]};
a source/drain pattern (144) on the active pattern (110) {[0016]};
a contact barrier layer (164) on the source/drain pattern (144) {[0027]}; and
a contact filling layer (180’) on the contact barrier layer (164) {[0029]},
wherein an uppermost point of the contact barrier layer (164) is between an upper surface of the contact filling layer (180’) and a lower surface of the contact filling layer (180’) {Fig. 10}.
Chen does not teach a first outer wall of the contact barrier layer and a first outer wall of the contact filling layer extend along a first common plane, and a second outer wall of the contact barrier layer and a second outer wall of the contact filling layer extend along a second common plane, and wherein the gate structure further comprises a gate capping layer that is on and in contact with the gate electrode, and the contact filling layer contacts the gate capping layer.
In an analogous art, Wang teaches in Fig. 11 and paragraphs [0016, 0026, 0040] a first outer wall (left wall) of a contact barrier layer (50, 52) and a first outer wall (left wall) of a contact filling layer (70/72) extend along a first common plane, and a second outer wall (right wall) of the contact barrier layer (50, 52) and a second outer wall (right wall) of the contact filling layer (70/72) extend along a second common plane, and wherein a gate structure (32, 34, 40) further comprises a gate capping layer (40) that is on and in contact with a gate electrode (32), and the contact filling layer (70/72) contacts the gate capping layer (40). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s semiconductor device based on the teachings of Wang, to achieve the above-identified subject matter, so that conductive material that will form a conductive feature can be more easily deposited in the opening or recess without a void being formed in the opening or recess[, … which] can cause higher resistance of the conductive features or complete failure of the conductive feature, such as by failing to establish electrical contact. Wang [0064]. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Wang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Still further, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. MPEP §2143((I)(E).
Regarding claim 2, Chen as modified by Wang teaches the semiconductor device of claim 1, and Chen further teaches wherein the contact filling layer (180’) comprises:
a first portion (portion surrounded by 164) having a first width along the first direction (horizontal), wherein the first portion (portion surrounded by 164) is surrounded by the contact barrier layer (164) {Fig. 10}; and
a second portion (portion above 164) on the first portion (portion surrounded by 164), not overlapping the contact barrier layer (164) in the first direction (horizontal), and having a second width along the first direction (horizontal) greater than the first width {Fig. 10}.
Regarding claim 3, Chen as modified by Wang teaches the semiconductor device of claim 1, and Chen further teaches further comprising a silicide layer (20) between the source/drain pattern (144) and the contact barrier layer (164), wherein the contact filling layer (180’) does not contact the silicide layer (20) {[0023]}.
Regarding claim 4, Chen as modified by Wang teaches the semiconductor device of claim 1, but Chen does not teach wherein the upper surface of the contact filling layer and an uppermost surface of the gate capping layer extend along a third common plane.
Wang teaches in Fig. 11 and paragraphs [0026, 0040] an upper surface of a contact filling layer (70/72) and an uppermost surface of a gate capping layer (40) extend along a third common plane. The motivation for this modification is identified above with respect to base claim 1.
Regarding claim 5, Chen as modified by Wang teaches the semiconductor device of claim 1, and Chen further teaches wherein the contact barrier layer (164) comprises titanium nitride, and the contact filling layer (180’) comprises tungsten {[0022, 0029]}.
Regarding claim 6, Chen as modified by Wang teaches the semiconductor device of claim 1, and Chen further teaches wherein the uppermost point of the contact barrier layer (164) is between an upper surface of the gate electrode (14 and/or 16) and the lower surface of the contact filling layer (180’) {Fig. 10}.
Regarding claim 8, Chen as modified by Wang teaches the semiconductor device of claim 1, and Chen further teaches wherein the contact barrier layer does not comprise silicon (Si) and boron (B) {[0022]}.
Regarding claim 9, Chen as modified by Wang teaches the semiconductor device of claim 1, and Chen further teaches wherein the upper surface of the gate electrode (14 and/or 16) is flat {Fig. 10}.
Regarding claim 10, Chen as modified by Wang teaches the semiconductor device of claim 1, but Chen does not teach wherein a first outer wall of the gate capping layer extends, from an upper surface of the gate capping layer, along the first common plane, in contact with the contact filling layer.
Wang teaches in Fig. 11 and paragraphs [0026, 0040] a first outer wall (left wall) of a gate capping layer (40) extends, from an upper surface of the gate capping layer (40), along a first common plane, in contact with a contact filling layer (70/72). The motivation for this modification is identified above with respect to base claim 1.
Regarding claim 12, Chen as modified by Wang teaches the semiconductor device of claim 1, and Chen further teaches wherein the contact barrier layer (164) entirely surrounds the lower surface of the contact filling layer (180’) {Fig. 10}.
Regarding claim 13, as interpreted in view of the indefiniteness rejection, Chen teaches a semiconductor device comprising:
an active pattern (110) extending in a first direction (horizontal) {[0015]};
a gate structure (M, 132, 142, 5) comprising a gate electrode (14 and/or 16) extending in a second direction (vertical) and a gate spacer (132 and/or 142) on the active pattern (110), wherein the gate electrode (14 and/or 16) and the gate spacer (132 and/or 142) are spaced apart from each other in the first direction (horizontal) {[0016, 0018]};
a source/drain pattern (144) on the active pattern (110) {[0016]};
a contact barrier layer (164) on the source/drain pattern (144) {[0027]}; and
a contact filling layer (180’) on the contact barrier layer (164) {[0029]},
wherein the contact filling layer (180’) comprises a first portion (portion surrounded by 164) surrounded by the contact barrier layer (164) and a second portion (portion above 164) on the first portion (portion surrounded by 164) that does not overlap the contact barrier layer (164) in the first direction (horizontal) {Fig. 10},
wherein a first width along the first direction (horizontal) of the first portion (portion surrounded by 164) is smaller than a second width along the first direction (horizontal) of the second portion (portion above 164) {Fig. 10}.
Chen does not teach a first outer wall of the contact barrier layer and a first outer wall of the second portion of the contact filling layer extend along a first common plane, and a second outer wall of the contact barrier layer and a second outer wall of the second portion of the contact filling layer extend along a second common plane, and wherein the gate structure further comprises a gate capping layer on and in contact with the gate electrode, and the contact filling layer contacts the gate capping layer.
Wang teaches in Fig. 11 and paragraphs [0016, 0026, 0040] a first outer wall (left wall) of a contact barrier layer (50, 52) and a first outer wall (left wall) of a second portion of a contact filling layer (70/72) extend along a first common plane, and a second outer wall (right wall) of the contact barrier layer (50, 52) and a second outer wall (right wall) of the second portion of the contact filling layer (70/72) extend along a second common plane, and wherein a gate structure (32, 34, 40) further comprises a gate capping layer (40) on and in contact with a gate electrode (32), and the contact filling layer (70/72) contacts the gate capping layer (40). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s semiconductor device based on the teachings of Wang, to achieve the above-identified subject matter, so that conductive material that will form a conductive feature can be more easily deposited in the opening or recess without a void being formed in the opening or recess[, … which] can cause higher resistance of the conductive features or complete failure of the conductive feature, such as by failing to establish electrical contact. Wang [0064]. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Wang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Still further, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. MPEP §2143((I)(E).
Regarding claim 14, Chen as modified by Wang teaches the semiconductor device of claim 13, and Chen further teaches wherein an uppermost point of the contact barrier layer (164) is between an upper surface of the gate electrode (14 and/or 16) and a lower surface of the contact filling layer (180’) {Fig. 10}.
Regarding claim 15, Chen as modified by Wang teaches the semiconductor device of claim 13, and Chen further teaches wherein the contact barrier layer (164) comprises titanium nitride, and the contact filling layer (180’) comprises tungsten {[0022, 0029]}.
Regarding claim 16, Chen as modified by Wang teaches the semiconductor device of claim 13, and Chen further teaches further comprising a silicide layer (20) between the source/drain pattern (144) and the contact barrier layer (164) {[0023]}.
Regarding claim 17, Chen as modified by Wang teaches the semiconductor device of claim 16, and Chen further teaches wherein a lower surface of the silicide layer (20) is between an upper surface of the source/drain pattern (144) and a lower surface of the source/drain pattern (144) {Fig. 10}.
Regarding claim 18, Chen as modified by Wang teaches the semiconductor device of claim 13, and Chen further teaches wherein an upper surface of the contact filling layer (180’) and an uppermost surface of the gate structure (M, 132, 142, 5) extend along a common plane {Fig. 10}.
Regarding claim 20, as interpreted in view of the indefiniteness rejection, Chen teaches in Fig. 10 a semiconductor device comprising:
an active pattern (110) extending in a first direction (horizontal) {[0015]};
a gate structure (M, 132, 142, 5) comprising a gate electrode (14 and/or 16) extending in a second direction (vertical) and a gate spacer (132 and/or 142) on the active pattern (110), wherein the gate electrode (14 and/or 16) and the gate spacer (132 and/or 142) are spaced apart from each other in the first direction (horizontal) {[0016, 0018]};
a source/drain pattern (144) on the active pattern (110 {[0016]});
a silicide layer (20) on the source/drain pattern (144) {[0023]};
a contact barrier layer (164) on the silicide layer (20) {[0027]}; and
a contact filling layer (180’) on the contact barrier layer (164) {[0029]},
wherein the contact filling layer (180’) comprises a first portion (portion surrounded by 164) surrounded by the contact barrier layer (164) and a second portion (portion above 164) on the first portion (portion surrounded by 164) that does not overlap the contact barrier layer (164) in the first direction (horizontal) {Fig. 10},
wherein a first width of the first portion (portion surrounded by 164) along the first direction (horizontal) is smaller than a second width of the second portion (portion above 164) along the first direction (horizontal) {Fig. 10},
wherein the contact barrier layer (164) comprises titanium nitride and the contact filling layer (180’) comprises tungsten {[0022, 0029]},
wherein an uppermost point of the contact barrier layer (164) is between an upper surface of the gate electrode (14 and/or 16) and a lower surface of the contact filling layer (180’) {Fig. 10}.
Chen does not teach a first outer wall of the contact barrier layer and a first outer wall of the second portion of the contact filling layer extend along a first common plane, and a second outer wall of the contact barrier layer and a second outer wall of the second portion of the contact filling layer extend along a second common plane, wherein the gate structure further comprises a gate capping layer on and in contact with the gate electrode, and the contact filling layer contacts the gate capping layer.
Wang teaches in Fig. 11 and paragraphs [0016, 0026, 0040] a first outer wall (left wall) of a contact barrier layer (50, 52) and a first outer wall (left wall) of a second portion of a contact filling layer (70/72) extend along a first common plane, and a second outer wall (right wall) of the contact barrier layer (50, 52) and a second outer wall (right wall) of the second portion of the contact filling layer (70/72) extend along a second common plane, and wherein a gate structure (32, 34, 40) further comprises a gate capping layer (40) on and in contact with a gate electrode (32), and the contact filling layer (70/72) contacts the gate capping layer (40). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s semiconductor device based on the teachings of Wang, to achieve the above-identified subject matter, so that conductive material that will form a conductive feature can be more easily deposited in the opening or recess without a void being formed in the opening or recess[, … which] can cause higher resistance of the conductive features or complete failure of the conductive feature, such as by failing to establish electrical contact. Wang [0064]. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Wang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Still further, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. MPEP §2143((I)(E).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Wang as applied to claim 10 above, and further in view of Leobandung et al. (US20160035857A1).
Regarding claim 11, Chen as modified by Wang teaches the semiconductor device of claim 10, but Chen does not teach further comprising an etch stop layer on a side surface of the gate spacer on the source/drain pattern, wherein the gate capping layer covers an upper surface of the etch stop layer.
In an analogous art, Leobandung teaches in Fig. 14 and paragraph [0042] an etch stop layer (904) on a side surface of a gate spacer (112) on a source/drain pattern (202), wherein a gate capping layer (902) covers an upper surface of the etch stop layer (904). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s semiconductor device as modified by Wang based on the teachings of Leobandung – to include an etch stop layer on a side surface of the gate spacer on the source/drain pattern, wherein the gate capping layer covers an upper surface of the etch stop layer – so contact trenches … may be formed using a selective etching process. Leobandung [0043]. Moreover, all the claimed elements (e.g., etch stop layer, gate spacer, source/drain pattern, capping layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Leobandung) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Wang as applied to claim 13 above, and further in view of Hwang et al. (US20220069100A1).
Regarding claim 19, Chen as modified by Wang teaches the semiconductor device of claim 13, but Chen does not teach wherein a grain size of the first portion is smaller than a grain size of the second portion.
In an analogous art, Hwang teaches in Fig. 4 and paragraph [0052] a grain size (G2) of a first portion (lower portion) of a contact filling layer (185) is smaller than a grain size (G2’) of a second portion (upper portion; e.g., 189) of the contact filling layer (185). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s semiconductor device as modified by Wang based on the teachings of Hwang – such that a grain size of the first portion is smaller than a grain size of the second portion – to form a grain adjustment region. Hwang [0052]. Moreover, all the claimed elements (e.g., grain size, first and second portions) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Hwang with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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