Prosecution Insights
Last updated: May 29, 2026
Application No. 18/390,782

SEMICONDUCTOR DEVICE

Non-Final OA §103§112
Filed
Dec 20, 2023
Priority
Jun 02, 2023 — RE 10-2023-0071614
Examiner
WARD, DAVID WILLIAM
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
62%
Grant Probability
Moderate
1-2
OA Rounds
1y 2m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allowance Rate
39 granted / 63 resolved
-6.1% vs TC avg
Strong +40% interview lift
Without
With
+39.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
37 currently pending
Career history
128
Total Applications
across all art units

Statute-Specific Performance

§103
93.2%
+53.2% vs TC avg
§102
6.0%
-34.0% vs TC avg
§112
0.8%
-39.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 63 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claim 7 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election of Species A (e.g., Figs. 2-5) was made without traverse in the reply filed on 20 March 2026. The election requirement is deemed proper and made final. The Office reminds Applicants to indicate the withdrawn status of claim 7 in their next submission of a claim listing. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following features must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Claim 1, lines 10 and 11, recites “outer walls of the contact barrier layer and outer walls of the contact filling layer extend along a common plane,” which is not illustrated by the drawings. Instead, the drawings (e.g., Fig. 2) illustrate that a first outer wall (e.g., left-side wall) of each of the contact barrier layer (e.g., 171) and the contact filling layer (e.g., 172) extend along a first common plane (e.g., vertical line) and a second outer wall (e.g., right-side wall) of each of the contact barrier layer (e.g., 171) and the contact filling layer (e.g., 172) extend along a second common plane (e.g., vertical line), in a cross-sectional view. Claim 13, lines 13-15, recites “outer walls of the contact barrier layer and outer walls of the second portion of the contact filling layer extend along a common plane,” which is not illustrated by the drawings. Instead, the drawings (e.g., Fig. 2) illustrate that a first outer wall (e.g., left-side wall) of each of the contact barrier layer (e.g., 171) and the second portion of the contact filling layer (e.g., 172) extend along a first common plane (e.g., vertical line) and a second outer wall (e.g., right-side wall) of each of the contact barrier layer (e.g., 171) and the second portion of the contact filling layer (e.g., 172) extend along a second common plane (e.g., vertical line), in a cross-sectional view. Claim 20, lines 15 and 16, recites “outer walls of the contact barrier layer and outer walls of the second portion of the contact filling layer extend along a common plane,” which is not illustrated by the drawings. Instead, the drawings (e.g., Fig. 2) illustrate that a first outer wall (e.g., left-side wall) of each of the contact barrier layer (e.g., 171) and the second portion of the contact filling layer (e.g., 172) extend along a first common plane (e.g., vertical line) and a second outer wall (e.g., right-side wall) of each of the contact barrier layer (e.g., 171) and the second portion of the contact filling layer (e.g., 172) extend along a second common plane (e.g., vertical line), in a cross-sectional view. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-6 and 8-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1, lines 10 and 11, recites “outer walls of the contact barrier layer and outer walls of the contact filling layer extend along a common plane,” which is indefinite because it is unclear how distinct and multiple walls (e.g., left-side wall and right-side wall within Fig. 2) of the same object (e.g., contact barrier layer/contact filling layer) extend along a common plane (e.g., vertical line). For the purpose of compact prosecution and to better comport with the disclosure of the application, the claim will be interpreted to recite “a first outer wall of each of the contact barrier layer and the contact filling layer extend along a first common plane and a second outer wall of each of the contact barrier layer and the contact filling layer extend along a second common plane, in a cross-sectional view.” Claims 2-6 and 8-12 are rejected due to their dependence from base claim 1. Claim 13, lines 13-15, recites “outer walls of the contact barrier layer and outer walls of the second portion of the contact filling layer extend along a common plane,” which is indefinite because it is unclear how distinct and multiple walls (e.g., left-side wall and right-side wall within Fig. 2) of the same object (e.g., contact barrier layer/second portion of the contact filling layer) extend along a common plane (e.g., vertical line). For the purpose of compact prosecution and to better comport with the disclosure of the application, the claim will be interpreted to recite “a first outer wall of each of the contact barrier layer and the second portion of the contact filling layer extend along a first common plane and a second outer wall of each of the contact barrier layer and the second portion of the contact filling layer extend along a second common plane, in a cross-sectional view.” Claims 14-19 are rejected due to their dependence from base claim 13. Claim 20, lines 15 and 16, recites “outer walls of the contact barrier layer and outer walls of the second portion of the contact filling layer extend along a common plane,” which is indefinite because it is unclear how distinct and multiple walls (e.g., left-side wall and right-side wall within Fig. 2) of the same object (e.g., contact barrier layer/second portion of the contact filling layer) extend along a common plane (e.g., vertical line). For the purpose of compact prosecution and to better comport with the disclosure of the application, the claim will be interpreted to recite “a first outer wall of each of the contact barrier layer and the second portion of the contact filling layer extend along a first common plane and a second outer wall of each of the contact barrier layer and the second portion of the contact filling layer extend along a second common plane, in a cross-sectional view.” Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-6, 8-10, 12-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US20170236747A1) in view of Chiang et al. (US20190385896A1). Regarding claim 1, as interpreted in view of the indefiniteness rejection, Chen teaches in Fig. 10 a semiconductor device comprising: an active pattern (110) extending in a first direction (horizontal) {[0015]}; a gate structure (M, 132, 142, 5) comprising a gate electrode (14 and/or 16) extending in a second direction (vertical) and a gate spacer (132 and/or 142) on the active pattern (110), wherein the gate electrode (14 and/or 16) and the gate spacer (132 and/or 142) are spaced apart from each other in the first direction (horizontal) {[0016, 0018]}; a source/drain pattern (144) on the active pattern (110) {[0016]}; a contact barrier layer (164) on the source/drain pattern (144) {[0027]}; and a contact filling layer (180’) on the contact barrier layer (164) {[0029]}, wherein an uppermost point of the contact barrier layer (164) is between an upper surface of the contact filling layer (180’) and a lower surface of the contact filling layer (180’) {Fig. 10}. Chen does not teach a first outer wall of each of the contact barrier layer and the contact filling layer extend along a first common plane and a second outer wall of each of the contact barrier layer and the contact filling layer extend along a second common plane, in a cross-sectional view. In an analogous art, Chiang teaches in Fig. 3A and paragraph [0026], a first outer wall (e.g., left-side wall) of each of the contact barrier layer (139) and the contact filling layer (141) extend along a first common plane and a second outer wall (e.g., right-side wall) of each of the contact barrier layer (139) and the contact filling layer (141) extend along a second common plane, in a cross-sectional view. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s semiconductor device based on the teachings of Chiang, to achieve the above-identified subject matter, to prevent the to-be-formed metal fill layer … from penetrating into surrounding silicon or oxide regions. Chiang [0027]. Moreover, all the claimed elements (e.g., contact barrier layer, contact filling layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Chiang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Regarding claim 2, Chen as modified by Chiang teaches the semiconductor device of claim 1, and Chen further teaches wherein the contact filling layer (180’) comprises: a first portion (portion surrounded by 164) having a first width along the first direction (horizontal), wherein the first portion (portion surrounded by 164) is surrounded by the contact barrier layer (164) {Fig. 10}; and a second portion (portion above 164) on the first portion (portion surrounded by 164), not overlapping the contact barrier layer (164) in the first direction (horizontal), and having a second width along the first direction (horizontal) greater than the first width {Fig. 10}. Regarding claim 3, Chen as modified by Chiang teaches the semiconductor device of claim 1, and Chen further teaches further comprising a silicide layer (20) between the source/drain pattern (144) and the contact barrier layer (164), wherein the contact filling layer (180’) does not contact the silicide layer (20) {[0023]}. Regarding claim 4, Chen as modified by Chiang teaches the semiconductor device of claim 1, and Chen further teaches wherein the upper surface of the contact filling layer (180’) and an uppermost surface of the gate structure (M, 132, 142, 5) extend along a common plane {Fig. 10}. Regarding claim 5, Chen as modified by Chiang teaches the semiconductor device of claim 1, and Chen further teaches wherein the contact barrier layer (164) comprises titanium nitride, and the contact filling layer (180’) comprises tungsten {[0022, 0029]}. Regarding claim 6, Chen as modified by Chiang teaches the semiconductor device of claim 1, and Chen further teaches wherein the uppermost point of the contact barrier layer (164) is between an upper surface of the gate electrode (14 and/or 16) and the lower surface of the contact filling layer (180’) {Fig. 10}. Regarding claim 8, Chen as modified by Chiang teaches the semiconductor device of claim 1, and Chen further teaches wherein the contact barrier layer does not comprise silicon (Si) and boron (B) {[0022]}. Regarding claim 9, Chen as modified by Chiang teaches the semiconductor device of claim 1, and Chen further teaches wherein the upper surface of the gate electrode (14 and/or 16) is flat {Fig. 10}. Regarding claim 10, Chen as modified by Chiang teaches the semiconductor device of claim 1, but Chen does not teach wherein the gate structure further comprises a gate capping layer on the gate electrode, and the contact filling layer contacts the gate capping layer. Chiang teaches in Fig. 3C and paragraph [0037], a capping layer (152) on a gate electrode (116), and a contact filling layer (141) contacts the capping layer (152). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s semiconductor device as modified by Chiang based on the further teachings of Chiang – such that Chen’s gate structure further comprises a gate capping layer on the gate electrode, and the contact filling layer contacts the gate capping layer – to seal the upper surface of the semiconductor device from intrusion by other material or influences (e.g., electrical, moisture, air, etc.). Chiang [0038]. Moreover, all the claimed elements (e.g., capping layer, gate electrode, contact filling layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Hwang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Regarding claim 12, Chen as modified by Chiang teaches the semiconductor device of claim 1, and Chen further teaches wherein the contact barrier layer (164) entirely surrounds the lower surface of the contact filling layer (180’) {Fig. 10}. Regarding claim 13, as interpreted in view of the indefiniteness rejection, Chen teaches a semiconductor device comprising: an active pattern (110) extending in a first direction (horizontal) {[0015]}; a gate structure (M, 132, 142, 5) comprising a gate electrode (14 and/or 16) extending in a second direction (vertical) and a gate spacer (132 and/or 142) on the active pattern (110), wherein the gate electrode (14 and/or 16) and the gate spacer (132 and/or 142) are spaced apart from each other in the first direction (horizontal) {[0016, 0018]}; a source/drain pattern (144) on the active pattern (110) {[0016]}; a contact barrier layer (164) on the source/drain pattern (144) {[0027]}; and a contact filling layer (180’) on the contact barrier layer (164) {[0029]}, wherein the contact filling layer (180’) comprises a first portion (portion surrounded by 164) surrounded by the contact barrier layer (164) and a second portion (portion above 164) on the first portion (portion surrounded by 164) that does not overlap the contact barrier layer (164) in the first direction (horizontal) {Fig. 10}, and wherein a first width along the first direction (horizontal) of the first portion (portion surrounded by 164) is smaller than a second width along the first direction (horizontal) of the second portion (portion above 164) {Fig. 10}. Chen does not teach a first outer wall of each of the contact barrier layer and the second portion of the contact filling layer extend along a first common plane and a second outer wall of each of the contact barrier layer and the second portion of the contact filling layer extend along a second common plane, in a cross-sectional view. Chiang teaches in Fig. 3A and paragraph [0026], a first outer wall (e.g., left-side wall) of each of the contact barrier layer (139) and the second portion (portion above 139) of the contact filling layer (141) extend along a first common plane and a second outer wall (e.g., right-side wall) of each of the contact barrier layer (139) and the second portion (portion above 139) of the contact filling layer (141) extend along a second common plane, in a cross-sectional view. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s semiconductor device based on the teachings of Chiang, to achieve the above-identified subject matter, to prevent the to-be-formed metal fill layer … from penetrating into surrounding silicon or oxide regions. Chiang [0027]. Moreover, all the claimed elements (e.g., contact barrier layer, contact filling layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Chiang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Regarding claim 14, Chen as modified by Chiang teaches the semiconductor device of claim 13, and Chen further teaches wherein an uppermost point of the contact barrier layer (164) is between an upper surface of the gate electrode (14 and/or 16) and a lower surface of the contact filling layer (180’) {Fig. 10}. Regarding claim 15, Chen as modified by Chiang teaches the semiconductor device of claim 13, and Chen further teaches wherein the contact barrier layer (164) comprises titanium nitride, and the contact filling layer (180’) comprises tungsten {[0022, 0029]}. Regarding claim 16, Chen as modified by Chiang teaches the semiconductor device of claim 13, and Chen further teaches further comprising a silicide layer (20) between the source/drain pattern (144) and the contact barrier layer (164) {[0023]}. Regarding claim 17, Chen as modified by Chiang teaches the semiconductor device of claim 16, and Chen further teaches wherein a lower surface of the silicide layer (20) is between an upper surface of the source/drain pattern (144) and a lower surface of the source/drain pattern (144) {Fig. 10}. Regarding claim 18, Chen as modified by Chiang teaches the semiconductor device of claim 13, and Chen further teaches wherein an upper surface of the contact filling layer (180’) and an uppermost surface of the gate structure (M, 132, 142, 5) extend along a common plane {Fig. 10}. Regarding claim 20, as interpreted in view of the indefiniteness rejection, Chen teaches in Fig. 10 a semiconductor device comprising: an active pattern (110) extending in a first direction (horizontal) {[0015]}; a gate structure (M, 132, 142, 5) comprising a gate electrode (14 and/or 16) extending in a second direction (vertical) and a gate spacer (132 and/or 142) on the active pattern (110), wherein the gate electrode (14 and/or 16) and the gate spacer (132 and/or 142) are spaced apart from each other in the first direction (horizontal) {[0016, 0018]}; a source/drain pattern (144) on the active pattern (110 {[0016]}); a silicide layer (20) on the source/drain pattern (144) {[0023]}; a contact barrier layer (164) on the silicide layer (20) {[0027]}; and a contact filling layer (180’) on the contact barrier layer (164) {[0029]}, wherein the contact filling layer (180’) comprises a first portion (portion surrounded by 164) surrounded by the contact barrier layer (164) and a second portion (portion above 164) on the first portion (portion surrounded by 164) that does not overlap the contact barrier layer (164) in the first direction (horizontal) {Fig. 10}, wherein a first width of the first portion (portion surrounded by 164) along the first direction (horizontal) is smaller than a second width of the second portion (portion above 164) along the first direction (horizontal) {Fig. 10}, wherein the contact barrier layer (164) comprises titanium nitride and the contact filling layer (180’) comprises tungsten {[0022, 0029]}, and wherein an uppermost point of the contact barrier layer (164) is between an upper surface of the gate electrode (14 and/or 16) and a lower surface of the contact filling layer (180’) {Fig. 10}. Chen does not teach a first outer wall of each of the contact barrier layer and the second portion of the contact filling layer extend along a first common plane and a second outer wall of each of the contact barrier layer and the second portion of the contact filling layer extend along a second common plane, in a cross-sectional view. Chiang teaches in Fig. 3A and paragraph [0026], a first outer wall (e.g., left-side wall) of each of the contact barrier layer (139) and the second portion (portion above 139) of the contact filling layer (141) extend along a first common plane and a second outer wall (e.g., right-side wall) of each of the contact barrier layer (139) and the second portion (portion above 139) of the contact filling layer (141) extend along a second common plane, in a cross-sectional view. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s semiconductor device based on the teachings of Chiang, to achieve the above-identified subject matter, to prevent the to-be-formed metal fill layer … from penetrating into surrounding silicon or oxide regions. Chiang [0027]. Moreover, all the claimed elements (e.g., contact barrier layer, contact filling layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Chiang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Chiang as applied to claim 10 above, and further in view of Leobandung et al. (US20160035857A1). Regarding claim 11, Chen as modified by Chiang teaches the semiconductor device of claim 10, but Chen does not teach further comprising an etch stop layer on a side surface of the gate spacer on the source/drain pattern, wherein the gate capping layer covers an upper surface of the etch stop layer. In an analogous art, Leobandung teaches in Fig. 14 and paragraph [0042] an etch stop layer (904) on a side surface of a gate spacer (112) on a source/drain pattern (202), wherein a gate capping layer (902) covers an upper surface of the etch stop layer (904). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s semiconductor device as modified by Chiang based on the teachings of Leobandung – to include an etch stop layer on a side surface of the gate spacer on the source/drain pattern, wherein the gate capping layer covers an upper surface of the etch stop layer – so contact trenches … may be formed using a selective etching process. Leobandung [0043]. Moreover, all the claimed elements (e.g., etch stop layer, gate spacer, source/drain pattern, capping layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Leobandung) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Chiang as applied to claim 13 above, and further in view of Hwang et al. (US20220069100A1). Regarding claim 19, Chen as modified by Chiang teaches the semiconductor device of claim 13, but Chen does not teach wherein a grain size of the first portion is smaller than a grain size of the second portion. In an analogous art, Hwang teaches in Fig. 4 and paragraph [0052] a grain size (G2) of a first portion (lower portion) of a contact filling layer (185) is smaller than a grain size (G2’) of a second portion (upper portion; e.g., 189) of the contact filling layer (185). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s semiconductor device as modified by Chiang based on the teachings of Hwang – such that a grain size of the first portion is smaller than a grain size of the second portion – to form a grain adjustment region. Hwang [0052]. Moreover, all the claimed elements (e.g., grain size, first and second portions) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Hwang with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Citation of Pertinent Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen et al. (US20160336270A1) teaches a semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID WARD whose telephone number is (703)756-1382. The examiner can normally be reached 6:30-3:30 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /D.W.W./ Examiner, Art Unit 2891 /MATTHEW C LANDAU/ Supervisory Patent Examiner, Art Unit 2891
Read full office action

Prosecution Timeline

Dec 20, 2023
Application Filed
May 06, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
62%
Grant Probability
99%
With Interview (+39.8%)
3y 7m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 63 resolved cases by this examiner. Grant probability derived from career allowance rate.

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