Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see section titled “Rejections under 35. U.S.C. 102 & 103,” filed 05/29/2026, with respect to the rejection of claims 1-4, 6-12, and 14-16 have been fully considered and are persuasive. The rejection of claims 1-4, 6-12, and 14-16 has been withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-7 and 14-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 5 and 13 were cancelled and their limitations were incorporated into independent claims 1 and 9, respectively. However, claims 6-7 still depend on cancelled claim 5 and claims 14-15 still depend on cancelled claim 13. In the interest of compact prosecution, examiner will assume that claims 6-7 are meant to now depend on claim 1 and claims 13-15 are meant to now depend on claim 9, however appropriate correction is required.
Allowable Subject Matter
Claims 1-4, 8-12, and 16 allowed.
Claims 6-7 and 14-15 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1 and its dependent claims. The closest prior art (US20220052206A1, US20150249209A1, US11532556B2) teaches a field effect transistor (FET) structure, comprising:
a gate structure (Cheng fig. 28D central gate structure 240), disposed between a first source/drain (S/D) epitaxial (EPI) structure and a second S/D EPI structure (Fig. 28D central gate structure 240 has source/drain feature 260C to the right of it and source/drain feature 260C to the left of it),
the gate structure comprising a channel structure and a vertical metal gate structure (Cheng fig. 28D central gate structure 240 comprises plurality of channel layers 215’ and gate stack 360A between the channel layers),
the channel structure comprising a plurality of vertically-stacked, horizontal channels connecting the first S/D EPI structure to the second S/D EPI structure horizontally through the vertical metal gate structure that at least partially surrounds the plurality of channels (Cheng fig. 28D central gate structure 240 comprises plurality of channel layers 215’ which are horizontal channels connecting source/drain feature to the right 260C and source/drain feature to the left 260C),
wherein at least one of the first S/D EPI structure and the second S/D EPI structure comprises a lower portion that extends vertically below a bottom surface of the vertical metal gate structure, the lower portion comprising sides and a bottom surface (Cheng fig. 28D both source/drain features 260C to the left and right of gate structure 240 have lower portions which extend beneath a bottom surface of gate structure 240);
a frontside inter-layer dielectric (ILD) layer disposed above the vertical metal gate structure, the first S/D EPI structure, and the second S/D EPI structure (Cheng fig. 28D ILD layer 270 disposed above central gate structure 240 and the source/drain features 260C to either side); and
a backside ILD layer disposed below the vertical metal gate structure, the first S/D EPI structure, and the second S/D EPI structure (Cheng fig. 28D ILD layer 376 disposed above central gate structure 240 and the source/drain features 260C to either side).
However, the closest prior art does not teach in combination with the other claimed elements
a first etch stop material disposed on at least the bottom surface of the lower portion of the second S/D EPI structure.
Additionally, the closest prior art does not teach the above in combination with the further limitations of dependent claims.
Examiner notes that while there are embodiments within the prior art, see Cheng figs. 18B-18D, that teach the use of a patterned protecting layer diagonal to source/drain to protect the gate stack, the cited prior art does not show an embodiment nor any motivation to combine embodiments such that a first etch stop material is disposed on at least the bottom surface of the lower portion of the second S/D EPI structure in addition with the other limitations of the independent claim.
Regarding claim 9 and its dependent claims. The closest prior art (US20220052206A1, US20150249209A1, US11532556B2) teaches a method for fabricating a field effect transistor (FET) structure, the method comprising:
providing a gate structure (Fig. 28D central gate structure 240), disposed between a first source/drain (S/D) epitaxial (EPI) structure and a second S/D EPI structure (Cheng fig. 28D central gate structure 240 has source/drain feature 260C to the right of it and source/drain feature 260C to the left of it),
the gate structure comprising a channel structure and a vertical metal gate structure (Cheng fig. 28D central gate structure 240 comprises plurality of channel layers 215’ and gate stack 360A between the channel layers),
the channel structure comprising a plurality of vertically-stacked, horizontal channels connecting the first S/D EPI structure to the second S/D EPI structure horizontally through the vertical metal gate structure that at least partially surrounds the plurality of channels (Cheng fig. 28D central gate structure 240 comprises plurality of channel layers 215’ which are horizontal channels connecting source/drain feature to the right 260C and source/drain feature to the left 260C),
wherein at least one of the first S/D EPI structure and the second S/D EPI structure comprises a lower portion that extends vertically below a bottom surface of the vertical metal gate structure, the lower portion comprising sides and a bottom surface (Cheng fig. 28D both source/drain features 260C to the left and right of gate structure 240 have lower portions which extend beneath a bottom surface of gate structure 240);
providing a frontside inter-layer dielectric (ILD) layer disposed above the vertical metal gate structure, the first S/D EPI structure, and the second S/D EPI structure (Cheng fig. 28D ILD layer 270 disposed above central gate structure 240 and the source/drain features 260C to either side); and
providing a backside ILD layer disposed below the vertical metal gate structure, the first S/D EPI structure, and the second S/D EPI structure (Cheng fig. 28D ILD layer 376 disposed above central gate structure 240 and the source/drain features 260C to either side).
However, the closest prior art does not teach in combination with the other claimed elements
providing a first etch stop material disposed on at least the bottom surface of the lower portion of the second S/D EPI structure.
Additionally, the closest prior art does not teach the above in combination with the further limitations of dependent claims.
Examiner notes that while there are embodiments within the prior art, see Cheng figs. 18B-18D, that teach the use of a patterned protecting layer diagonal to source/drain to protect the gate stack, the cited prior art does not show an embodiment nor any motivation to combine embodiments such that a first etch stop material is disposed on at least the bottom surface of the lower portion of the second S/D EPI structure in addition with the other limitations of the independent claim.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights