Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 8-12, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (US20220052206A1, hereinafter Cheng).
Regarding claim 1, Cheng discloses a field effect transistor (FET) structure, comprising:
a gate structure (Fig. 28D central gate structure 240), disposed between a first source/drain (S/D) epitaxial (EPI) structure and a second S/D EPI structure (Fig. 28D central gate structure 240 has source/drain feature 260C to the right of it and source/drain feature 260C to the left of it),
the gate structure comprising a channel structure and a vertical metal gate structure (Fig. 28D central gate structure 240 comprises plurality of channel layers 215’ and gate stack 360A between the channel layers),
the channel structure comprising a plurality of vertically-stacked, horizontal channels connecting the first S/D EPI structure to the second S/D EPI structure horizontally through the vertical metal gate structure that at least partially surrounds the plurality of channels (Fig. 28D central gate structure 240 comprises plurality of channel layers 215’ which are horizontal channels connecting source/drain feature to the right 260C and source/drain feature to the left 260C),
wherein at least one of the first S/D EPI structure and the second S/D EPI structure comprises a lower portion that extends vertically below a bottom surface of the vertical metal gate structure, the lower portion comprising sides and a bottom surface (Fig. 28D both source/drain features 260C to the left and right of gate structure 240 have lower portions which extend beneath a bottom surface of gate structure 240);
a frontside inter-layer dielectric (ILD) layer disposed above the vertical metal gate structure, the first S/D EPI structure, and the second S/D EPI structure (Fig. 28D ILD layer 270 disposed above central gate structure 240 and the source/drain features 260C to either side); and
a backside ILD layer disposed below the vertical metal gate structure, the first S/D EPI structure, and the second S/D EPI structure (Fig. 28D ILD layer 376 disposed above central gate structure 240 and the source/drain features 260C to either side).
Regarding claim 2, Cheng discloses the FET structure of claim 1, further comprising:
a first coupling material disposed on the bottom surface of the lower portion of the first S/D EPI structure (Par. 64 teaches that “[s]imilar to the frontside conductive features 380, the backside conductive features 378 may also include multiple conductive layers, such as a silicide“ and that “the silicide layer directly contacts the bottom surface of the source/drain features”); and
a first backside S/D contact (BSDC) extending vertically through the backside ILD layer and in contact with the first coupling material (Fig. 28D backside conductive feature 378 extends through ILD 376 to contact the silicide layer as taught in par. 64).
Regarding claim 3, Cheng discloses the FET structure of claim 2,
wherein the first coupling material comprises silicide (Par. 64 teaches that “[s]imilar to the frontside conductive features 380, the backside conductive features 378 may also include multiple conductive layers, such as a silicide“).
Regarding claim 4, Cheng discloses the FET structure of claim 2,
wherein the first coupling material is further disposed on at least one of the sides of the lower portion of the first S/D EPI structure (Par. 64 teaches that “[s]imilar to the frontside conductive features 380, the backside conductive features 378 may also include multiple conductive layers, such as a silicide“ and that “the silicide layer directly contacts the bottom surface of the source/drain features” which includes a portion of the curved sidewall as seen in fig. 28D).
Regarding claim 8, Cheng discloses the FET structure of claim 1,
wherein the gate structure comprises a gate-all-around (GAA) structure (Par. 18 “method 100 fabricates a multi-gate device that includes p-type GAA transistors”).
Regarding claim 9, Cheng discloses a method for fabricating a field effect transistor (FET) structure, the method comprising:
providing a gate structure (Fig. 28D central gate structure 240), disposed between a first source/drain (S/D) epitaxial (EPI) structure and a second S/D EPI structure (Fig. 28D central gate structure 240 has source/drain feature 260C to the right of it and source/drain feature 260C to the left of it),
the gate structure comprising a channel structure and a vertical metal gate structure (Fig. 28D central gate structure 240 comprises plurality of channel layers 215’ and gate stack 360A between the channel layers),
the channel structure comprising a plurality of vertically-stacked, horizontal channels connecting the first S/D EPI structure to the second S/D EPI structure horizontally through the vertical metal gate structure that at least partially surrounds the plurality of channels (Fig. 28D central gate structure 240 comprises plurality of channel layers 215’ which are horizontal channels connecting source/drain feature to the right 260C and source/drain feature to the left 260C),
wherein at least one of the first S/D EPI structure and the second S/D EPI structure comprises a lower portion that extends vertically below a bottom surface of the vertical metal gate structure, the lower portion comprising sides and a bottom surface (Fig. 28D both source/drain features 260C to the left and right of gate structure 240 have lower portions which extend beneath a bottom surface of gate structure 240);
providing a frontside inter-layer dielectric (ILD) layer disposed above the vertical metal gate structure, the first S/D EPI structure, and the second S/D EPI structure (Fig. 28D ILD layer 270 disposed above central gate structure 240 and the source/drain features 260C to either side); and
providing a backside ILD layer disposed below the vertical metal gate structure, the first S/D EPI structure, and the second S/D EPI structure (Fig. 28D ILD layer 376 disposed above central gate structure 240 and the source/drain features 260C to either side).
Regarding claim 10, Cheng discloses the method of claim 9, further comprising:
providing a first coupling material disposed on the bottom surface of the lower portion of the first S/D EPI structure (Par. 64 teaches that “[s]imilar to the frontside conductive features 380, the backside conductive features 378 may also include multiple conductive layers, such as a silicide“ and that “the silicide layer directly contacts the bottom surface of the source/drain features”); and
providing a first backside S/D contact (BSDC) extending vertically through the backside ILD layer and in contact with the first coupling material (Fig. 28D backside conductive feature 378 extends through ILD 376 to contact the silicide layer as taught in par. 64).
Regarding claim 11, Cheng discloses the method of claim 10,
wherein the first coupling material comprises silicide (Par. 64 teaches that “[s]imilar to the frontside conductive features 380, the backside conductive features 378 may also include multiple conductive layers, such as a silicide“).
Regarding claim 12, Cheng discloses the method of claim 10,
wherein the first coupling material is further disposed on at least one of the sides of the lower portion of the first S/D EPI structure (Par. 64 teaches that “[s]imilar to the frontside conductive features 380, the backside conductive features 378 may also include multiple conductive layers, such as a silicide“ and that “the silicide layer directly contacts the bottom surface of the source/drain features” which includes a portion of the curved sidewall as seen in fig. 28D).
Regarding claim 16, Cheng discloses the method of claim 9,
wherein providing the gate structure comprises providing a gate-all-around (GAA) structure (Par. 18 “method 100 fabricates a multi-gate device that includes p-type GAA transistors”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US20220052206A1).
Regarding claim 5, Cheng teaches the FET structure of claim 1,
further comprising a first etch stop material disposed on at least the bottom surface of the lower portion of the second S/D EPI structure (Par. 58 teaches “the patterned protecting layer 374 includes other one or more material different from the gate stack 360B and the channel layers 215′ so that the subsequent etching process has no (or minimal) etching effect to the protecting layer.” While Cheng does not explicitly disclose a first etch stop material disposed on at least the bottom surface of the lower portion of the second S/D EPI structure, the primary function of an etch stop layer, as taught above by Cheng, is to protect an underlying layer during etching and etch to a desired depth. A rearrangement of the patterned protecting layer 374 to be disposed on at least the bottom surface of the lower portion of the second S/D EPI structure would not provide any new or unexpected results as the primary function of protecting an underlying layer from overetching and etching to a desired depth is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore rearrange patterned protecting layer 374 to have a first etch stop material disposed on at least the bottom surface of the lower portion of the second S/D EPI structure, see MPEP 2144.04(VI)(B)).
Regarding claim 6, Cheng teaches the FET structure of claim 5,
wherein the first etch stop material is further disposed on at least one of the sides of the lower portion of the second S/D EPI structure (Cheng fig. 28D teaches a source/drain feature 260C with a rounded bottom and so an etch stop layer, as taught above in the rejection of claim 5, would be disposed on at least a portion of the curved sidewalls of source/drain feature 260C).
Regarding claim 13, Cheng teaches the method of claim 9, further comprising:
providing a first etch stop material disposed on at least the bottom surface of the lower portion of the second S/D EPI structure (Par. 58 teaches “the patterned protecting layer 374 includes other one or more material different from the gate stack 360B and the channel layers 215′ so that the subsequent etching process has no (or minimal) etching effect to the protecting layer.” While Cheng does not explicitly disclose a first etch stop material disposed on at least the bottom surface of the lower portion of the second S/D EPI structure, the primary function of an etch stop layer, as taught above by Cheng, is to protect an underlying layer during etching and etch to a desired depth. A rearrangement of the patterned protecting layer 374 to be disposed on at least the bottom surface of the lower portion of the second S/D EPI structure would not provide any new or unexpected results as the primary function of protecting an underlying layer from overetching and etching to a desired depth is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore rearrange patterned protecting layer 374 to have a first etch stop material disposed on at least the bottom surface of the lower portion of the second S/D EPI structure, see MPEP 2144.04(VI)(B)).
Regarding claim 14, Cheng teaches the method of claim 13,
wherein the first etch stop material is further disposed on at least one of the sides of the lower portion of the second S/D EPI structure (Cheng fig. 28D teaches a source/drain feature 260C with a rounded bottom and so an etch stop layer, as taught above in the rejection of claim 5, would be disposed on at least a portion of the curved sidewalls of source/drain feature 260C).
Claims 7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US20220052206A1) as applied to claim 5 above, and further in view of Lu et al. (US20150249209A1, hereinafter Lu).
Regarding claim 7, Cheng teaches the FET structure of claim 5.
Cheng does not appear to teach
wherein the first etch stop material comprises at least one of titanium silicide (TiSi), silicon carbon nitride (SiCN), silicon carbon oxynitride (SiCON), aluminum nitride (AlN), an area-selective deposition (ASD) dielectric, or a silicon-germanium (SiGe) epitaxial layer.
Lu teaches
wherein the first etch stop material comprises silicon carbon nitride (SiCN) (Par. 27 “[t]he exemplary low K etch stop layer can be formed of insulating materials such as silicon carbon nitride (SiCN)”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention as both Cheng and Lu teach suitable materials for use in an etch stop layer, it would have been obvious to substitute Cheng’s etch stop with Lu’s etch stop formed from SiCN to achieve the predictable result of forming an etch stop formed from SiCN.
Regarding claim 15, Cheng teaches the method of claim 13.
Cheng does not appear to teach
wherein the first etch stop material comprises at least one of titanium silicide (TiSi), silicon carbon nitride (SiCN), silicon carbon oxynitride (SiCON), aluminum nitride (AlN), an area-selective deposition (ASD) dielectric, or a silicon-germanium (SiGe) epitaxial layer.
Lu teaches
wherein the first etch stop material comprises silicon carbon nitride (SiCN) (Par. 27 “[t]he exemplary low K etch stop layer can be formed of insulating materials such as silicon carbon nitride (SiCN)”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention as both Cheng and Lu teach suitable materials for use in an etch stop layer, it would have been obvious to substitute Cheng’s etch stop with Lu’s etch stop formed from SiCN to achieve the predictable result of forming an etch stop formed from SiCN.
Conclusion
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/COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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