DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-3, 5-12, and 14-22 are pending in this office action and presented for examination. Claims 1, 5, 10, 14, and 19 are newly amended; claims 4 and 13 are newly cancelled; and claims 21-22 are newly added by the response received June 5, 2026.
Examiner notes that claims 5 and 14 appear to have language deleted without appropriate strikethrough, which may make it unclear as to whether the language was deleted purposefully or inadvertently. If on purpose, Examiner recommends readding and then marking up the deleted language appropriately in the next response; if inadvertently, Examiner recommends readding the deleted language.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3, 5-12, and 14-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the partial results” in line 6. However, it is indefinite as to whether the antecedent basis for this limitation is “partial results” in claim 1, line 2, or “partial results” as recited in claim 1, lines 4-5. Note that this limitation is also recited in claim 1, line 7; claim 1, line 9; claim 2, line 2; claim 3, line 2; claim 3, line 3; claim 8, line 2; and claim 9, line 1.
Claims 2-3 and 5-9 are rejected for failing to alleviate the rejection of claim 1 above.
Claim 10 recites the limitation “the partial results” in line 8. However, it is indefinite as to whether the antecedent basis for this limitation is “partial results” in claim 10, line 4, or “partial results” as recited in claim 10, line 7. Note that this limitation is also recited in claim 10, line 9; claim 10, line 11; claim 11, line 2; claim 12, line 2; claim 12, line 3; claim 17, line 2; and claim 18, line 1.
Claims 11-12 and 14-18 are rejected for failing to alleviate the rejection of claim 10 above.
Claim 19 recites the limitation “the partial results” in line 8. However, it is indefinite as to whether the antecedent basis for this limitation is “partial results” in claim 19, line 4, or “partial results” as recited in claim 19, lines 6-7. Note that this limitation is also recited in claim 19, line 9; claim 19, line 11; claim 20, line 3; claim 21, line 2; and claim 21, line 3.
Claims 20-22 are rejected for failing to alleviate the rejection of claim 19 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 5-11, 14-20, and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (Kim) (US 20070027870 A1) in view of Norrie et al. (Norrie) (US 20210263739 A1) in view of Zbiciak (US 20170308381 A1) in view of Sprangle et al. (Sprangle) (US 20090172349 A1).
Consider claim 1, Kim discloses a method comprising: opening an aperture for processing partial results per an open aperture command, wherein the aperture is a memory address range for writing operands into ([0023], lines 20-25, in one embodiment, the memory controller manages the partial results by storing them in a buffer before reducing the partial results to a combined result, such as a summation of the partial results, product of the partial results, or other operation; regarding the open aperture command, see [0022], lines 3-15, at operation 401, a task is detected that will use multiple processing elements to compute a number of partial results that will be reduced into a combined result. In one embodiment, the task is indicated by a particular type of instruction within a program being executed by a processing system in which one embodiment is used. In another embodiment, the task is detected by an access by an instruction to a particular memory range, in which a data structure is stored, that is designated to be associated with tasks that will use multiple processing elements to generate a number of partial results, which will then be reduced to a combined result before being stored to the data structure. In other embodiments, the task may be indicated in other ways), partial results written into the aperture and final results generated using the partial results written into the aperture ([0023], lines 20-25, in one embodiment, the memory controller manages the partial results by storing them in a buffer before reducing the partial results to a combined result, such as a summation of the partial results, product of the partial results, or other operation); receiving the partial results in the aperture ([0023], lines 20-25, in one embodiment, the memory controller manages the partial results by storing them in a buffer before reducing the partial results to a combined result, such as a summation of the partial results, product of the partial results, or other operation) from multiple processing units operating in parallel ([0001], lines 3-4, performing a number of computations in a number of processing elements in parallel; claim 9, lines 4-5, a plurality of processing elements to generate a plurality of partial results of the instruction in parallel; [0018], lines 3-4, processing elements 301, 303, 305, 307); processing the partial results to generate final results ([0023], lines 20-25, in one embodiment, the memory controller manages the partial results by storing them in a buffer before reducing the partial results to a combined result, such as a summation of the partial results, product of the partial results, or other operation; [0019], lines 5-13, in one embodiment, the shared memory and/or main memory contains a data structure 317 that will store a final result of a combined set of calculations from each of the processing elements. For example, in one embodiment, the data structure will contain a sum of a plurality of numbers computed by each of the processing elements, whereas in other embodiments, the data structure may contain a product, or some other mathematical reduction of numbers computed by each of the processing elements; [0020], lines 6-17, the individual processing elements may store a result of the partial calculation performed by each processing element in their respective local copies of the data structure and then may send the partial results concurrently to the shared L2 cache or to the memory controller, in which the partial results can be combined and stored in main memory concurrently, instead of serially as in the prior art. In one embodiment of the invention, the memory controller contains logic to combine the results of the computations produced by the processing elements and store the combined result into the original data structure within the main memory).
In addition, to any extent to which Kim does not implicitly disclose that the aperture is a memory address range for writing operands into, Norrie explicitly discloses a memory address range in general, as well as an aperture being a memory address range for writing operands into in particular ([0079], lines 14-17, the address locations in memory cells of the shared memory 104 can be used to write (store) results of computes that occur at different components of system 100; [0080], lines 1-5, the system 100 includes an operator/accumulator unit 320 (“operator 320”) that is (or can be) coupled to the shared memory 104. The operator 320 is configured to accumulate values based on one or more arithmetic operations). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Norrie with the invention of Kim to facilitate data storage. Alternatively, this modification merely entails combining prior art elements (the cited prior art elements of Kim, and the well-known concept of a memory address range as explicitly disclosed by Norrie) according to known methods (Examiner submits that memory addressing in general was known to one of ordinary skill in the art before the effective filing date of the claimed invention, as also evidenced by Norrie) to yield predictable results (the invention of Kim, wherein the aperture comprises, in particular, a memory address range, for writing operands into), which is a rationale that may support a conclusion of obviousness as per MPEP 2143.
However, the combination thus far does not entail closing the aperture per a close aperture command, wherein after the aperture is closed, the multiple processing units are not permitted to write into the aperture. The combination thus far also does not entail that the aforementioned open aperture command specifies an input data type for the aforementioned partial results written into the aperture and an output data type for the aforementioned final results generated using the partial results written into the aperture.
On the other hand, Zbiciak discloses, in addition to an open command ([0198], lines 3-4, A STROPEN instruction opens a stream), closing per a close command ([0205], lines 1-2, a STRCLOSE instruction closes a stream in active state 3602), wherein after closing, not permitting data to be written from memory to be operated on ([0205], lines 7-12, a STRCLOSE instruction ends the corresponding stream immediately, allowing a program to prematurely terminate one or both streams. A STRCLOSE instruction does not stall processor 100, and does not wait for the stream to finish sending requests).
Zbiciak’s teaching allows a program to specifically state it no longer needs resources, and clears state (Zbiciak, [0207], lines 1-8), which facilitates multitasking by enabling other tasks to use those resources and increases security by preventing other tasks from seeing state. Zbiciak’s teaching also enables a known state to be reached (Zbiciak, [0206], lines 6-9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Zbiciak with the combination of Kim and Norrie in order to facilitate reuse of resources, increase security, and enable a known state to be reached. Note that Zbiciak’s teaching of an open command and a close command to respectively permit and not permit data to be written from memory to be operated on, when applied to the combination of Kim and Norrie wherein data to be operated on is written from multiple processing units to a buffer, results in the overall claimed limitation of closing the aperture per a close aperture command, wherein after the aperture is closed, the multiple processing units are not permitted to write into the aperture. Alternatively, this modification merely entails combining prior art elements (the prior art elements cited above, including an aperture, of the combination of Kim and Norrie, and Zbiciak’s teaching of an open and close command) according to known methods (Examiner submits the general concept of opening and closing to regulate data flow is known, such as opening and closing network ports) to yield predictable results (the combination of Kim and Norrie, wherein writing to an aperture is or is not permitted based on an open aperture command and a close aperture command respectively), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
However, the combination thus far does not entail that the aforementioned open aperture command specifies an input data type for the aforementioned partial results written into the aperture and an output data type for the aforementioned final results generated using the partial results written into the aperture.
On the other hand, Sprangle discloses a command specifies an input data type and an output data type (FIG. 7, which shows the command specifying an addition entailing input data type float16 and output data type F32 (float 32)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Sprangle with the combination of Kim, Norrie, and Zbiciak in order to increase processor capability by supporting different data types. Alternatively, this modification merely entails combining prior art elements (the cited prior art elements of Kim, Norrie, and Zbiciak, including an open aperture command, an aperture, partial results, and final results generated using the partial results, and Sprangle’s teaching of a command specifying an input data type and an output data type) according to known methods (Examiner submits that the concept of an input data type and an output data type was known to one of ordinary skill in the art before the effective filing date of the claimed invention) to yield predictable results (the combination of Kim, Norrie, and Zbiciak, wherein the open aperture command specifies an input data type for partial results written into the aperture and an output data type for final results generated using the partial results written into the aperture), which is a rationale that may support a conclusion of obviousness as per MPEP 2143.
Consider claim 2, the overall combination entails the method of claim 1 (see above), wherein the aperture comprises a memory address into which the partial results are written (Kim, [0023], lines 20-25, in one embodiment, the memory controller manages the partial results by storing them in a buffer before reducing the partial results to a combined result, such as a summation of the partial results, product of the partial results, or other operation; Norrie, [0079], lines 14-17, the address locations in memory cells of the shared memory 104 can be used to write (store) results of computes that occur at different components of system 100; [0080], lines 1-5, the system 100 includes an operator/accumulator unit 320 (“operator 320”) that is (or can be) coupled to the shared memory 104. The operator 320 is configured to accumulate values based on one or more arithmetic operations).
Consider claim 5, the combination thus far entails the method of claim 1 (see above), wherein the open aperture command specifies an address of an output buffer (Kim, [0022], lines 3-15, at operation 401, a task is detected that will use multiple processing elements to compute a number of partial results that will be reduced into a combined result. In one embodiment, the task is indicated by a particular type of instruction within a program being executed by a processing system in which one embodiment is used. In another embodiment, the task is detected by an access by an instruction to a particular memory range, in which a data structure is stored, that is designated to be associated with tasks that will use multiple processing elements to generate a number of partial results, which will then be reduced to a combined result before being stored to the data structure. In other embodiments, the task may be indicated in other ways; also see Sprangle, e.g., the destination argument 84, 0b1000, in FIG. 8) and an operator ([0022], lines 3-15, at operation 401, a task is detected that will use multiple processing elements to compute a number of partial results that will be reduced into a combined result. In one embodiment, the task is indicated by a particular type of instruction within a program being executed by a processing system in which one embodiment is used. In another embodiment, the task is detected by an access by an instruction to a particular memory range, in which a data structure is stored, that is designated to be associated with tasks that will use multiple processing elements to generate a number of partial results, which will then be reduced to a combined result before being stored to the data structure. In other embodiments, the task may be indicated in other ways; [0019], lines 5-13, in one embodiment, the shared memory and/or main memory contains a data structure 317 that will store a final result of a combined set of calculations from each of the processing elements. For example, in one embodiment, the data structure will contain a sum of a plurality of numbers computed by each of the processing elements, whereas in other embodiments, the data structure may contain a product, or some other mathematical reduction of numbers computed by each of the processing elements; also see Sprangle, opcode 172 in FIG. 7).
Consider claim 6, the overall combination entails the method of claim 5 (see above), wherein the processing comprises storing the final results in the output buffer (Kim, [0019], lines 5-13, in one embodiment, the shared memory and/or main memory contains a data structure 317 that will store a final result of a combined set of calculations from each of the processing elements. For example, in one embodiment, the data structure will contain a sum of a plurality of numbers computed by each of the processing elements, whereas in other embodiments, the data structure may contain a product, or some other mathematical reduction of numbers computed by each of the processing elements; [0020], lines 6-17, the individual processing elements may store a result of the partial calculation performed by each processing element in their respective local copies of the data structure and then may send the partial results concurrently to the shared L2 cache or to the memory controller, in which the partial results can be combined and stored in main memory concurrently, instead of serially as in the prior art. In one embodiment of the invention, the memory controller contains logic to combine the results of the computations produced by the processing elements and store the combined result into the original data structure within the main memory).
Consider claim 7, the overall combination entails the method of claim 5 (see above), wherein the operator specifies a fixed operation or a programmatically defined operation (Kim, [0019], lines 5-13, in one embodiment, the shared memory and/or main memory contains a data structure 317 that will store a final result of a combined set of calculations from each of the processing elements. For example, in one embodiment, the data structure will contain a sum of a plurality of numbers computed by each of the processing elements, whereas in other embodiments, the data structure may contain a product, or some other mathematical reduction of numbers computed by each of the processing elements; [0020], lines 6-17, the individual processing elements may store a result of the partial calculation performed by each processing element in their respective local copies of the data structure and then may send the partial results concurrently to the shared L2 cache or to the memory controller, in which the partial results can be combined and stored in main memory concurrently, instead of serially as in the prior art. In one embodiment of the invention, the memory controller contains logic to combine the results of the computations produced by the processing elements and store the combined result into the original data structure within the main memory; [0022], lines 3-15, at operation 401, a task is detected that will use multiple processing elements to compute a number of partial results that will be reduced into a combined result. In one embodiment, the task is indicated by a particular type of instruction within a program being executed by a processing system in which one embodiment is used. In another embodiment, the task is detected by an access by an instruction to a particular memory range, in which a data structure is stored, that is designated to be associated with tasks that will use multiple processing elements to generate a number of partial results, which will then be reduced to a combined result before being stored to the data structure. In other embodiments, the task may be indicated in other ways).
Consider claim 8, the overall combination entails the method of claim 5 (see above), wherein the processing comprises applying the operator to the partial results to generate the final results (Kim, [0019], lines 5-13, in one embodiment, the shared memory and/or main memory contains a data structure 317 that will store a final result of a combined set of calculations from each of the processing elements. For example, in one embodiment, the data structure will contain a sum of a plurality of numbers computed by each of the processing elements, whereas in other embodiments, the data structure may contain a product, or some other mathematical reduction of numbers computed by each of the processing elements; [0020], lines 6-17, the individual processing elements may store a result of the partial calculation performed by each processing element in their respective local copies of the data structure and then may send the partial results concurrently to the shared L2 cache or to the memory controller, in which the partial results can be combined and stored in main memory concurrently, instead of serially as in the prior art. In one embodiment of the invention, the memory controller contains logic to combine the results of the computations produced by the processing elements and store the combined result into the original data structure within the main memory).
Consider claim 9, the overall combination entails the method of claim 1 (see above), wherein the partial results are generated in parallel (Kim, [0021], lines 9-10, moreover, embodiments of the invention may concurrently generate partial results).
Consider claim 10, Kim discloses a system comprising: a memory configured to store data for an aperture ([0018], line 5, local memories; [0023], line 22, buffer); and a hardware processor ([0018], lines 5-9, processor) configured to: open the aperture for processing partial results per an open aperture command, wherein the aperture is a memory address range for writing operands into ([0023], lines 20-25, in one embodiment, the memory controller manages the partial results by storing them in a buffer before reducing the partial results to a combined result, such as a summation of the partial results, product of the partial results, or other operation; regarding the open aperture command, see [0022], lines 3-15, at operation 401, a task is detected that will use multiple processing elements to compute a number of partial results that will be reduced into a combined result. In one embodiment, the task is indicated by a particular type of instruction within a program being executed by a processing system in which one embodiment is used. In another embodiment, the task is detected by an access by an instruction to a particular memory range, in which a data structure is stored, that is designated to be associated with tasks that will use multiple processing elements to generate a number of partial results, which will then be reduced to a combined result before being stored to the data structure. In other embodiments, the task may be indicated in other ways), partial results written into the aperture and final results generated using the partial results written into the aperture ([0023], lines 20-25, in one embodiment, the memory controller manages the partial results by storing them in a buffer before reducing the partial results to a combined result, such as a summation of the partial results, product of the partial results, or other operation); receiving the partial results in the aperture ([0023], lines 20-25, in one embodiment, the memory controller manages the partial results by storing them in a buffer before reducing the partial results to a combined result, such as a summation of the partial results, product of the partial results, or other operation) from multiple processing units of the hardware processor operating in parallel ([0001], lines 3-4, performing a number of computations in a number of processing elements in parallel; claim 9, lines 4-5, a plurality of processing elements to generate a plurality of partial results of the instruction in parallel; [0018], lines 3-4, processing elements 301, 303, 305, 307); processing the partial results to generate final results ([0023], lines 20-25, in one embodiment, the memory controller manages the partial results by storing them in a buffer before reducing the partial results to a combined result, such as a summation of the partial results, product of the partial results, or other operation; [0019], lines 5-13, in one embodiment, the shared memory and/or main memory contains a data structure 317 that will store a final result of a combined set of calculations from each of the processing elements. For example, in one embodiment, the data structure will contain a sum of a plurality of numbers computed by each of the processing elements, whereas in other embodiments, the data structure may contain a product, or some other mathematical reduction of numbers computed by each of the processing elements; [0020], lines 6-17, the individual processing elements may store a result of the partial calculation performed by each processing element in their respective local copies of the data structure and then may send the partial results concurrently to the shared L2 cache or to the memory controller, in which the partial results can be combined and stored in main memory concurrently, instead of serially as in the prior art. In one embodiment of the invention, the memory controller contains logic to combine the results of the computations produced by the processing elements and store the combined result into the original data structure within the main memory).
In addition, to any extent to which Kim does not implicitly disclose that the aperture is a memory address range for writing operands into, Norrie explicitly discloses a memory address range in general, as well as an aperture being a memory address range for writing operands into in particular ([0079], lines 14-17, the address locations in memory cells of the shared memory 104 can be used to write (store) results of computes that occur at different components of system 100; [0080], lines 1-5, the system 100 includes an operator/accumulator unit 320 (“operator 320”) that is (or can be) coupled to the shared memory 104. The operator 320 is configured to accumulate values based on one or more arithmetic operations). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Norrie with the invention of Kim to facilitate data storage. Alternatively, this modification merely entails combining prior art elements (the cited prior art elements of Kim, and the well-known concept of a memory address range as explicitly disclosed by Norrie) according to known methods (Examiner submits that memory addressing in general was known to one of ordinary skill in the art before the effective filing date of the claimed invention, as also evidenced by Norrie) to yield predictable results (the invention of Kim, wherein the aperture comprises, in particular, a memory address range, for writing operands into), which is a rationale that may support a conclusion of obviousness as per MPEP 2143.
However, the combination thus far does not entail closing the aperture per a close aperture command, wherein after the aperture is closed, the multiple processing units are not permitted to write into the aperture. The combination thus far also does not entail that the aforementioned open aperture command specifies an input data type for the aforementioned partial results written into the aperture and an output data type for the aforementioned final results generated using the partial results written into the aperture.
On the other hand, Zbiciak discloses, in addition to an open command ([0198], lines 3-4, A STROPEN instruction opens a stream), closing per a close command ([0205], lines 1-2, a STRCLOSE instruction closes a stream in active state 3602), wherein after closing, not permitting data to be written from memory to be operated on ([0205], lines 7-12, a STRCLOSE instruction ends the corresponding stream immediately, allowing a program to prematurely terminate one or both streams. A STRCLOSE instruction does not stall processor 100, and does not wait for the stream to finish sending requests).
Zbiciak’s teaching allows a program to specifically state it no longer needs resources, and clears state (Zbiciak, [0207], lines 1-8), which facilitates multitasking by enabling other tasks to use those resources and increases security by preventing other tasks from seeing state. Zbiciak’s teaching also enables a known state to be reached (Zbiciak, [0206], lines 6-9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Zbiciak with the combination of Kim and Norrie in order to facilitate reuse of resources, increase security, and enable a known state to be reached. Note that Zbiciak’s teaching of an open command and a close command to respectively permit and not permit data to be written from memory to be operated on, when applied to the combination of Kim and Norrie wherein data to be operated on is written from multiple processing units to a buffer, results in the overall claimed limitation of closing the aperture per a close aperture command, wherein after the aperture is closed, the multiple processing units are not permitted to write into the aperture. Alternatively, this modification merely entails combining prior art elements (the prior art elements cited above, including an aperture, of the combination of Kim and Norrie, and Zbiciak’s teaching of an open and close command) according to known methods (Examiner submits the general concept of opening and closing to regulate data flow is known, such as opening and closing network ports) to yield predictable results (the combination of Kim and Norrie, wherein writing to an aperture is or is not permitted based on an open aperture command and a close aperture command respectively), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
However, the combination thus far does not entail that the aforementioned open aperture command specifies an input data type for the aforementioned partial results written into the aperture and an output data type for the aforementioned final results generated using the partial results written into the aperture.
On the other hand, Sprangle discloses a command specifies an input data type and an output data type (FIG. 7, which shows the command specifying an addition entailing input data type float16 and output data type F32 (float 32)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Sprangle with the combination of Kim, Norrie, and Zbiciak in order to increase processor capability by supporting different data types. Alternatively, this modification merely entails combining prior art elements (the cited prior art elements of Kim, Norrie, and Zbiciak, including an open aperture command, an aperture, partial results, and final results generated using the partial results, and Sprangle’s teaching of a command specifying an input data type and an output data type) according to known methods (Examiner submits that the concept of an input data type and an output data type was known to one of ordinary skill in the art before the effective filing date of the claimed invention) to yield predictable results (the combination of Kim, Norrie, and Zbiciak, wherein the open aperture command specifies an input data type for partial results written into the aperture and an output data type for final results generated using the partial results written into the aperture), which is a rationale that may support a conclusion of obviousness as per MPEP 2143.
Consider claim 11, the overall combination entails the system of claim 10 (see above), wherein the aperture comprises a memory address into which the partial results are written (Kim, [0023], lines 20-25, in one embodiment, the memory controller manages the partial results by storing them in a buffer before reducing the partial results to a combined result, such as a summation of the partial results, product of the partial results, or other operation; Norrie, [0079], lines 14-17, the address locations in memory cells of the shared memory 104 can be used to write (store) results of computes that occur at different components of system 100; [0080], lines 1-5, the system 100 includes an operator/accumulator unit 320 (“operator 320”) that is (or can be) coupled to the shared memory 104. The operator 320 is configured to accumulate values based on one or more arithmetic operations).
Consider claim 14, the combination thus far entails the system of claim 10, wherein the open aperture command specifies an address of an output buffer (Kim, [0022], lines 3-15, at operation 401, a task is detected that will use multiple processing elements to compute a number of partial results that will be reduced into a combined result. In one embodiment, the task is indicated by a particular type of instruction within a program being executed by a processing system in which one embodiment is used. In another embodiment, the task is detected by an access by an instruction to a particular memory range, in which a data structure is stored, that is designated to be associated with tasks that will use multiple processing elements to generate a number of partial results, which will then be reduced to a combined result before being stored to the data structure. In other embodiments, the task may be indicated in other ways; also see Sprangle, e.g., the destination argument 84, 0b1000, in FIG. 8) and an operator ([0022], lines 3-15, at operation 401, a task is detected that will use multiple processing elements to compute a number of partial results that will be reduced into a combined result. In one embodiment, the task is indicated by a particular type of instruction within a program being executed by a processing system in which one embodiment is used. In another embodiment, the task is detected by an access by an instruction to a particular memory range, in which a data structure is stored, that is designated to be associated with tasks that will use multiple processing elements to generate a number of partial results, which will then be reduced to a combined result before being stored to the data structure. In other embodiments, the task may be indicated in other ways; [0019], lines 5-13, in one embodiment, the shared memory and/or main memory contains a data structure 317 that will store a final result of a combined set of calculations from each of the processing elements. For example, in one embodiment, the data structure will contain a sum of a plurality of numbers computed by each of the processing elements, whereas in other embodiments, the data structure may contain a product, or some other mathematical reduction of numbers computed by each of the processing elements; also see Sprangle, opcode 172 in FIG. 7).
Consider claim 15, the overall combination entails the system of claim 14 (see above), wherein the processing comprises storing the final results in the output buffer (Kim, [0019], lines 5-13, in one embodiment, the shared memory and/or main memory contains a data structure 317 that will store a final result of a combined set of calculations from each of the processing elements. For example, in one embodiment, the data structure will contain a sum of a plurality of numbers computed by each of the processing elements, whereas in other embodiments, the data structure may contain a product, or some other mathematical reduction of numbers computed by each of the processing elements; [0020], lines 6-17, the individual processing elements may store a result of the partial calculation performed by each processing element in their respective local copies of the data structure and then may send the partial results concurrently to the shared L2 cache or to the memory controller, in which the partial results can be combined and stored in main memory concurrently, instead of serially as in the prior art. In one embodiment of the invention, the memory controller contains logic to combine the results of the computations produced by the processing elements and store the combined result into the original data structure within the main memory).
Consider claim 16, the overall combination entails the system of claim 14 (see above), wherein the operator specifies a fixed operation or a programmatically defined operation (Kim, [0019], lines 5-13, in one embodiment, the shared memory and/or main memory contains a data structure 317 that will store a final result of a combined set of calculations from each of the processing elements. For example, in one embodiment, the data structure will contain a sum of a plurality of numbers computed by each of the processing elements, whereas in other embodiments, the data structure may contain a product, or some other mathematical reduction of numbers computed by each of the processing elements; [0020], lines 6-17, the individual processing elements may store a result of the partial calculation performed by each processing element in their respective local copies of the data structure and then may send the partial results concurrently to the shared L2 cache or to the memory controller, in which the partial results can be combined and stored in main memory concurrently, instead of serially as in the prior art. In one embodiment of the invention, the memory controller contains logic to combine the results of the computations produced by the processing elements and store the combined result into the original data structure within the main memory; [0022], lines 3-15, at operation 401, a task is detected that will use multiple processing elements to compute a number of partial results that will be reduced into a combined result. In one embodiment, the task is indicated by a particular type of instruction within a program being executed by a processing system in which one embodiment is used. In another embodiment, the task is detected by an access by an instruction to a particular memory range, in which a data structure is stored, that is designated to be associated with tasks that will use multiple processing elements to generate a number of partial results, which will then be reduced to a combined result before being stored to the data structure. In other embodiments, the task may be indicated in other ways).
Consider claim 17, the overall combination entails the system of claim 14 (see above), wherein the processing comprises applying the operator to the partial results to generate the final results (Kim, [0019], lines 5-13, in one embodiment, the shared memory and/or main memory contains a data structure 317 that will store a final result of a combined set of calculations from each of the processing elements. For example, in one embodiment, the data structure will contain a sum of a plurality of numbers computed by each of the processing elements, whereas in other embodiments, the data structure may contain a product, or some other mathematical reduction of numbers computed by each of the processing elements; [0020], lines 6-17, the individual processing elements may store a result of the partial calculation performed by each processing element in their respective local copies of the data structure and then may send the partial results concurrently to the shared L2 cache or to the memory controller, in which the partial results can be combined and stored in main memory concurrently, instead of serially as in the prior art. In one embodiment of the invention, the memory controller contains logic to combine the results of the computations produced by the processing elements and store the combined result into the original data structure within the main memory)
Consider claim 18, the overall combination entails the system of claim 10 (see above), wherein the partial results are generated in parallel (Kim, [0021], lines 9-10, moreover, embodiments of the invention may concurrently generate partial results).
Consider claim 19, Kim discloses a non-transitory computer-readable medium storing instructions that, when executed, cause a processor to perform operations ([0032], lines 4-8, aspects may be implemented using instructions stored on a machine-readable medium (software), which if executed by a processor, would cause the processor to perform a method to carry out embodiments of the invention) comprising: opening an aperture for processing partial results per an open aperture command, wherein the aperture is a memory address range for writing operands into ([0023], lines 20-25, in one embodiment, the memory controller manages the partial results by storing them in a buffer before reducing the partial results to a combined result, such as a summation of the partial results, product of the partial results, or other operation; regarding the open aperture command, see [0022], lines 3-15, at operation 401, a task is detected that will use multiple processing elements to compute a number of partial results that will be reduced into a combined result. In one embodiment, the task is indicated by a particular type of instruction within a program being executed by a processing system in which one embodiment is used. In another embodiment, the task is detected by an access by an instruction to a particular memory range, in which a data structure is stored, that is designated to be associated with tasks that will use multiple processing elements to generate a number of partial results, which will then be reduced to a combined result before being stored to the data structure. In other embodiments, the task may be indicated in other ways), partial results written into the aperture and final results generated using the partial results written into the aperture ([0023], lines 20-25, in one embodiment, the memory controller manages the partial results by storing them in a buffer before reducing the partial results to a combined result, such as a summation of the partial results, product of the partial results, or other operation); receiving the partial results in the aperture ([0023], lines 20-25, in one embodiment, the memory controller manages the partial results by storing them in a buffer before reducing the partial results to a combined result, such as a summation of the partial results, product of the partial results, or other operation) from multiple processing units operating in parallel ([0001], lines 3-4, performing a number of computations in a number of processing elements in parallel; claim 9, lines 4-5, a plurality of processing elements to generate a plurality of partial results of the instruction in parallel; [0018], lines 3-4, processing elements 301, 303, 305, 307); processing the partial results to generate final results ([0023], lines 20-25, in one embodiment, the memory controller manages the partial results by storing them in a buffer before reducing the partial results to a combined result, such as a summation of the partial results, product of the partial results, or other operation; [0019], lines 5-13, in one embodiment, the shared memory and/or main memory contains a data structure 317 that will store a final result of a combined set of calculations from each of the processing elements. For example, in one embodiment, the data structure will contain a sum of a plurality of numbers computed by each of the processing elements, whereas in other embodiments, the data structure may contain a product, or some other mathematical reduction of numbers computed by each of the processing elements; [0020], lines 6-17, the individual processing elements may store a result of the partial calculation performed by each processing element in their respective local copies of the data structure and then may send the partial results concurrently to the shared L2 cache or to the memory controller, in which the partial results can be combined and stored in main memory concurrently, instead of serially as in the prior art. In one embodiment of the invention, the memory controller contains logic to combine the results of the computations produced by the processing elements and store the combined result into the original data structure within the main memory).
In addition, to any extent to which Kim does not implicitly disclose that the aperture is a memory address range for writing operands into, Norrie explicitly discloses a memory address range in general, as well as an aperture being a memory address range for writing operands into in particular ([0079], lines 14-17, the address locations in memory cells of the shared memory 104 can be used to write (store) results of computes that occur at different components of system 100; [0080], lines 1-5, the system 100 includes an operator/accumulator unit 320 (“operator 320”) that is (or can be) coupled to the shared memory 104. The operator 320 is configured to accumulate values based on one or more arithmetic operations). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Norrie with the invention of Kim to facilitate data storage. Alternatively, this modification merely entails combining prior art elements (the cited prior art elements of Kim, and the well-known concept of a memory address range as explicitly disclosed by Norrie) according to known methods (Examiner submits that memory addressing in general was known to one of ordinary skill in the art before the effective filing date of the claimed invention, as also evidenced by Norrie) to yield predictable results (the invention of Kim, wherein the aperture comprises, in particular, a memory address range, for writing operands into), which is a rationale that may support a conclusion of obviousness as per MPEP 2143.
However, the combination thus far does not entail closing the aperture per a close aperture command, wherein after the aperture is closed, the multiple processing units are not permitted to write into the aperture. The combination thus far also does not entail that the aforementioned open aperture command specifies an input data type for the aforementioned partial results written into the aperture and an output data type for the aforementioned final results generated using the partial results written into the aperture.
On the other hand, Zbiciak discloses, in addition to an open command ([0198], lines 3-4, A STROPEN instruction opens a stream), closing per a close command ([0205], lines 1-2, a STRCLOSE instruction closes a stream in active state 3602), wherein after closing, not permitting data to be written from memory to be operated on ([0205], lines 7-12, a STRCLOSE instruction ends the corresponding stream immediately, allowing a program to prematurely terminate one or both streams. A STRCLOSE instruction does not stall processor 100, and does not wait for the stream to finish sending requests).
Zbiciak’s teaching allows a program to specifically state it no longer needs resources, and clears state (Zbiciak, [0207], lines 1-8), which facilitates multitasking by enabling other tasks to use those resources and increases security by preventing other tasks from seeing state. Zbiciak’s teaching also enables a known state to be reached (Zbiciak, [0206], lines 6-9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Zbiciak with the combination of Kim and Norrie in order to facilitate reuse of resources, increase security, and enable a known state to be reached. Note that Zbiciak’s teaching of an open command and a close command to respectively permit and not permit data to be written from memory to be operated on, when applied to the combination of Kim and Norrie wherein data to be operated on is written from multiple processing units to a buffer, results in the overall claimed limitation of closing the aperture per a close aperture command, wherein after the aperture is closed, the multiple processing units are not permitted to write into the aperture. Alternatively, this modification merely entails combining prior art elements (the prior art elements cited above, including an aperture, of the combination of Kim and Norrie, and Zbiciak’s teaching of an open and close command) according to known methods (Examiner submits the general concept of opening and closing to regulate data flow is known, such as opening and closing network ports) to yield predictable results (the combination of Kim and Norrie, wherein writing to an aperture is or is not permitted based on an open aperture command and a close aperture command respectively), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
However, the combination thus far does not entail that the aforementioned open aperture command specifies an input data type for the aforementioned partial results written into the aperture and an output data type for the aforementioned final results generated using the partial results written into the aperture.
On the other hand, Sprangle discloses a command specifies an input data type and an output data type (FIG. 7, which shows the command specifying an addition entailing input data type float16 and output data type F32 (float 32)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Sprangle with the combination of Kim, Norrie, and Zbiciak in order to increase processor capability by supporting different data types. Alternatively, this modification merely entails combining prior art elements (the cited prior art elements of Kim, Norrie, and Zbiciak, including an open aperture command, an aperture, partial results, and final results generated using the partial results, and Sprangle’s teaching of a command specifying an input data type and an output data type) according to known methods (Examiner submits that the concept of an input data type and an output data type was known to one of ordinary skill in the art before the effective filing date of the claimed invention) to yield predictable results (the combination of Kim, Norrie, and Zbiciak, wherein the open aperture command specifies an input data type for partial results written into the aperture and an output data type for final results generated using the partial results written into the aperture), which is a rationale that may support a conclusion of obviousness as per MPEP 2143.
Consider claim 20, the overall combination entails the non-transitory computer-readable medium of claim 19 (see above), wherein the aperture comprises a memory address into which the partial results are written (Kim, [0023], lines 20-25, in one embodiment, the memory controller manages the partial results by storing them in a buffer before reducing the partial results to a combined result, such as a summation of the partial results, product of the partial results, or other operation; Norrie, [0079], lines 14-17, the address locations in memory cells of the shared memory 104 can be used to write (store) results of computes that occur at different components of system 100; [0080], lines 1-5, the system 100 includes an operator/accumulator unit 320 (“operator 320”) that is (or can be) coupled to the shared memory 104. The operator 320 is configured to accumulate values based on one or more arithmetic operations).
Consider claim 22, the combination thus far entails the non-transitory computer-readable medium of claim 19 (see above), wherein the open aperture command specifies an address of an output buffer (Kim, [0022], lines 3-15, at operation 401, a task is detected that will use multiple processing elements to compute a number of partial results that will be reduced into a combined result. In one embodiment, the task is indicated by a particular type of instruction within a program being executed by a processing system in which one embodiment is used. In another embodiment, the task is detected by an access by an instruction to a particular memory range, in which a data structure is stored, that is designated to be associated with tasks that will use multiple processing elements to generate a number of partial results, which will then be reduced to a combined result before being stored to the data structure. In other embodiments, the task may be indicated in other ways; also see Sprangle, e.g., the destination argument 84, 0b1000, in FIG. 8) and an operator ([0022], lines 3-15, at operation 401, a task is detected that will use multiple processing elements to compute a number of partial results that will be reduced into a combined result. In one embodiment, the task is indicated by a particular type of instruction within a program being executed by a processing system in which one embodiment is used. In another embodiment, the task is detected by an access by an instruction to a particular memory range, in which a data structure is stored, that is designated to be associated with tasks that will use multiple processing elements to generate a number of partial results, which will then be reduced to a combined result before being stored to the data structure. In other embodiments, the task may be indicated in other ways; [0019], lines 5-13, in one embodiment, the shared memory and/or main memory contains a data structure 317 that will store a final result of a combined set of calculations from each of the processing elements. For example, in one embodiment, the data structure will contain a sum of a plurality of numbers computed by each of the processing elements, whereas in other embodiments, the data structure may contain a product, or some other mathematical reduction of numbers computed by each of the processing elements; also see Sprangle, opcode 172 in FIG. 7).
Claim(s) 3, 12, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, Norrie, Zbiciak, and Sprangle as applied to claims 1, 10 and 19 above, and further in view of Park (US 20180315153 A1).
Consider claim 3, the combination thus far discloses the method of claim 1 (see above), but does not disclose receiving a first portion of the partial results occurs concurrently with processing a second portion of the partial results.
On the other hand, Park discloses receiving a first portion of partial results occurs concurrently with processing a second portion of the partial results ([0139], lines 1-22, the execution clusters 810 and 812 are programmable circuits that performs computation operations. For this purpose, the execution clusters 810 and 812 may include the multiplier circuits FE0 through FEN, a compressor 1010 and a multi-cycle accumulator 1014. Each of the multiplier circuits FE0 through FEN may store a pixel value in the read data 1008 and a corresponding filter element value in the kernel memory 808. The pixel value and the corresponding filter element value are multiplied in the multiplier circuit to generate a multiplied value 1009. In some embodiments, the compressor 1010 receives the multiplied values 1009 and accumulates subsets of multiplied values 1009 to generate compressed values 1012. In other embodiments, instead of accumulating the subsets of multiplied values 1009, the compressor 1010 may select (i) a minimum value, (ii) a maximum value, or (iii) a median value from each subset of multiplied values 1009. The multi-cycle accumulator 1014 receives the compressed values 1012 and performs accumulation (or selection of a minimum value, a maximum value or a media value) on the compressed values 1012 generated across multiple processing cycles of the convolution core 802).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Park with the combination of Kim, Norrie, Zbiciak, and Sprangle in order to increase system performance via concurrency. Alternatively, this modification merely entails combining prior art elements (the cited prior art elements of Kim, Norrie, Zbiciak, and Sprangle, as well as Kim’s disclosure that in one embodiment, each processing element may return its respective partial result as soon as it has been computed rather than waiting for other processing elements to complete their respective computations, in [0023], lines 14-17, and the accumulation across multiple processing cycles as disclosed by Park) according to known methods (Examiner submits that the concept of performing a running calculation was known to one of ordinary skill in the art before the effective filing date of the claimed invention) to yield predictable results (the combination of Kim, Norrie, Zbiciak, and Sprangle, wherein receiving a first portion of the partial results occurs concurrently with processing a second portion of the partial results), which is a rationale that may support a conclusion of obviousness as per MPEP 2143.
Consider claim 12, the combination thus far discloses the system of claim 10 (see above), but does not disclose receiving a first portion of the partial results occurs at least partially concurrently with processing a second portion of the partial results.
On the other hand, Park discloses receiving a first portion of partial results occurs at least partially concurrently with processing a second portion of the partial results ([0139], lines 1-22, the execution clusters 810 and 812 are programmable circuits that performs computation operations. For this purpose, the execution clusters 810 and 812 may include the multiplier circuits FE0 through FEN, a compressor 1010 and a multi-cycle accumulator 1014. Each of the multiplier circuits FE0 through FEN may store a pixel value in the read data 1008 and a corresponding filter element value in the kernel memory 808. The pixel value and the corresponding filter element value are multiplied in the multiplier circuit to generate a multiplied value 1009. In some embodiments, the compressor 1010 receives the multiplied values 1009 and accumulates subsets of multiplied values 1009 to generate compressed values 1012. In other embodiments, instead of accumulating the subsets of multiplied values 1009, the compressor 1010 may select (i) a minimum value, (ii) a maximum value, or (iii) a median value from each subset of multiplied values 1009. The multi-cycle accumulator 1014 receives the compressed values 1012 and performs accumulation (or selection of a minimum value, a maximum value or a media value) on the compressed values 1012 generated across multiple processing cycles of the convolution core 802).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Park with the combination of Kim, Norrie, Zbiciak, and Sprangle in order to increase system performance via concurrency. Alternatively, this modification merely entails combining prior art elements (the cited prior art elements of Kim, Norrie, Zbiciak, and Sprangle, as well as Kim’s disclosure that in one embodiment, each processing element may return its respective partial result as soon as it has been computed rather than waiting for other processing elements to complete their respective computations, in [0023], lines 14-17, and the accumulation across multiple processing cycles as disclosed by Park) according to known methods (Examiner submits that the concept of performing a running calculation was known to one of ordinary skill in the art before the effective filing date of the claimed invention) to yield predictable results (the combination of Kim, Norrie, Zbiciak, and Sprangle, wherein receiving a first portion of the partial results occurs at least partially concurrently with processing a second portion of the partial results), which is a rationale that may support a conclusion of obviousness as per MPEP 2143.
Consider claim 21, the combination thus far discloses the non-transitory computer-readable medium of claim 19 (see above), but does not disclose receiving a first portion of the partial results occurs at least partially concurrently with processing a second portion of the partial results.
On the other hand, Park discloses receiving a first portion of partial results occurs at least partially concurrently with processing a second portion of the partial results ([0139], lines 1-22, the execution clusters 810 and 812 are programmable circuits that performs computation operations. For this purpose, the execution clusters 810 and 812 may include the multiplier circuits FE0 through FEN, a compressor 1010 and a multi-cycle accumulator 1014. Each of the multiplier circuits FE0 through FEN may store a pixel value in the read data 1008 and a corresponding filter element value in the kernel memory 808. The pixel value and the corresponding filter element value are multiplied in the multiplier circuit to generate a multiplied value 1009. In some embodiments, the compressor 1010 receives the multiplied values 1009 and accumulates subsets of multiplied values 1009 to generate compressed values 1012. In other embodiments, instead of accumulating the subsets of multiplied values 1009, the compressor 1010 may select (i) a minimum value, (ii) a maximum value, or (iii) a median value from each subset of multiplied values 1009. The multi-cycle accumulator 1014 receives the compressed values 1012 and performs accumulation (or selection of a minimum value, a maximum value or a media value) on the compressed values 1012 generated across multiple processing cycles of the convolution core 802).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Park with the combination of Kim, Norrie, Zbiciak, and Sprangle in order to increase system performance via concurrency. Alternatively, this modification merely entails combining prior art elements (the cited prior art elements of Kim, Norrie, Zbiciak, and Sprangle, as well as Kim’s disclosure that in one embodiment, each processing element may return its respective partial result as soon as it has been computed rather than waiting for other processing elements to complete their respective computations, in [0023], lines 14-17, and the accumulation across multiple processing cycles as disclosed by Park) according to known methods (Examiner submits that the concept of performing a running calculation was known to one of ordinary skill in the art before the effective filing date of the claimed invention) to yield predictable results (the combination of Kim, Norrie, Zbiciak, and Sprangle, wherein receiving a first portion of the partial results occurs at least partially concurrently with processing a second portion of the partial results), which is a rationale that may support a conclusion of obviousness as per MPEP 2143.
Response to Arguments
Applicant on page 7 argues: ‘Claims 4-8 and 13-17 stand rejected under 35 U.S.C. 112, 2nd paragraph. In particular, claims 4 and 13 were rejected as reciting "an open aperture command," which is also recited in claims 1 and 10. In response, claims 4 and 13 have been canceled. Claims 4 and 13 stand rejected under 35 U.S.C. 112, 4th paragraph. In response, these claims have been canceled. Applicants request withdrawal of the above rejections as the claims they applied to have been canceled.’
In view of the aforementioned claim cancellations, the previously presented rejections under 35 U.S.C. 112 are withdrawn.
Applicant on page 8 argues: “Claims 1, 10, and 19 have been amended to recite that the open aperture command specifies an input data type for partial results written into the aperture and an output data type for final results generated using the partial results written into the aperture. Support for the amendments can be found at least at paragraph [0023] of the Specification. Applicants submit that the cited references do not teach or suggest these features.”
In view of the aforementioned amendments to the independent claims, Examiner is incorporating the Sprangle reference into the rejections of claims 1, 10, and 19 — see the Claim Rejections - 35 USC § 103 section above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KEITH E VICARY/ Primary Examiner, Art Unit 2183
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