Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I, Subspecies C, Subspecies X1 for examination on which claims 1-7, 9-17, 19, and 20 are readable, in the reply filed on 03/25/2026 is acknowledged.
Claims 8, 18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/25/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 9, 11, 14, 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 20190131273 A1; hereinafter “Chen”).
In re claim 1, Chen discloses in fig. 12, a semiconductor package, comprising:
a redistribution substrate RDL1 (¶14);
a bridge chip (bridge chip comprising bridge die 150, RDL2, passive devices 100, 200, encapsulation layer E1 and other connecting structures in the encapsulation layer E1; hereinafter “Bridge”) on the redistribution substrate RDL1 (¶65, 66, 70);
a first conductive post (TIV on the left of the interposer 150; hereinafter “TIV1”) and a second conductive post (TIV on the right of the interposer 150; hereinafter “TIV2”) on the redistribution substrate RDL1 and spaced apart from the bridge chip 150 (¶16);
a first semiconductor chip 300 on the bridge chip 150 and the first conductive post TIV1 (¶25);
a second semiconductor chip 400 on the bridge chip and the second conductive post TIV2 (¶25-26); and
a first mold layer E2, UF on the redistribution substrate RDL1, the bridge chip 150, the first semiconductor chip 300, and the second semiconductor chip 400 (¶22, 30-31),
wherein the bridge chip 150 comprises:
a bridge die 150 connected to an active surface of the first semiconductor chip 300a and an active surface of the second semiconductor chip 400a (¶25-26);
a second mold layer E1, 106 on the bridge die 150 (¶22, 70);
a penetration via (TIV, 108) adjacent to the bridge die 150 and vertically penetrating the second mold layer E1; and
a capacitor 100 disposed a bottom surface of the second mold layer E1 (as best understood, a capacitor 100 disposed on a bottom surface of the second mold layer) and connected to the penetration via (TIV, 108) (¶20).
In re claim 3, Chen discloses in fig. 12, the semiconductor package of claim 1,
wherein the first mold layer comprises:
a first sub-mold layer UF on the redistribution substrate RDL1, the first conductive post TIV1, the second conductive post TIV2, and the bridge chip Bridge; and
a second sub-mold layer E2 on the first sub-mold layer UF, the first semiconductor chip 300, and the second semiconductor chip 400.
In re claim 9, Chen discloses in fig. 12, the semiconductor package of claim 1,
wherein the bridge chip (Bridge) directly contacts a top surface of the redistribution substrate RDL1, and
wherein a conductive pattern 104 (¶15) of the redistribution substrate is connected to the capacitor of the bridge chip (Bridge).
In re claim 11, Chen discloses in fig. 12, a semiconductor package, comprising:
a redistribution substrate RDL1 (¶14);
a bridge chip (bridge chip comprising bridge die 150, RDL2, passive devices 100, 200, encapsulation layer E1; hereinafter “Bridge”) on the redistribution substrate RDL1 (¶65, 66, 70);
a first semiconductor chip 300 and a second semiconductor chip 400 on the bridge chip Bridge (¶25-26),
each of the first semiconductor chip 300 and the second semiconductor chip 400 being shifted from the bridge chip Bridge horizontally such that a portion of an active surface of the bridge chip Bridge is exposed (e.g., a middle portion of the bridge chip exposed which is in between the first and second semiconductor chips 300, 400); and
vertical connection terminals TIV1, TIV2 (e.g., the fan-out via TIV in between 100 and 150 has been interpreted as TIV1 and the second rightmost TIV has been interpreted as TIV2) horizontally spaced apart from the bridge chip Bridge and connecting the first semiconductor chip 300 (TIV1 connects the first semiconductor chip 300 through the semiconductor chip 100) and the second semiconductor chip 400 to the redistribution substrate RDL1 (¶16),
wherein the bridge chip comprises:
a redistribution layer RDL2 on an active surface of the first semiconductor chip 300a and an active surface of the second semiconductor chip 400a (¶49);
a bridge die 150 on a bottom surface of the redistribution layer RDL2 (¶65-66);
a first mold layer E1 on the bottom surface of the redistribution layer RDL2 and the bridge die 150 (¶70);
a capacitor 100 on a bottom surface of the first mold layer E1 (¶20-21); and
a penetration via 100d vertically penetrating the first mold layer E1 and connecting the redistribution layer RDL2 to the capacitor 100 (¶18).
In re claim 14, Chen discloses in fig. 12, the semiconductor package of claim 11, further comprising:
a second mold layer UF on the redistribution substrate RDL1, the bridge chip bridge (¶30); and
a third mold layer E2 on the second mold layer UF, the first semiconductor chip 300 and the second semiconductor chip 400 (¶31).
In re claim 19, Chen discloses in fig. 12, the semiconductor package of claim 11, wherein the bridge chip Bridge directly contacts a top surface of the redistribution substrate RDL1, and wherein a conductive pattern of the redistribution substrate 104 is connected (e.g., electrically connected) to the capacitor 100 of the bridge chip (¶33).
Claim(s) 1, 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 20190131273 A1; hereinafter “Chen”), in an alternative interpretation.
In re claim 1, Chen discloses in fig. 12, a semiconductor package, comprising:
a redistribution substrate RDL1 (¶14);
a bridge chip (bridge chip comprising bridge die 150, RDL2, passive devices 100, 200, encapsulation layer E1 and other connecting structures in the encapsulation layer E1; hereinafter “Bridge”) on the redistribution substrate RDL1 (¶65, 66, 70);
a first conductive post (TIV on the left of the interposer 150; hereinafter “TIV1”) and a second conductive post (TIV on the right of the interposer 150; hereinafter “TIV2”) on the redistribution substrate RDL1 and spaced apart from the bridge chip 150 (¶16);
a first semiconductor chip 300 on the bridge chip 150 and the first conductive post TIV1 (¶25);
a second semiconductor chip 400 on the bridge chip and the second conductive post TIV2 (¶25-26); and
a first mold layer E2, UF on the redistribution substrate RDL1, the bridge chip 150, the first semiconductor chip 300, and the second semiconductor chip 400 (¶22, 30-31),
wherein the bridge chip 150 comprises:
a bridge die 150 connected to an active surface of the first semiconductor chip 300a and an active surface of the second semiconductor chip 400a (¶25-26);
a second mold layer E1 on the bridge die 150 (¶70);
a penetration via (TIV, 100b, 100d) adjacent to the bridge die 150 and vertically penetrating the second mold layer E1; and
a capacitor 100 disposed a bottom surface of the second mold layer E1 (as best understood, a capacitor 100 disposed on a bottom surface of the second mold layer) and connected to the penetration via (TIV, 100b, 100d) (¶20).
In re claim 10, Chen discloses in fig. 12, the semiconductor package of claim 1,
wherein the bridge chip further comprises a redistribution layer RDL2 on the bridge die 150 and the second mold layer E1,
wherein the redistribution layer RDL2 is connected to the bridge die 150 and the penetration via (TIV, 100b, 100d), and
wherein the first semiconductor chip 300 and the second semiconductor chip 400 are electrically connected to the redistribution layer RDL2 of the bridge chip.
Claim(s) 1, 3, 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 20190131273 A1; hereinafter “Chen”), in an alternative interpretation of the first and second mold layers.
In re claim 1, Chen discloses in fig. 12, a semiconductor package, comprising:
a redistribution substrate RDL1 (¶14);
a bridge chip (bridge chip comprising bridge die 150 and connectors above it; hereinafter “Bridge”) on the redistribution substrate RDL1 (¶65, 66, 70);
a first conductive post (TIV on the left of the interposer 150; hereinafter “TIV1”) and a second conductive post (TIV on the right of the interposer 150; hereinafter “TIV2”) on the redistribution substrate RDL1 and spaced apart from the bridge chip 150 (¶16);
a first semiconductor chip 300 on the bridge chip 150 and the first conductive post TIV1 (¶25);
a second semiconductor chip 400 on the bridge chip and the second conductive post TIV2 (¶25-26); and
a first mold layer E1, E2 on the redistribution substrate RDL1, the bridge chip 150, the first semiconductor chip 300, and the second semiconductor chip 400 (¶22, 30-31),
wherein the bridge chip Bridge comprises: a bridge die 150 connected to an active surface of the first semiconductor chip 300a and an active surface of the second semiconductor chip 400a (¶25-26);
a second mold layer 106 on the bridge die 150 (¶22);
a penetration via 108 adjacent to the bridge die 150 and vertically penetrating the second mold layer 106 (¶22); and
a capacitor 200 disposed a bottom surface of the second mold layer 106 (as best understood, a capacitor 200 disposed on a bottom surface of the second mold layer) and connected to the penetration via 108 (¶20).
In re claim 3, Chen discloses in fig. 12, the semiconductor package of claim 1,
wherein the first mold layer E1, E2 comprises:
a first sub-mold layer E1 on the redistribution substrate RDL1, the first conductive post TIV1, the second conductive post TIV2, and the bridge chip Bridge; and
a second sub-mold layer E2 on the first sub-mold layer E1, the first semiconductor chip 300, and the second semiconductor chip 400.
In re claim 7, Chen discloses in fig. 12, the semiconductor package of claim 3, wherein a top surface of the first sub- mold layer E1 is coplanar with a top surface of the first conductive post TIV1, a top surface of the second conductive post TIV2, and a top surface of the bridge chip Bridge.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 12, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view Pietambaram et al. (US 20230197697 A1; hereinafter “Pietambaram”).
In re claim 2, Chen discloses the semiconductor package of claim 1 outlined above.
Chen does not expressly disclose wherein the capacitor comprises:
a first electrode on the bottom surface of the second mold layer;
a second electrode vertically spaced apart from the first electrode; and
a high-k dielectric layer between the first electrode and the second electrode.
In the same field of endeavor, Pietambaram discloses in figs. 1A-1B, wherein a capacitor 190 comprises (¶20-22):
a first electrode 196 on a bottom surface of a second mold layer 133-1;
a second electrode 198 vertically spaced apart from the first electrode 196; and
a high-k dielectric layer 135 between the first electrode 196 and the second electrode 198.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form the capacitor of Chen as having claimed structure to achieve a high capacitance density (¶21 of Pietambaram).
In re claim 12, Chen discloses in fig. 12, the semiconductor package of claim 11, wherein the vertical connection terminals TIV comprise:
second posts TIV2 adjacent to a second side of the bridge chip Bridge and connecting the redistribution substrate RDL1 to the second semiconductor chip 400.
Chen does not expressly disclose first posts adjacent to a first side of the bridge chip and connecting the redistribution substrate to the first semiconductor chip.
In the same field of endeavor, Pietambaram discloses in figs. 1A-1B, wherein first posts 192, 152 adjacent to a first side of a bridge chip 114-2 and connecting a redistribution substrate (102, 127, 146, 150, 144) to a first semiconductor chip 114-3 (¶20-24).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Pietambaram into the package of Chen to establish connection of the upper semiconductor chip with the lower substrate forming a larger multi-tier circuit and accommodate various functions like power delivery interconnects or high-speed signal interconnects (¶24 of Pietambaram).
In re claim 17, Chen discloses the semiconductor package of claim 11 outlined above.
Chen does not expressly disclose wherein the capacitor comprises:
a first electrode on the bottom surface of the first mold layer;
a second electrode vertically spaced apart from the first electrode; and
a high-k dielectric layer between the first electrode and the second electrode.
In the same field of endeavor, Pietambaram discloses in figs. 1A-1B, wherein a capacitor 190 comprises (¶20-22):
a first electrode 196 on a bottom surface of a first mold layer 133-1;
a second electrode 198 vertically spaced apart from the first electrode 196; and
a high-k dielectric layer 135 between the first electrode 196 and the second electrode 198.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form the capacitor of Chen as having claimed structure to achieve a high capacitance density (¶21 of Pietambaram).
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view Duan et al. (US 20240222219 A1; hereinafter “Duan”).
In re claim 4, Chen discloses in fig. 12, the semiconductor package of claim 3,
wherein the first semiconductor chip 300 comprises a first sub-post (the connecting structure 300b, 300d, 300e shown in the annotated figure below) (hereinafter “SubPost1”) and a second sub-post (the connecting structure 300b, 300d, 300e shown in the annotated figure below) (hereinafter “SubPost2”),
the first sub-post SubPost1 and the second sub-post SubPost2 being on the active surface of the first semiconductor chip 300a,
wherein the second semiconductor chip 400 comprises a third sub-post (the connecting structure 400b, 400d, 400e shown in the annotated figure below) (hereinafter “SubPost3”) and a fourth sub- post (the connecting structure 400b, 400d, 400e shown in the annotated figure below) (hereinafter “SubPost4”),
the third sub-post SubPost3 and the fourth sub-post SubPost4 being on the active surface of the second semiconductor chip 400a,
wherein the second sub-post SubPost2 connects (e.g., electrically connects) the bridge die 150 of the bridge chip to the first semiconductor chip 300,
wherein the third sub-post SubPost3 connects (e.g., electrically connects) the second conductive post TIV2 to the second semiconductor chip 400, and
wherein the fourth sub-post SubPost4 connects (e.g., electrically connects) the bridge die 150 of the bridge chip to the second semiconductor chip 400.
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Chen does not expressly disclose wherein the first sub-post SubPost1 connects the first conductive post to the first semiconductor chip.
In the same field of endeavor, Duan discloses in fig. 1B, wherein a first sub-post (a first interconnect structure 106 underneath chip 104a) connects a first conductive post 112 to a first semiconductor chip 104a (¶38).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Duan into the package of Chen to establish connection of the upper semiconductor chip with the lower substrate forming a larger circuit (¶17 of Duan).
In re claim 5, Chen, as modified by Duan, discloses the semiconductor package of claim 4 outlined above.
Chen further discloses in fig. 12, the semiconductor package of claim 4,
wherein the second sub-mold layer E2 is on the first sub-post SubPost1, the second sub-post SubPost2, the third sub-post SubPost3, and the fourth sub-post SubPost4.
Chen does not expressly disclose wherein a bottom surface of each of the first sub-post, the second sub-post, the third sub-post, and fourth sub-post is coplanar with a bottom surface of the second sub-mold layer.
In the same field of endeavor, Duan discloses in fig. 1B, wherein a bottom surface of each of the first sub-post (a first interconnect structure 106 underneath chip 104a), a second sub-post (a second interconnect structure 106 underneath chip 104a), a third sub-post (a first interconnect structure 106 underneath chip 104b), and a fourth sub-post (a second interconnect structure 106 underneath chip 104b) is coplanar with a bottom surface (e.g., at the A-A’ interface or 142) of a second sub-mold layer 108 (¶35, 38).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to make the first to fourth sub-posts of Chen coplanar with the bottom surface of the second sub-mold layer to bond the upper package with the lower package including the bridge chip with reduce process complexity (¶1-3 of Duan).
In re claim 6, Chen, as modified by Duan, discloses the semiconductor package of claim 4 outlined above.
Chen further discloses in fig. 12, the semiconductor package of claim 4, wherein the penetration via (TIV, 108) and a conductive pattern of the bridge die (e.g., a conductive pattern comprising a connecting pillar above 150 and 108) directly contact the second sub-post SubPost2 and the fourth sub- post SubPost4 (see fig. 12 annotated above in claim 4).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view Marin et al. (US 20240105655 A1; hereinafter “Marin”).
In re claim 13, Chen discloses the semiconductor package of claim 11 outlined above.
Chen does not expressly disclose the semiconductor package further comprising
a connection substrate on the redistribution substrate,
wherein the connection substrate comprises an opening,
wherein the bridge chip is in the opening of the connection substrate, and
wherein the vertical connection terminals comprise conductive patterns in the connection substrate.
In the same field of endeavor, Marin discloses in fig. 1, a semiconductor package, comprising
a connection substrate 107 (¶21) on a redistribution substrate 127, 150, 144, 146 (¶32, 34),
wherein the connection substrate 107 comprises an opening 119 (¶21),
wherein a bridge chip 114-1 is in the opening of the connection substrate 119 (¶21), and
wherein vertical connection terminals comprise conductive patterns 108 in the connection substrate 107 (¶21).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Marin into the package of Chen and form the bridge die in a cavity formed in a connection substrate to help reduce the cost and complexity associated with assembling multi-die IC packages relative to conventional approaches by incorporating double-sided embedded dies with through-silicon vias (TSVs) that enable power signals to be routed through the embedded dies (¶14-15 of Marin).
Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view Duan et al. (US 20240222219 A1; hereinafter “Duan”).
In re claim 15, Chen discloses in fig. 12, the semiconductor package of claim 14,
wherein the first semiconductor chip 300 comprises a first sub-post (the connecting structure 300b, 300d, 300e shown in the annotated figure below) (hereinafter “SubPost1”) and a second sub-post (the connecting structure 300b, 300d, 300e shown in the annotated figure below) (hereinafter “SubPost2”),
the first sub-post SubPost1 and the second sub-post SubPost2 being on the active surface of the first semiconductor chip 300a,
wherein the second semiconductor chip 400 comprises a third sub-post (the connecting structure 400b, 400d, 400e shown in the annotated figure below) (hereinafter “SubPost3”) and a fourth sub- post (the connecting structure 400b, 400d, 400e shown in the annotated figure below) (hereinafter “SubPost4”),
the third sub-post SubPost3 and the fourth sub-post SubPost4 being on the active surface of the second semiconductor chip 400a,
wherein the second sub-post SubPost2 connects (e.g., electrically connects) the bridge die 150 of the bridge chip to the first semiconductor chip 300,
wherein the third sub-post SubPost3 connects (e.g., electrically connects) the second conductive post TIV2 to the second semiconductor chip 400, and
wherein the fourth sub-post SubPost4 connects (e.g., electrically connects) the bridge die 150 of the bridge chip to the second semiconductor chip 400.
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Chen does not expressly disclose wherein the first sub-post SubPost1 connects the first conductive post to the first semiconductor chip.
In the same field of endeavor, Duan discloses in fig. 1B, wherein a first sub-post (a first interconnect structure 106 underneath chip 104a) connects a first conductive post 112 to a first semiconductor chip 104a (¶38).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Duan into the package of Chen to establish connection of the upper semiconductor chip with the lower substrate forming a larger circuit (¶17 of Duan).
Chen does not expressly disclose wherein a bottom surface of each of the first sub-post, the second sub-post, the third sub-post, and fourth sub-post is coplanar with a bottom surface of the third sub-mold layer.
In the same field of endeavor, Duan discloses in fig. 1B, wherein a bottom surface of each of the first sub-post (a first interconnect structure 106 underneath chip 104a), a second sub-post (a second interconnect structure 106 underneath chip 104a), a third sub-post (a first interconnect structure 106 underneath chip 104b), and a fourth sub-post (a second interconnect structure 106 underneath chip 104b) is coplanar with a bottom surface (e.g., at the A-A’ interface or 142) of a third sub-mold layer 108 (¶35, 38).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to make the first to fourth sub-posts of Chen coplanar with the bottom surface of the second sub-mold layer to bond the upper package with the lower package including the bridge chip with reduce process complexity (¶1-3 of Duan).
In re claim 16, Chen discloses in fig. 12, the semiconductor package of claim 15, wherein a conductive pattern of the bridge die (e.g., a conductive pattern comprising a connecting pillar above 150 and 108) directly contacts the second sub-post SubPost2 and the fourth sub- post SubPost4 (see fig. 12 annotated above in claim 15).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view Elsherbini et al. (US 20210111156 A1; hereinafter “Elsherbini”).
In re claim 20, Chen discloses in fig. 12, a semiconductor package, comprising:
a first semiconductor chip 300 and a second semiconductor chip 400 horizontally spaced apart from each other (¶25-26);
first sub-posts (the connecting structures 300b, 300d, 300e shown in the annotated figure below) (hereinafter “SubPost1”) on a top surface of the first semiconductor chip 300 and connected to the first semiconductor chip 300 (¶25);
second sub-posts (the connecting structures 400b, 400d, 400e shown in the annotated figure below) (hereinafter “SubPost2”) on a top surface of the second semiconductor chip 400 and connected to the second semiconductor chip 400 (¶26);
a first mold layer E2 on the first semiconductor chip 300, the second semiconductor chip 400, the first sub-posts SubPost1, and the second sub-posts SubPost2 (¶31);
a bridge chip (bridge chip comprising bridge die 150; hereinafter “Bridge”) on the first mold layer E1, a portion of the first sub-posts, and a portion of the second sub-posts (e.g., the bridge chip is on the lower surfaces of the first mold layer E1, a portion of the first sub-posts SubPost1, and a portion of the second sub-posts SubPost2);
a second mold layer E1 on the first mold layer E2 (a second mold layer E1 on the lower surface of the first mold layer E2) and the bridge chip 150;
a redistribution substrate RDL2 on the second mold layer E1 and the bridge chip 150 (¶64-66);
first posts TIV vertically penetrating the second mold layer E1 and connecting a remaining portion of the first sub-posts to the redistribution substrate; and
second posts TIV vertically penetrating the second mold layer E1 and connecting a remaining portion of the second sub-posts SubPost2 to the redistribution substrate RDL1,
wherein the bridge chip comprises:
a bridge die 150 connected to a portion of the first sub-posts SubPost1 and a portion of the second sub-posts SubPost2;
a capacitor 100 adjacent to the bridge die 150; and
a penetration via (TIV, 100b, 100d) vertically connected to the capacitor 100 and adjacent to the bridge die 150.
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Chen does not expressly disclose first posts connecting a remaining portion of the first sub-posts to the redistribution substrate; and a capacitor on to the bridge die.
In the same field of endeavor, Elsherbini discloses in fig. 1, a semiconductor package 100, wherein first posts 152 connecting a remaining portion of first sub-posts 122, 130-1 to a redistribution substrate 127 (¶24, 35); and a capacitor 114-1 on a bridge die 114-2 (¶24, 29).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Ecton into the package of Chen and form the bridge die in a cavity formed in a connection substrate to help reduce the cost and complexity associated with assembling multi-die IC packages relative to conventional approaches by incorporating double-sided embedded dies with through-silicon vias (TSVs) that enable power signals to be routed through the embedded dies and also to integrate features or functionality and to facilitate connections to other components, such as package substrates (¶1, 14 of Ecton).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893
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