DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (Claims 1-8) in the reply filed on 04/15/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 2 recite “a first dielectric layer, located between the source conductor and an inner surface of the trench, configured to isolate from the source conductor and the inner surface of the trench;”
It is not clear from what a first dielectric layer is configured to isolate the source conductor and the inner surface of the trench.
For the purposes of examination the Examiner will treat “a first dielectric layer, located between the source conductor and an inner surface of the trench, configured to isolate from the source conductor and the inner surface of the trench;” as --configured to isolate the source conductor from the inner surface of the trench--
Further, claims 1 and 2 recite
“a gate dielectric layer, located between the gate conductor and the inner surface of the trench, configured to isolate from the gate conductor and the inner surface of the trench;”
It is not clear from what a gate dielectric layer is configured to isolate the gate conductor and the inner surface of the trench.
For the purposes of examination, the Examiner will treat “a gate dielectric layer, located between the gate conductor and the inner surface of the trench, configured to isolate from the gate conductor and the inner surface of the trench;” as --configured to isolate the gate conductor from the inner surface of the trench --.
Claims 3-8 are rejected as being dependent on Claim 1.
Claim 2 recite “ an isolation dielectric layer, located between the source conductor and the gate conductor, configured to isolate from the source conductor and the gate conductor”.
It is not clear from what an isolation dielectric layer is configured to isolate the source conductor and the gate conductor.
For the purposes of examination, the Examiner will treat “an isolation dielectric layer, located between the source conductor and the gate conductor, configured to isolate from the source conductor and the gate conductor” as - configured to isolate the source conductor from the gate conductor --.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102(A2) as being anticipated by Li et al. (CN 115528090 A, filed 09/25/2022).
Regarding Claim 1, Li (Fig. 1) discloses a gate-source structure of an asymmetric trench metal oxide semiconductor field effect transistor (MOSFET), comprising:
a substrate (10) of a first doping type (n);
an epitaxial layer (9) of the first doping type (n) on the substrate (10);
a current spreading layer (portion of 7) of the first doping type (n) in the epitaxial layer (9);
a trench (trench region) extending from a surface to an inside of the current spreading layer (7);
a source conductor (6) located in the trench;
a first dielectric layer (13), located between the source conductor (6) and an inner surface of the trench (trench region), configured to isolate from the source conductor (6) and the inner surface of the trench (trench region);
a gate conductor (3) located in the trench (trench region);
an isolation dielectric layer (12), located between the source conductor (6) and the gate conductor (3), configured to isolate from the source conductor (6) and the gate conductor (3);
a gate dielectric layer (12), located between the gate conductor (3) and the inner surface of the trench (trench region), configured to isolate from the gate conductor (3) and the inner surface of the trench (trench region); (“the polysilicon region 3 surrounded by the thick gate oxide layer 12”). The Examiner notes that gate 3 must be isolated from 7, 4 and 2 for the MOSFET to operate.
wherein:
the source conductor includes:
a first portion (vertical portion of 6) opposite to a side of the gate conductor (3); and
a second portion (horizontal portion of 6) opposite to a bottom of the gate conductor (3); and
the first portion and the second portion are perpendicular and connected to each other. (See Fig. 1).
PNG
media_image1.png
1128
768
media_image1.png
Greyscale
Regarding Claim 2, Li (Fig. 1) discloses an asymmetric trench metal oxide semiconductor field effect transistor (MOSFET), comprising:
a substrate (10) of a first doping type (n);
an epitaxial layer (9) of the first doping type (n) on the substrate (9);
a current spreading layer (7) of the first doping type (n) in the epitaxial layer (9);
a trench (trench region) extending from a surface to an inside of the current spreading layer (7);
a source conductor (6) located in the trench (trench region);
a first dielectric layer (13), located between the source conductor (6) and an inner surface of the trench (trench region), configured to isolate from the source conductor (6) and the inner surface of the trench (trench region);
a gate conductor (3) located in the trench (trench region);
an isolation dielectric layer (12), located between the source conductor (trench region) and the gate conductor (3), configured to isolate from the source conductor (6) and the gate conductor (3);
a gate dielectric layer (12), located between the gate conductor (3) and the inner surface of the trench (trench region), configured to isolate from the gate conductor (3) and the inner surface of the trench (trench region); (“the polysilicon region 3 surrounded by the thick gate oxide layer 12”). The Examiner notes that gate 3 must be isolated from 7, 4 and 2 for the MOSFET to operate.
a first body region (8 left) located adjacent a first sidewall of the trench;
a second body region (8 right) located adjacent a second sidewall of the trench, the first sidewall of the trench opposite to the second sidewall of the trench;
wherein:
the source conductor includes:
a first portion (vertical portion of 6) opposite to a side of the gate conductor (3); and a
second portion (bottom portion of 6) opposite to a bottom of the gate conductor (3); and
the first portion and the second portion are perpendicular and connected to each other. (See Fig. 1).
Regarding Claim 3, Li (Fig. 1) discloses the asymmetric trench MOSFET according to claim 2, wherein
the second body (See annotated Fig. 1) region comprises:
a third portion (vertical portion of 8) located adjacent the second sidewall of the trench; and
a fourth portion (horizontal portion of 8 located on a level below trench region) located below the trench; wherein
the third portion and the fourth portion are connected together to form an integration, (See Fig. 1) surrounding the second sidewall of the trench, at least a part of a bottom wall of the trench, and a corner formed by the second sidewall of the trench and the bottom wall of the trench. (See annotated Fig. 1)
Regarding Claim 4, Li (Fig. 1) discloses the asymmetric trench MOSFET according to claim 3, wherein
both the second portion and the fourth portion extend in a first direction (horizontal), and in the first direction (vertical), an end of the fourth portion away from the third portion is not excess an end of the second portion away from the first portion. (See annotated Fig. 1).
Regarding Claim 5, Li (Fig. 1) discloses the asymmetric trench MOSFET according to claim 2, further comprises:
a first doped region (1st doped region) of a second doping type (p), the first doped region located adjacent a side of the first body region (1st body region) away from the trench (trench region);
a third doped region (the N + contact region 2 left) of the first doping type (n) located in the first body region and adjacent to the trench (Fig. 1);
a fourth doped region (the N + contact region 2 right) of the first doping type (n) located in the second body region and adjacent to the trench; (Fig. 1) and
a second doped region (2nd doped region) of a second doping type (P), located in the second body region, and adjacent to a side of the fourth doped region away from the trench. (Fig. 1)
The Examiner notes that since the Applicant did not explicitly specified metes and bound of first, third and fourth doped region, the Examiner selected doped regions that satisfy claim limitations.
Regarding Claim 6, Li (Fig. 1) discloses the asymmetric trench MOSFET according to claim 5, wherein
the first doped region extends from a surface to the inside of the current spreading layer, and a depth of the first doped region in the current spreading layer is greater than a depth of the trench in the current spreading layer. (See annotated Fig. 1)
The Examiner notes that since the Applicant did not explicitly specified metes and bound of first doped region the Examiner selected a doped region that satisfies claim limitation.
Regarding Claim 7, Li (Fig. 1) discloses the asymmetric trench MOSFET according to claim 5, wherein
a bottom of the first doped region (1st doped region) is located in the current spreading layer (portion of 7) or in the epitaxial layer. (9) (See annotated Fig. 1)
Regarding Claim 8, Li (Fig. 1) discloses the asymmetric trench MOSFET according to claim 2, wherein
a bottom of the second body region (fourth region and third region) is located in the current spreading layer (section of 7) or in the epitaxial layer (9). (See annotated Fig. 1)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DMITRIY YEMELYANOV/Examiner, Art Unit 2891
Prosecution Insights