DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Non-Final Action filed on 6/17/2026 is acknowledged.
Applicant amended claims 1 and 11.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 6, 10-13, 15, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2020/0135932) (hereafter Wang), in view of Cheng et al. (US 2021/0118995) (hereafter Cheng).
Regarding claim 1, Wang discloses an integrated circuit structure, comprising:
a vertical arrangement of horizontal nanowires (element number is not shown in Fig. 12B but see 204B in Fig. 4B, paragraph 0022);
a gate stack (top layer of “high-k gate dielectric layer”, “work function metal layer”, and “bulk conductive layer” of 270 in Fig. 12B, paragraph 0043; and see paragraph 0043, wherein “The high-k dielectric layer may include one or more high-k dielectric materials (or one or more layers of high-k dielectric materials)”) over the vertical arrangement of horizontal nanowires (element number is not shown in Fig. 12B but see 204B in Fig. 4B), wherein the gate stack (top layer of “high-k gate dielectric layer”, “work function metal layer”, and “bulk conductive layer” of 270 in Fig. 12B, paragraph 0043) comprises a high-k gate dielectric layer (top layer of “high-k dielectric layer” of 270 in Fig. 12B; and see paragraph 0043, wherein “The high-k dielectric layer may include one or more high-k dielectric materials (or one or more layers of high-k dielectric materials)”) and a metal gate electrode (“work function metal layer” and “bulk conductive layer” of 270 in Fig. 12B, paragraph 0043);
a pair of dielectric spacers 264 (Fig. 12B, paragraph 0045) along sides of the gate stack (top layer of “high-k gate dielectric layer”, “work function metal layer”, and “bulk conductive layer” of 270 in Fig. 12B, paragraph 0043) and over the vertical arrangement of horizontal nanowires (element number is not shown in Fig. 12B but see 204B in Fig. 4B); and
a material (bottom layer of “high-k dielectric layer” of 270 in Fig. 12B, paragraph 0043; and see paragraph 0043, wherein “The high-k dielectric layer may include one or more high-k dielectric materials (or one or more layers of high-k dielectric materials)”) comprising metal and oxygen (see paragraph 0043, wherein “hafnium silicon oxide (HfSiO), hafnium oxide (HfO.sub.2), alumina (Al.sub.2O.sub.3), zirconium oxide (ZrO.sub.2), lanthanum oxide (La.sub.2O.sub.3), titanium oxide (TiO.sub.2), yttrium oxide (Y.sub.2O.sub.3), strontium titanate (SrTiO.sub.3), or a combination thereof”), the material (bottom layer of “high-k dielectric layer” of 270 in Fig. 12B, paragraph 0043) comprising metal and oxygen between adjacent ones of the vertical arrangement of horizontal nanowires (element number is not shown in Fig. 12B but see 204B in Fig. 4B) at a location between the pair of dielectric spacers 264 (Fig. 12B) and the sides of the gate stack (top layer of “high-k gate dielectric layer”, “work function metal layer”, and “bulk conductive layer” of 270 in Fig. 12B, paragraph 0043).
Wang does not disclose the material comprising metal and oxygen is discontinuous along the sides of the gate stack.
Cheng discloses the material 127B (Fig. 1B, paragraph 0042) comprising metal and oxygen (see paragraph 0042, wherein “a high-k dielectric material, such as hafnium oxide (HfO.sub.2), titanium oxide (TiO.sub.2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta.sub.2O.sub.3), hafnium silicate (HfSiO.sub.4), zirconium oxide (ZrO.sub.2), zirconium silicate (ZrSiO.sub.2)”) is discontinuous along the sides of the gate stack (128B, 130B, 134B, and 135B in Fig. 1B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Wang to form the material comprising metal and oxygen is discontinuous along the sides of the gate stack, as taught by Cheng, since nanostructured channel regions 120B and 122B (Cheng, Fig. 1B, paragraph 0041) can be wrapped around by at least interfacial oxide layers 127A-127B (Cheng, Fig. 1B, paragraph 0041) and gate dielectric layers 128A-128B (Cheng, Fig. 1B, paragraph 0041) to fill the spaces between adjacent nanostructured channel regions 120B and 122B (Cheng, Fig. 1B, paragraph 0041), and thus electrically isolate nanostructured channel regions 120B and 122B (Cheng, Fig. 1B, paragraph 0041) from each other.
Regarding claim 2, Wang further discloses the integrated circuit structure of claim 1, wherein the material (bottom layer of “high-k dielectric layer” of 270 in Fig. 12B, paragraph 0043; and see paragraph 0043, wherein “hafnium silicon oxide (HfSiO), hafnium oxide (HfO.sub.2), alumina (Al.sub.2O.sub.3), zirconium oxide (ZrO.sub.2), lanthanum oxide (La.sub.2O.sub.3), titanium oxide (TiO.sub.2), yttrium oxide (Y.sub.2O.sub.3), strontium titanate (SrTiO.sub.3), or a combination thereof”) comprising metal and oxygen is a material selected from the group consisting of titanium oxide (TiOx), tantalum oxide (TaOx) and aluminum oxide (AlOx).
Regarding claim 3, Wang further discloses the integrated circuit structure of claim 1, wherein the pair of dielectric spacers 264 (Fig. 12B, paragraph 0039, wherein “silicon nitride, silicon oxynitride, silicon nitride with oxygen or carbon elements, other suitable materials, or combinations thereof”) comprises a dielectric material selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxide, and carbon-doped silicon nitride.
Regarding claim 5, Wang further discloses the integrated circuit structure of claim 1, further comprising: a pair of epitaxial source (element number is not shown in Fig. 12B but see 252-254 in Fig. 12A, paragraph 0034) or drain structures at first and second ends of the vertical arrangement of horizontal nanowires (element number is not shown in Fig. 12B but see 204B in Fig. 4B).
Regarding claim 6, Wang further discloses the integrated circuit structure of claim 5, wherein the pair of epitaxial source (element number is not shown in Fig. 12B but see 252-254 in Fig. 12A, paragraph 0034) or drain structures is a pair of discrete epitaxial source or drain structures.
Regarding claim 10, Wang further discloses the integrated circuit structure of claim 1, wherein the nanowires of the vertical arrangement of horizontal nanowires (element number is not shown in Fig. 12B but see 204B in Fig. 4B, paragraph 0022) comprise silicon (see paragraph 0022,wherein “SiGe”).
Regarding claim 11, Wang discloses an integrated circuit structure, comprising:
a horizontal nanowire (element number is not shown in Fig. 12B but see 204B in Fig. 4B, paragraph 0022);
a gate stack (top layer of “high-k gate dielectric layer”, “work function metal layer”, and “bulk conductive layer” of 270 in Fig. 12B, paragraph 0043; and see paragraph 0043, wherein “The high-k dielectric layer may include one or more high-k dielectric materials (or one or more layers of high-k dielectric materials)”) over the horizontal nanowire (element number is not shown in Fig. 12B but see 204B in Fig. 4B), wherein the gate stack (top layer of “high-k gate dielectric layer”, “work function metal layer”, and “bulk conductive layer” of 270 in Fig. 12B, paragraph 0043) comprises a high-k gate dielectric layer (top layer of “high-k dielectric layer” of 270 in Fig. 12B; and see paragraph 0043, wherein “The high-k dielectric layer may include one or more high-k dielectric materials (or one or more layers of high-k dielectric materials)”) and a metal gate electrode (“work function metal layer” and “bulk conductive layer” of 270 in Fig. 12B, paragraph 0043);
a pair of dielectric spacers 264 (Fig. 12B, paragraph 0045) along sides of the gate stack (top layer of “high-k gate dielectric layer”, “work function metal layer”, and “bulk conductive layer” of 270 in Fig. 12B, paragraph 0043) and over the horizontal nanowire (element number is not shown in Fig. 12B but see 204B in Fig. 4B); and
a material (bottom layer of “high-k dielectric layer” of 270 in Fig. 12B, paragraph 0043; and see paragraph 0043, wherein “The high-k dielectric layer may include one or more high-k dielectric materials (or one or more layers of high-k dielectric materials)”) comprising metal and oxygen, the material (see paragraph 0043, wherein “hafnium silicon oxide (HfSiO), hafnium oxide (HfO.sub.2), alumina (Al.sub.2O.sub.3), zirconium oxide (ZrO.sub.2), lanthanum oxide (La.sub.2O.sub.3), titanium oxide (TiO.sub.2), yttrium oxide (Y.sub.2O.sub.3), strontium titanate (SrTiO.sub.3), or a combination thereof”) comprising metal and oxygen between the horizontal nanowire (element number is not shown in Fig. 12B but see 204B in Fig. 4B) at a location between the pair of dielectric spacers 264 (Fig. 12B) and the sides of the gate stack (top layer of “high-k gate dielectric layer”, “work function metal layer”, and “bulk conductive layer” of 270 in Fig. 12B, paragraph 0043).
Wang does not disclose the material comprising metal and oxygen is discontinuous along the sides of the gate stack.
Cheng discloses the material 127B (Fig. 1B, paragraph 0042) comprising metal and oxygen (see paragraph 0042, wherein “a high-k dielectric material, such as hafnium oxide (HfO.sub.2), titanium oxide (TiO.sub.2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta.sub.2O.sub.3), hafnium silicate (HfSiO.sub.4), zirconium oxide (ZrO.sub.2), zirconium silicate (ZrSiO.sub.2)”) is discontinuous along the sides of the gate stack (128B, 130B, 134B, and 135B in Fig. 1B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Wang to form the material comprising metal and oxygen is discontinuous along the sides of the gate stack, as taught by Cheng, since nanostructured channel regions 120B and 122B (Cheng, Fig. 1B, paragraph 0041) can be wrapped around by at least interfacial oxide layers 127A-127B (Cheng, Fig. 1B, paragraph 0041) and gate dielectric layers 128A-128B (Cheng, Fig. 1B, paragraph 0041) to fill the spaces between adjacent nanostructured channel regions 120B and 122B (Cheng, Fig. 1B, paragraph 0041), and thus electrically isolate nanostructured channel regions 120B and 122B (Cheng, Fig. 1B, paragraph 0041) from each other.
Regarding claim 12, Wang further discloses the integrated circuit structure of claim 11, wherein the material (bottom layer of “high-k dielectric layer” of 270 in Fig. 12B, paragraph 0043; and see paragraph 0043, wherein “hafnium silicon oxide (HfSiO), hafnium oxide (HfO.sub.2), alumina (Al.sub.2O.sub.3), zirconium oxide (ZrO.sub.2), lanthanum oxide (La.sub.2O.sub.3), titanium oxide (TiO.sub.2), yttrium oxide (Y.sub.2O.sub.3), strontium titanate (SrTiO.sub.3), or a combination thereof”) comprising metal and oxygen is a material selected from the group consisting of titanium oxide (TiOx), tantalum oxide (TaOx) and aluminum oxide (AlOx).
Regarding claim 13, Wang further discloses the integrated circuit structure of claim 11, wherein the pair of dielectric spacers 264 (Fig. 12B, paragraph 0039, wherein “silicon nitride, silicon oxynitride, silicon nitride with oxygen or carbon elements, other suitable materials, or combinations thereof”) comprises a dielectric material selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxide, and carbon-doped silicon nitride.
Regarding claim 15, Wang further discloses the integrated circuit structure of claim 11, further comprising: a pair of epitaxial source (element number is not shown in Fig. 12B but see 252-254 in Fig. 12A, paragraph 0034) or drain structures at first and second ends of the horizontal nanowire (element number is not shown in Fig. 12B but see 204B in Fig. 4B).
Regarding claim 16, Wang further discloses the integrated circuit structure of claim 15, wherein the pair of epitaxial source (element number is not shown in Fig. 12B but see 252-254 in Fig. 12A, paragraph 0034) or drain structures is a pair of discrete epitaxial source or drain structures.
Regarding claim 20, Wang further discloses the integrated circuit structure of claim 11, wherein the horizontal nanowire (element number is not shown in Fig. 12B but see 204B in Fig. 4B, paragraph 0022) comprises silicon (see paragraph 0022,wherein “SiGe”).
Claims 4, 8, 9, 14, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Cheng as applied to claims 1 and 11 above, and further in view of Wong et al. (US 2020/0411667) (hereafter Wong).
Regarding claim 4, Wang in view of Cheng discloses the integrated circuit structure of claim 1, however Wang and Cheng do not disclose the high-k gate dielectric layer comprises a metal oxide gate dielectric material different than the material comprising metal and oxygen.
Wong discloses the high-k gate dielectric layer 262 (Fig. 20A, paragraph 0053) comprises a metal oxide gate dielectric material different (see paragraph 0053, wherein “the high-k dielectric layer 262 includes a dielectric material having a higher dielectric constant than the dielectric layer 216”) than the material 216 (Fig. 20A, paragraph 0031, wherein “the dielectric layer 216 include a high-k dielectric material”) comprising metal and oxygen.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Wang in view of Cheng to form the high-k gate dielectric layer comprises a metal oxide gate dielectric material different than the material comprising metal and oxygen, as taught by Wong, since applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
Regarding claim 8, Wang in view of Cheng discloses the integrated circuit structure of claim 1, however Wang and Cheng do not disclose the vertical arrangement of horizontal nanowires is over a sub-fin, and the material comprising metal and oxygen is further between the sub-fin and a bottommost nanowire of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.
Wong discloses the vertical arrangement of horizontal nanowires 204a (Fig. 20A, paragraph 0019) is over a sub-fin 204c (Fig. 20A, paragraph 0027), and the material 216 (Fig. 20A, paragraph 0031) comprising metal and oxygen is further between the sub-fin 204c (Fig. 20A) and a bottommost nanowire (bottom 204a in Fig. 20A) of the vertical arrangement of horizontal nanowires 204a (Fig. 20A) at a location between the pair of dielectric spacers 212 (Fig. 20A, paragraph 0014) and the sides of the gate stack 260 (Fig. 20A, paragraph 0051).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Wang in view of Cheng to form the vertical arrangement of horizontal nanowires is over a sub-fin, and the material comprising metal and oxygen is further between the sub-fin and a bottommost nanowire of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack, as taught by Wong, since allowing better gate control (Wong, paragraph 0012), lowered leakage current, and improved scaling capability for various IC applications
Regarding claim 9, Wang in view of Cheng and Wong discloses the integrated circuit structure of claim 8, however Wang and Cheng do not disclose the sub-fin comprises a portion of a bulk silicon substrate.
Wong discloses the sub-fin 204c (Fig. 2A, paragraph 0016) comprises a portion of a bulk silicon substrate 202 (Fig. 2A, paragraph 0015, wherein “silicon”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Wang in view of Cheng to form the sub-fin comprises a portion of a bulk silicon substrate, as taught by Wong, since the doped regions (Wong, paragraph 0016) may be formed directly on the substrate 202 (Wong, Fig. 2A, paragraph 0016), in a p-well structure, in an n-well structure, in a dual-well structure, or in a raised structure such that each fin 204 (Wong, Fig. 2A, paragraph 0016) may be suitable for providing an n-type FET or a p-type FET.
Regarding claim 14, Wang in view of Cheng discloses the integrated circuit structure of claim 11, however Wang and Cheng do not disclose the high-k gate dielectric layer comprises a metal oxide gate dielectric material different than the material comprising metal and oxygen.
Wong discloses the high-k gate dielectric layer 262 (Fig. 20A, paragraph 0053) comprises a metal oxide gate dielectric material different (see paragraph 0053, wherein “the high-k dielectric layer 262 includes a dielectric material having a higher dielectric constant than the dielectric layer 216”) than the material 216 (Fig. 20A, paragraph 0031, wherein “the dielectric layer 216 include a high-k dielectric material”) comprising metal and oxygen.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Wang in view of Cheng to form the high-k gate dielectric layer comprises a metal oxide gate dielectric material different than the material comprising metal and oxygen, as taught by Wong, since applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
Regarding claim 18, Wang in view of Cheng discloses the integrated circuit structure of claim 11, however Wang and Cheng do not disclose the horizontal nanowire is over a sub-fin, and the material comprising metal and oxygen is between the sub-fin and horizontal nanowire at a location between the pair of dielectric spacers and the sides of the gate stack.
Wong discloses the horizontal nanowire 204a (Fig. 20A, paragraph 0019) is over a sub-fin 204c (Fig. 20A, paragraph 0027), and the material 216 (Fig. 20A, paragraph 0031) comprising metal and oxygen is between the sub-fin 204c (Fig. 20A) and horizontal nanowire (bottom 204a in Fig. 20A) at a location between the pair of dielectric spacers 212 (Fig. 20A, paragraph 0014) and the sides of the gate stack 260 (Fig. 20A, paragraph 0051).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Wang in view of Cheng to form the horizontal nanowire is over a sub-fin, and the material comprising metal and oxygen is between the sub-fin and horizontal nanowire at a location between the pair of dielectric spacers and the sides of the gate stack, as taught by Wong, since allowing better gate control (Wong, paragraph 0012), lowered leakage current, and improved scaling capability for various IC applications
Regarding claim 19, Wang in view of Cheng and Wong discloses the integrated circuit structure of claim 18, however Wang and Cheng do not disclose the sub-fin comprises a portion of a bulk silicon substrate.
Wong discloses the sub-fin 204c (Fig. 2A, paragraph 0016) comprises a portion of a bulk silicon substrate 202 (Fig. 2A, paragraph 0015, wherein “silicon”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Wang in view of Cheng to form the sub-fin comprises a portion of a bulk silicon substrate, as taught by Wong, since the doped regions (Wong, paragraph 0016) may be formed directly on the substrate 202 (Wong, Fig. 2A, paragraph 0016), in a p-well structure, in an n-well structure, in a dual-well structure, or in a raised structure such that each fin 204 (Wong, Fig. 2A, paragraph 0016) may be suitable for providing an n-type FET or a p-type FET.
Claims 7and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Cheng as applied to claims 5 and 15 above, and further in view of Hong et al. (US 2020/0403093) (hereafter Hong).
Regarding claim 7, Wang in view of Cheng discloses the integrated circuit structure of claim 5, however Wang and Cheng do not disclose the pair of epitaxial source or drain structures is a pair of non-discrete epitaxial source or drain structures.
Hong discloses the pair of epitaxial source or drain structures (“source and drain regions” in paragraph 0071) is a pair of non-discrete epitaxial source or drain structures (see paragraph 0071, wherein “The fins may have either discrete or non-discrete source and drain regions”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Wang in view of Cheng to form the pair of epitaxial source or drain structures is a pair of non-discrete epitaxial source or drain structures, as taught by Hong, since a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing discrete epitaxial source or drain structures from the source or drain structures listed in Hong (e.g. discrete or non-discrete source and drain regions in paragraph 0071); if this leads to the anticipated success, in the instant case providing source or drain structures to the semiconductor device, it is likely the product not of innovation but of ordinary skill. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Regarding claim 17, Wang in view of Cheng discloses the integrated circuit structure of claim 15, however Wang and Cheng do not disclose the pair of epitaxial source or drain structures is a pair of non-discrete epitaxial source or drain structures.
Hong discloses the pair of epitaxial source or drain structures (“source and drain regions” in paragraph 0071) is a pair of non-discrete epitaxial source or drain structures (see paragraph 0071, wherein “The fins may have either discrete or non-discrete source and drain regions”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Wang in view of Cheng to form the pair of epitaxial source or drain structures is a pair of non-discrete epitaxial source or drain structures, as taught by Hong, since a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing discrete epitaxial source or drain structures from the source or drain structures listed in Hong (e.g. discrete or non-discrete source and drain regions in paragraph 0071); if this leads to the anticipated success, in the instant case providing source or drain structures to the semiconductor device, it is likely the product not of innovation but of ordinary skill. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Response to Arguments
1. Applicant's arguments filed 6/17/2026 have been fully considered.
2. Applicant's arguments with respect to claims 1-20 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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