DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-8, 10-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al US 2016/0329298.
Pertaining to claim 1, Lee teaches a semiconductor device package, comprising:
a fanout package structure 200 including one or more functional chips 220;
a system on chip 100 mounted face down on the fanout package structure 200 and bonded face to face with the one or more functional chips See Figure 3; and
an additional functional chip 300 mounted on and bonded to the system on chip 100 see Figure 3 marked up below. Note: “face down” is overly broad, as all sides can be considered a “face” side and “face down” doesn’t explicitly imply a direction, only a certain “face”(ie side) of the element is “down” (ie facing) the next element.
PNG
media_image1.png
388
674
media_image1.png
Greyscale
Pertaining to claim 3, Lee teaches the semiconductor device package of claim 1, wherein the additional functional chip 300 is mounted face to back (face and back are arbitrary) on the system on chip 100 and a face of the additional functional chip is bonded to through silicon vias 150 in the system on chip 100 Note that 300 is bonded to vias 150 by element 360b see Figure 3.
PNG
media_image2.png
372
592
media_image2.png
Greyscale
Pertaining to claim 4, Lee teaches the semiconductor device package of claim 1, wherein the system on chip is mounted on a redistribution layer of the fanout package structure by at least one of copper pillars or solder balls Lee teaches solder ball elements see Figure 3.
Pertaining to claim 5, Lee teaches the semiconductor device package of claim 1, wherein the one or more functional chips correspond to an in-package high speed local memory that performs analogously to an on- chip static random access memory. Statement of intended use and not given any patentable weight. MPEP 2111.02 is directed to weight given to the preamble of claims and notes that the claim preamble must be read in the context of the entire claim. MEPEP 2111.02 contains more discussion and case law cites regarding this issure, and is accessible via MPEP8 (August 2001) – 2111.02 Weight of Preamble – 2100 Patentability. The determination of whether preamble recitations are structural limitations or mere statements of purpose or use “can be resolved only on review of the entirety of the [record] to gain an understanding of what the inventors actually invented and intended to encompass by the claim.” Corning Glass Works, 868 F.2d at 1257, 9 USPQ2d at 1966. If the body of the claim fully and intrinsically sets forth all the limitations of the claimed invention, and the preamble merely states, for example, the purpose or intended use of the invention, rather than any distinct preamble is not considered a limitation and is of no significance to claim construction.
Pertaining to claim 6, Lee teaches the semiconductor device package of claim 1, wherein the additional functional chip corresponds to a dynamic random access memory. [0062] Lee teaches DDR memory
Pertaining to claim 7, Lee teaches the semiconductor device package of claim 1, further comprising a mold material surrounding the system on chip and the additional functional chip. Elements 140 and 340 see Figure 3
Pertaining to claim 8, Lee teaches a method, comprising:
mounting a system on chip 100 face down on a fanout package structure 200 in a manner that bonds the system on chip face to face with one or more functional chips included in the fanout package structure See Figure 3 marked up below;
mounting an additional functional chip 300 on the system on chip; and
bonding the additional functional chip to the system on chip See Figure 3 marked up below.
PNG
media_image1.png
388
674
media_image1.png
Greyscale
Pertaining to claim 10, Lee teaches the method of claim 9, wherein bonding the additional functional chip includes: bonding the additional functional chip to the system on chip by wire bonding 330. See Figure 3, wire bonding is employed to bond the functional chip elements to the SOC with intervening wiring layers within element 310. The claim does not exclude intermediate elements and “bonding” can include all elements required for the connection to be complete.
Pertaining to claim 11, Lee teaches the method of claim 8, wherein mounting the additional functional chip 300 includes:
mounting the additional functional chip 300 face to back (face and back are arbitrary) on the system on chip 100. See Figure 3 marked up below
PNG
media_image2.png
372
592
media_image2.png
Greyscale
Pertaining to claim 12, Lee teaches the method of claim 11, wherein bonding the additional functional chip includes:
bonding a face of the additional functional chip 300 to through silicon vias 150 in the system on chip 100 see Figure 3.
Pertaining to claim 13, Lee teaches the method of claim 8, wherein the system on chip is mounted on a redistribution layer of the fanout package structure by at least one of copper pillars or solder balls Lee teaches solder balls see Figure 3.
Pertaining to claim 14, Lee teaches the method of claim 8, wherein the one or more functional chips correspond to an in-package high speed local memory that performs analogously to an on-chip static random access memory. Statement of intended use and not given any patentable weight. MPEP 2111.02 is directed to weight given to the preamble of claims and notes that the claim preamble must be read in the context of the entire claim. MEPEP 2111.02 contains more discussion and case law cites regarding this issure, and is accessible via MPEP8 (August 2001) – 2111.02 Weight of Preamble – 2100 Patentability. The determination of whether preamble recitations are structural limitations or mere statements of purpose or use “can be resolved only on review of the entirety of the [record] to gain an understanding of what the inventors actually invented and intended to encompass by the claim.” Corning Glass Works, 868 F.2d at 1257, 9 USPQ2d at 1966. If the body of the claim fully and intrinsically sets forth all the limitations of the claimed invention, and the preamble merely states, for example, the purpose or intended use of the invention, rather than any distinct preamble is not considered a limitation and is of no significance to claim construction.
Pertaining to claim 15, Lee teaches the method of claim 8, wherein the additional functional chip corresponds to a dynamic random access memory. [0062] Lee teaches DDR memory
Pertaining to claim 16, Lee teaches the method of claim 8, further comprising:
surrounding the system on chip and the additional functional chip with a mold material. Elements 140 and 340 see Figure 3
Pertaining to claim 17, Lee teaches a system comprising:
a system on chip 100 mounted face down on a top redistribution layer of a fanout package 200; and
a functional chip 300 mounted on the system on chip 100. See Figure 3 marked up below
PNG
media_image3.png
586
836
media_image3.png
Greyscale
Pertaining to claim 18, Lee teaches the system of claim 17, wherein the functional chip is mounted face up atop the system on chip and is bonded to the system on chip using wire bonds that connect a face of the functional chip to the top redistribution layer of the fanout package. See Figure 3 marked up directly above in the rejection of claim 17. Wire bonding is employed to bond the functional chip elements to the SOC with intervening wiring layers within element 310. The claim does not exclude intermediate elements and “bonding” can include all elements required for the connection to be complete.
Pertaining to claim 19, Lee teaches the system of claim 17, wherein the functional chip is mounted face down atop the system on chip and is bonded to the system on chip by through silicon vias in the system on chip. Given that this is a different embodiment than Claim 18, the reference can be reinterpreted (including in claim 17) as “face” and “up” “down” are arbitrary and interchangeable without additional clarifying relationships between the elements. Lee teaches vias 150 to mount the functional chip to the SoC as shown in Figure 3. The claim does not exclude intermediate elements and “bonding” can include all elements required for the connection to be complete. See newly marked up Figure 3 for an alternative interpretation for this different embodiment
PNG
media_image4.png
490
752
media_image4.png
Greyscale
Pertaining to claim 20, Lee teaches the system of claim 18, wherein the functional chip corresponds to a dynamic random access memory. [0062] Lee teaches DDR memory
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claims 1 and 8 above, and further in view of Aoki US 2020/0091102.
Pertaining to claim 2, Lee teaches the semiconductor device package of claim 1, wherein the additional functional chip is mounted back to back on the system on chip by a solder ball in combination with wire bonding mount and does not teach wherein an adhesive is used and then subsequently bonded to the system on chip by wire bonding. Aoki teaches that a chip package can be mounted to a system on a chip using adhesive 12a and wire bonds 13 see Figure 2 marked up below. It would have been within the scope of one of ordinary skill in the art at the time the invention was filed to combine the teachings of Lee and Aoki to enable the bonding step of Lee to be performed according to the teachings of Aoki because one of ordinary skill in the art at the time the invention was filed would have been motivated to look to alternative suitable methods of performing the disclosed bonding step of Lee and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
PNG
media_image5.png
530
780
media_image5.png
Greyscale
Pertaining to claim 9, Lee teaches the method of claim 8, but does not teach using an adhesive to mount the functional chip to the system on a chip. Aoki teaches that a chip package can be mounted to a system on a chip using adhesive 12a and wire bonds 13 see Figure 2 marked up above. It would have been within the scope of one of ordinary skill in the art at the time the invention was filed to combine the teachings of Lee and Aoki to enable the bonding step of Lee to be performed according to the teachings of Aoki because one of ordinary skill in the art at the time the invention was filed would have been motivated to look to alternative suitable methods of performing the disclosed bonding step of Lee and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
Prosecution Insights