DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-9, 11-17, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al US 2023/0110079 (Tsai) and further in view of Tsai et al US 2021/0305226 (Tsai 2).
Pertaining to claim 1, Tsai teaches a semiconductor device package, comprising:
a fanout package structure 10 including a redistribution layer 110/150/160 and one or more functional chips 130/140 embedded therein, wherein faces of the one or more functional chips are mounted to the redistribution layer 110/150/160;
a system on chip 170 mounted face down on the redistribution layer 110/150/160 of the fanout package structure 10 and bonded face to face with the one or more functional chips (170 is bonded to 130/140 “face to face” in that the sides with connection elements are facing each other as illustrated in figure 1 P1/P3 [0030]); and
Tsai fails to teach an additional functional chip mounted on and bonded to the system on chip. Tsai 2 teaches a package structure with embedded functional chip 111, comprising a system on a chip (SoC) 150 with multiple chips 150a/b/c/d arranged in a stacked and bonded structure as illustrated in Figure 1F [0039]-[0040]. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate the multi stack of SoC dies as taught by Tsai 2 with the device package of Tsai, the ordinary artisan would have been motivated to do so for the purpose of expanding the function of the SoC package, namely by providing the additional functions of the chips taught by Tsai 2 in [0040] such as logic, memory, radio, analog, sensing, power management, voltage management etc (see cited paragraph) and would have been a matter of design choice to optimize the function of the packaged device.
Pertaining to claim 3, Tsai in view of Tsai 2 teaches the semiconductor device package of claim 1, wherein the additional functional chip is mounted face to back (this is totally arbitrary, you can simply select a side to be the “face” or the “back” as those terms imply no specific structural limitation) on the system on chip and a face of the additional functional chip is bonded to through silicon vias in the system on chip See Tsai 2 [0040] and Figure 1F, 150d can be the SoC and 150C is bonded to 150d to through silicon vias 136.
Pertaining to claim 4, Tsai in view of Tsai 2 teaches the semiconductor device package of claim 1, wherein the system on chip is mounted on the redistribution layer of the fanout package structure by at least one of copper pillars or solder balls Both Tsai and Tsai 2 teach bonding using solder balls (174 Tsai) (155 Tsai 2).
Pertaining to claim 5, Tsai in view of Tsai 2 teaches the semiconductor device package of claim 1, wherein the one or more functional chips correspond to an in-package high speed local memory that performs analogously to an on-chip static random access memory See Tsai 2 [0040] teaches that one of the chips 150a/b/c/d can be a high bandwidth memory.
Pertaining to claim 6, Tsai in view of Tsai 2 teaches the semiconductor device package of claim 1, wherein the additional functional chip corresponds to a dynamic random access memory See Tsai 2 [0040].
Pertaining to claim 7, Tsai in view of Tsai 2 teaches the semiconductor device package of claim 1, further comprising a mold material surrounding the system on chip and the additional functional chip See Tsai 2 element 151.
Pertaining to claim 8, Tsai teaches a method, comprising:
mounting a system on chip 170 face down on a redistribution layer 110/150/160 of a fanout package structure in a manner that bonds the system on chip 170 face to face (bumps to bumps) with one or more functional chips 130/140 embedded in the redistribution layer of included in the fanout package structure See Figure 1, wherein faces of the one or more functional chips are mounted to the redistribution layer 110/150/160 see Figure 1;
Tsai fails to teach an additional functional chip mounted on and bonded to the system on chip. Tsai 2 teaches a package structure with embedded functional chip 111, comprising a system on a chip (SoC) 150 with multiple chips 150a/b/c/d arranged in a stacked and bonded structure as illustrated in Figure 1F [0039]-[0040]. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate the multi stack of SoC dies as taught by Tsai 2 with the device package of Tsai, the ordinary artisan would have been motivated to do so for the purpose of expanding the function of the SoC package, namely by providing the additional functions of the chips taught by Tsai 2 in [0040] such as logic, memory, radio, analog, sensing, power management, voltage management etc (see cited paragraph) and would have been a matter of design choice to optimize the function of the packaged device.
Pertaining to claim 9, Tsai in view of Tsai 2 teaches the method of claim 8, wherein mounting the additional functional chip includes:
mounting the additional functional chip back to back (this is totally arbitrary, you can simply select a side to be the “face” or the “back” as those terms imply no specific structural limitation) on the system on chip by an adhesive Tsai 2 teaches solder balls, which are adhesive see Tsai 2 Figure 1F element 147.
Pertaining to claim 11, Tsai in view of Tsai 2 teaches the method of claim 8, wherein mounting the additional functional chip includes:
mounting the additional functional chip 150a/b/c/d face to back on the system on chip [0040] Tsai 2 Note “face” and “back” are not terms that imply a physical structure and are wholly arbitrary in nature, Tsai 2 teaches additional functional chips stacked on each other and you can call one side the face and one side the back or vice versa, without additional claimed description it doesn’t matter see Tsai 2 Figure 1F elements 150a/b/c/d.
Pertaining to claim 12, Tsai in view of Tsai 2 teaches the method of claim 11, wherein bonding the additional functional chip includes:
bonding a face of the additional functional chip to through silicon vias in the system on chip. Tsai 2 teaches bonding additional functional chips to through vias 136 in chips 150a/b/c/d see Figure 1F
Pertaining to claim 13, Tsai in view of Tsai 2 teaches the method of claim 8, wherein the system on chip is mounted on the redistribution layer of the fanout package structure by at least one of copper pillars or solder balls 155 see Tsai 2 (see also Tsai element 174).
Pertaining to claim 14, Tsai in view of Tsai 2 teaches the method of claim 8, wherein the one or more functional chips correspond to an in-package high speed local memory that performs analogously to an on-chip static random access memory. See Tsai 2 [0040] teaches that one of the chips 150a/b/c/d can be a high bandwidth memory
Pertaining to claim 15, Tsai in view of Tsai 2 teaches the method of claim 8, wherein the additional functional chip corresponds to a dynamic random access memory. See Tsai 2 [0040].
Pertaining to claim 16, Tsai in view of Tsai 2 teaches the method of claim 8, further comprising:
surrounding the system on chip and the additional functional chip with a mold material See Tsai 2 element 151.
Pertaining to claim 17, Tsai teaches a system comprising:
a system on chip 170 mounted face down arbitrary on a top redistribution layer 110/150/160 of a fanout package structure 10 and bonded face to face arbitrary nonetheless bump bonds to bump bonds implies the same sides are being bonded with one or more functional chips 130/140,
Tsai fails to teach the one or more functional chips embedded in the top redistribution layer, wherein faces of the one or more functional chips are mounted to the redistribution layer; and an additional functional chip mounted on and bonded to the system on chip.
Tsai 2 teaches
functional chip 112 embedded in the top redistribution layer 115 (out of 122+115),
wherein faces of the one or more functional chips are mounted to the redistribution layer 122; and an additional functional chip 150a/b/c/d mounted on and bonded to the system on chip 150a/b/c/d [0040]. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate the multi stack of SoC dies as taught by Tsai 2 with the device package of Tsai, the ordinary artisan would have been motivated to do so for the purpose of expanding the function of the SoC package, namely by providing the additional functions of the chips taught by Tsai 2 in [0040] such as logic, memory, radio, analog, sensing, power management, voltage management etc (see cited paragraph) and would have been a matter of design choice to optimize the function of the packaged device.
Pertaining to claim 19, Tsai in view of Tsai 2 teaches the system of claim 17, wherein the additional functional chip is mounted face down arbitrary atop the system on chip 150 [0040] and is bonded to the system on chip by through silicon vias in the system on chip. Tsai 2 teaches bonding additional functional chips to through vias 136 in chips 150a/b/c/d see Figure 1F
Claim(s) 2, 10, 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al US 2023/0110079 (Tsai) and further in view of Tsai et al US 2021/0305226 (Tsai 2) and further in view of Seidemann et al US 2019/0214369
Pertaining to claims 2, 10 and 18, Tsai in view of Tsai 2 teach the package/method/system as claimed in claims 1, 8 and 17, but fail to teach wherein the additional functional chip is mounted on the system on chip by an adhesive and bonded to the system on chip by wire bonding. (note “face” and “back” are arbitrary and do not imply any physical features or elements and the face or back can be arbitrarily selected)
Seidemann teaches a chip 130 adhered to another chip 125 which is mounted to a substrate with electrical interconnections (ie redistribution networks), the chip 130 being wire bonded 120 to the substrate 135 see Figure 1. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to select a known in the art interconnection technique such as wiring bonding to electrically connect a chip to an electrical interconnect structure in a substrate as an alternative to bump bonding with through vias as this is a simple matter of design choice that one of ordinary skill at the time the invention was filed would have known to consider. When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill in the art has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co v. Teleflex Inc.
Pertaining to claim 20 Tsai in view of Tsai 2 in view of Seidemann teaches the system of claim 18, wherein the additional functional chip corresponds to a dynamic random access memory Tsai 2 [0040].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30.
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/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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