DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Office acknowledges receipt on 18 June 2025 of Applicants’ amendments in which claims 1, 5, 6, 9, 10, 14, 15, 18, and 19 are amended, claims 2-4, 11-13, and 20 are cancelled, and claims 21-27 are newly added. The Office withdraws the drawing objections and the indefiniteness rejections identified in the Office Communication dated 19 March 2026 in view of the amendments.
Response to Arguments
Applicants’ arguments with respect to claim(s) 1, 10, and 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claim 10 is objected to because of the following informalities:
Claim 10, line 3, recites “a in-package memory,” which should read “an in-package memory” for proper grammar.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5, 10, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (US20230253381A1) in view of Choi et al. (US20220077064A1).
Regarding claim 1, Jeong teaches in Fig. 13 a semiconductor device package, comprising:
a system on chip (SoC) (120) configured to interface with multiple types of memory {[0032, 0037]};
in-package memory (140) connected to the SoC (120) by a via (125) included in a packaging laminate substrate (145, 125, 123) positioned between the SoC (120) and the in-package memory (140) {[0037]}; and
dynamic random access memory (220) mounted back-to-back on the SoC (120) by an adhesive (224) and bonded to the SoC (120) by wire bonding (225) [0097].
Jeong does not teach the via included in a packaging laminate substrate is part of a via stack; and the packaging laminate substrate comprises a plurality of layers, each layer of the plurality of layers including a plurality of vias having corresponding via pads.
In an analogous art, Choi teaches in Fig. 7 and paragraph [0100] a via included in a packaging laminate substrate (240) is part of a via stack (stack of 241); and the packaging laminate substrate (240) comprises a plurality of layers (e.g., layers of 245), each layer of the plurality of layers including a plurality of vias (241) having corresponding via pads (243). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong’s semiconductor device package based on the teachings of Choi, to achieve the above-identified subject matter, for interconnecting two electronic components. Choi [0004]. Moreover, all the claimed elements (e.g., packaging laminate substrate, via stack, layers, vias, via pads) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Choi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Examiner’s Note: The limitation of “to interface with multiple types of memory” is directed to a manner in which the claimed subject matter is intended to be employed and, accordingly, does not structurally distinguish the claimed invention from the prior art. MPEP §2114(II) – a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Regarding claim 5, Jeong as modified by Choi teaches the semiconductor device package of claim 1, but Jeong does not teach wherein the via stack is configured to provide via-to-via connection of the SoC to the in-package memory.
Choi teaches in Fig. 7 and paragraph [0100] a via stack (240) is configured to provide via (241) to via (241) connection of a chip (204) to another chip (202). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong’s semiconductor device package as modified by Choi based on the further teachings of Choi – such that Jeong’s modified via stack is configured to provide via-to-via connection of Jeong’s SoC to Jeong’s in-package memory – for interconnecting the two electronic components. Choi [0004]. Moreover, all the claimed elements (e.g., via stack, via-to-via connection, SoC, in-package memory) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Choi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 10, Jeong teaches in Fig. 13 a method, comprising:
positioning a packaging laminate substrate (145, 125, 123) between a system on chip (SoC) (120) configured to interface with multiple types of memory and a[n] in-package memory (140), wherein the in-package memory (140) is connected to the SoC (120) by a via (125) included in the packaging laminate substrate (145, 125, 123) {[0032, 0037]}, and
mounting a dynamic random access memory (220) back-to-back on the SoC (120) using an adhesive (224); and bonding the dynamic random access memory (220) to the SoC (120) using wire bonding (225) [0097].
Jeong does not teach the via included in a packaging laminate substrate is part of a via stack; and the packaging laminate substrate comprises a plurality of layers, each layer of the plurality of layers including a plurality of vias having corresponding via pads.
Choi teaches in Fig. 7 and paragraph [0100] a via included in a packaging laminate substrate (240) is part of a via stack (stack of 241); and the packaging laminate substrate (240) comprises a plurality of layers (e.g., layers of 245), each layer of the plurality of layers including a plurality of vias (241) having corresponding via pads (243). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong’s method based on the teachings of Choi, to achieve the above-identified subject matter, for interconnecting two electronic components. Choi [0004]. Moreover, all the claimed elements (e.g., packaging laminate substrate, via stack, layers, vias, via pads) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Choi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Examiner’s Note: The limitation of “to interface with multiple types of memory” is directed to a manner in which the claimed subject matter is intended to be employed and, accordingly, does not structurally distinguish the claimed invention from the prior art. MPEP §2114(II) – a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Regarding claim 14, Jeong as modified by Choi teaches the method of claim 10, but Jeong does not teach wherein the via stack is configured to provide via-to-via connection of the SoC to the in-package memory.
Choi teaches in Fig. 7 and paragraph [0100] a via stack (240) is configured to provide via (241) to via (241) connection of a chip (204) to another chip (202). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong’s method as modified by Choi based on the further teachings of Choi – such that Jeong’s modified via stack is configured to provide via-to-via connection of Jeong’s SoC to Jeong’s in-package memory – for interconnecting the two electronic components. Choi [0004]. Moreover, all the claimed elements (e.g., via stack, via-to-via connection, SoC, in-package memory) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Choi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 6 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong in view of Choi as applied to claim 1 (for claim 6) and claim 10 (for claim 15) above, and further in view of Chung et al. (US20240055343A1).
Regarding claim 6, Jeong as modified by Choi teaches the semiconductor device package of claim 1, but Jeong does not teach further comprising a mold material surrounding the SoC and the dynamic random access memory.
In an analogous art, Chung teaches in Fig. 8B and paragraphs [0034, 0035, 0047, 0070] a mold material (507) surrounding an SoC (201) and a dynamic random access memory (202). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong’s semiconductor device package as modified by Choi based on the teachings of Chung, to achieve the above-identified subject matter, to provide[] protection from moisture, dust, and other environmental factors. Chung [0003]. Moreover, all the claimed elements (e.g., mold material, SoC, dynamic random access memory) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Chung) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 15, Jeong as modified by Choi teaches the method of claim 10, but Jeong does not teach further comprising surrounding the SoC and the dynamic random access memory with a mold material.
Chung teaches in Fig. 8B and paragraphs [0034, 0035, 0047, 0070] surrounding an SoC (201) and a dynamic random access memory (202) with a mold material (507). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong’s method as modified by Choi based on the teachings of Chung, to achieve the above-identified subject matter, to provide[] protection from moisture, dust, and other environmental factors. Chung [0003]. Moreover, all the claimed elements (e.g., mold material, SoC, dynamic random access memory) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Chung) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 7, 8, 16, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong in view of Choi as applied to claim 1 (for claims 7 and 8) and claim 10 (for claims 16 and 17) above, and further in view of Sundaram et al. (US20120106117A1).
Regarding claim 7, Jeong as modified by Choi teaches the semiconductor device package of claim 1, but Jeong does not teach wherein the via stack has a pitch in a range of forty to eighty micrometers.
In an analogous art, Sundaram teaches in Fig. 3 and paragraph [0063] a via stack (110, 140) has a pitch in a range of forty to eighty micrometers {pitch of 3-50 micrometers}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong’s semiconductor device package as modified by Choi based on the teachings of Sundaram – such that the via stack has a pitch in a range of forty to eighty micrometers – so ultra-small through vias … can be defined within the interposer … such that each of the through vias … extends from the first side … to the second side … of the interposer. Sundaram [0063]. Moreover, all the claimed elements (e.g., via stack, pitch) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Sundaram) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. MPEP §2144.05(I).
Regarding claim 8, Jeong as modified by Choi teaches the semiconductor device package of claim 1, but Jeong does not teach wherein individual vias of the via stack have a size in a range of ten to forty micrometers.
Sundaram teaches in Fig. 3 and paragraph [0063] that individual vias (110) of a via stack (110, 140) have a size in a range of ten to forty micrometers (diameter of 1-25 micrometers). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong’s semiconductor device package as modified by Choi based on the teachings of Sundaram – such that individual vias of the via stack have a size in a range of ten to forty micrometers – so ultra-small through vias … can be defined within the interposer … such that each of the through vias … extends from the first side … to the second side … of the interposer. Sundaram [0063]. Moreover, all the claimed elements (e.g., vias, via stack, size) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Sundaram) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. MPEP §2144.05(I).
Regarding claim 16, Jeong as modified by Choi teaches the method of claim 10, but Jeong does not teach wherein the via stack has a pitch in a range of forty to eighty micrometers.
Sundaram teaches in Fig. 3 and paragraph [0063] a via stack (110, 140) has a pitch in a range of forty to eighty micrometers {pitch of 3-50 micrometers}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong’s method as modified by Choi based on the teachings of Sundaram – such that the via stack has a pitch in a range of forty to eighty micrometers – so ultra-small through vias … can be defined within the interposer … such that each of the through vias … extends from the first side … to the second side … of the interposer. Sundaram [0063]. Moreover, all the claimed elements (e.g., via stack, pitch) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Sundaram) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. MPEP §2144.05(I).
Regarding claim 17, Jeong as modified by Choi teaches the method of claim 10, but Jeong does not teach wherein individual vias of the via stack have a size in a range of ten to forty micrometers.
Sundaram teaches in Fig. 3 and paragraph [0063] that individual vias (110) of a via stack (110, 140) have a size in a range of ten to forty micrometers (diameter of 1-25 micrometers). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong’s method as modified by Choi based on the teachings of Sundaram – such that individual vias of the via stack have a size in a range of ten to forty micrometers – so ultra-small through vias … can be defined within the interposer … such that each of the through vias … extends from the first side … to the second side … of the interposer. Sundaram [0063]. Moreover, all the claimed elements (e.g., vias, via stack, size) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Sundaram) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. MPEP §2144.05(I).
Claim(s) 9 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong in view of Choi as applied to claim 1 (for claim 9) and claim 10 (for claim 18) above, and further in view of Majhi et al. (US20250112205A1).
Regarding claim 9, Jeong as modified by Choi teaches the semiconductor device package of claim 1, but Jeong does not teach wherein the packaging laminate substrate further includes a plurality of peripheral stack vias configured to supply power and input-output routing to the SoC and the in-package memory.
In an analogous art, Majhi teaches in Fig. 2G and paragraph [0049] a plurality of peripheral stack vias (287) configured to supply power and input-output routing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong’s semiconductor device package as modified by Choi based on the teachings of Majhi – such that Jeong’s modified packaging laminate substrate further includes a plurality of peripheral stack vias configured to supply power and input-output routing to Jeong’s SoC and in-package memory – so [t]he redistribution layer region … can further provide the routing of power and ground signals to the integrated circuit dies. Majhi [0049]. Moreover, all the claimed elements (e.g., stack vias) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Majhi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
The Office notes that the recitation of “configured to supply power and input-output routing” is directed to a manner in which the claimed subject matter is intended to be employed and, accordingly, does not structurally distinguish the claimed invention from the prior art. MPEP §2114(II) – a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Still further, the Office notes that every conductor is implicitly “configured to supply power and input-output routing.”
Regarding claim 18, Jeong as modified by Choi teaches the method of claim 10, but Jeong does not teach wherein the packaging laminate substrate further includes a plurality of peripheral stack vias configured to supply power and input-output routing to the SoC and the in-package memory.
Majhi teaches in Fig. 2G and paragraph [0049] a plurality of peripheral stack vias (287) configured to supply power and input-output routing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong’s method as modified by Choi based on the teachings of Majhi – such that Jeong’s modified packaging laminate substrate further includes a plurality of peripheral stack vias configured to supply power and input-output routing to Jeong’s system on chip and Jeong’s functional chip – so [t]he redistribution layer region … can further provide the routing of power and ground signals to the integrated circuit dies. Majhi [0049]. Moreover, all the claimed elements (e.g., stack vias) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Majhi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
The Office further notes that the recitation of “configured to supply power and input-output routing” is directed to a manner in which the claimed subject matter is intended to be employed and, accordingly, does not structurally distinguish the claimed invention from the prior art. MPEP §2114(II) – a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Still further, the Office notes that every conductor is implicitly “configured to supply power and input-output routing.”
Claim(s) 22 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong in view of Choi as applied to claim 1 (for claim 22) and claim 10 (for claim 26) above, and further in view of Chun et al. (US20210202391A1).
Regarding claim 22, Jeong as modified by Choi teaches the semiconductor device package of claim 1, but Jeong does not teach wherein via pads corresponding to individual vias of the via stack have a size in a range of twenty-five to sixty micrometers.
In an analogous art, Chun teaches in Fig. 15 and paragraph [0047] via pads (pad-RDL1 through pad-RDL3) corresponding to individual vias (via3) of the via stack have a size in a range of twenty to fifty micrometers, while the dimensions may be greater or smaller. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong’s semiconductor device package as modified by Choi based on the teachings of Chun – such that Jeong’s via pads corresponding to individual vias of the via stack have a size in a range of twenty-five to sixty micrometers – because all the claimed elements (e.g., via pads, vias, via stack) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Chun) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. MPEP §2144.05(I).
Regarding claim 26, Jeong as modified by Choi teaches the method of claim 10, but Chung does not teach wherein via pads corresponding to individual vias of the via stack have a size in a range of twenty-five to sixty micrometers.
In an analogous art, Chun teaches in Fig. 15 and paragraph [0047] via pads (pad-RDL1 through pad-RDL3) corresponding to individual vias (via3) of a via stack have a size in a range of twenty to fifty micrometers, while the dimensions may be greater or smaller. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong’s method as modified by Choi based on the teachings of Chun, to achieve the above-identified subject matter, because all the claimed elements (e.g., via pads, vias, via stack) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Chun) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. MPEP §2144.05(I).
Claim(s) 23, 24, and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong in view of Choi as applied to claim 1 (for claims 23 and 24) and claim 10 (for claim 27) above, and further in view of Chen et al. (US20230040467A1).
Regarding claim 23, Jeong as modified by Choi teaches the semiconductor device package of claim 1, but Jeong does not teach further comprising an underfill provided around connection elements that connect the SoC to pads of the via stack.
In an analogous art, Chen teaches in Figs. 2B, 8 and paragraphs [0057, 0065] an underfill (225) provided around connection elements (228) that connect an SoC (223) to pads (e.g., 244a1) of a via stack (e.g., 240b1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong’s semiconductor device package as modified by Choi based on the teachings of Chen, to achieve the above-identified subject matter, to fix the first semiconductor die … and second semiconductor die … to the interposer. Chen [0057]. Moreover, all the claimed elements (e.g., underfill, connection elements, SoC, pads, via stack) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Chen) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 24, Jeong as modified by Choi teaches the semiconductor device package of claim 1, but Jeong does not teach further teaches wherein vias of the via stack, via pads corresponding to the vias, bumps of the in-package memory, and bumps of the SoC have a same pitch.
Chen teaches in Figs. 2B, 8, 17 and paragraphs [0065, 0099] that vias (e.g., 241a2, 242a2, 243a2, 244a2) of a via stack (e.g., 240b1), via pads (e.g., 242a1, 243a1, 244a1) corresponding to the vias, bumps (228) of an in-package memory (224/223), and bumps (228) of an SoC (223/224) have a same pitch. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong’s semiconductor device package as modified by Choi based on the teachings of Chen, to achieve the above-identified subject matter, because all the claimed elements (e.g., vias, via stack, via pads, bumps, in-package memory, SoC, pitch) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Chen) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 27, Jeong as modified by Choi teaches the method of claim 10, but Chung does not teach wherein vias of the via stack, via pads corresponding to the vias, bumps of the in-package memory, and bumps of the SoC have a same pitch.
Chen teaches in Figs. 2B, 8, 17 and paragraphs [0065, 0099] that vias (e.g., 241a2, 242a2, 243a2, 244a2) of a via stack (e.g., 240b1), via pads (e.g., 242a1, 243a1, 244a1) corresponding to the vias, bumps (228) of an in-package memory (224/223), and bumps (228) of an SoC (223/224) have a same pitch. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong’s method as modified by Choi based on the further teachings of Chen, to achieve the above-identified subject matter, because all the claimed elements (e.g., vias, via stack, via pads, bumps, in-package memory, SoC, pitch) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Chen) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong in view of Choi as applied to claim 1 above, and further in view of Lin et al. (US20160343695A1).
Regarding claim 25, Jeong as modified by Choi teaches the semiconductor device package of claim 1, but Jeong does not teach further comprising a first dielectric material layer arranged between the packaging laminate substrate and the SoC, and a second dielectric material layer arranged between the packaging laminate substrate and the in-package memory.
In an analogous art, Lin teaches in Fig. 5 and paragraph [0025, 0030, 0042, 0060] a first dielectric material layer (150B) arranged between a packaging laminate substrate (e.g., substrate including vias and pads of 130A and/or 130B) and an SoC (110B), and a second dielectric material (150A) layer arranged between the packaging laminate substrate (e.g., substrate including vias and pads of 130A and/or 130B) and an in-package memory (110A). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong’s semiconductor device package as modified by Choi based on the teachings of Lin, to achieve the above-identified subject matter, to electrically insulate individual conductive elements from undesired electrical signals. Moreover, all the claimed elements (e.g., dielectric material layer, packaging laminate substrate, SoC, in-package memory) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Lin) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong in view of Shim et al. (US20190103432A1) and Choi.
Regarding claim 19, Jeong teaches in Fig. 13 a system, comprising:
a semiconductor device package (1000) {[0090]}, wherein the semiconductor device package (1000) includes:
a system on chip (SoC) (120) configured to interface with multiple types of memory {[0032, 0037]};
in-package memory (140) connected to the SoC (120) by a via (125) included in a packaging laminate substrate (145, 125, 123) positioned between the SoC (120) and the in-package memory (140) {[0037]}
; and
dynamic random access memory (220) mounted back-to-back on the SoC (120) by an adhesive (224) and bonded to the SoC (120) by wire bonding (225) [0097].
Jeong does not teach a display device; and a semiconductor device package configured to process images rendered to the display device.
In an analogous art, Shim teaches a display device (1020) {Fig. 16; [0080]}; and a semiconductor device package (1) configured to process images rendered to the display device (1020) {Figs. 1, 16; [0025, 0078]}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong’s system based on the teachings of Shim – to include a display device; and a semiconductor device package configured to process images rendered to the display device – for communicating processed imagery to a display for viewing by a user. Shim [0028]. Moreover, all the claimed elements (e.g., semiconductor device package, display device) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Shim) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Jeong does not teach the via included in a packaging laminate substrate is part of a via stack; and the packaging laminate substrate comprises a plurality of layers, each layer of the plurality of layers including a plurality of vias having corresponding via pads.
In an analogous art, Choi teaches in Fig. 7 and paragraph [0100] a via included in a packaging laminate substrate (240) is part of a via stack (stack of 241); and the packaging laminate substrate (240) comprises a plurality of layers (e.g., layers of 245), each layer of the plurality of layers including a plurality of vias (241) having corresponding via pads (243). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong’s system as modified by Shim based on the teachings of Choi, to achieve the above-identified subject matter, for interconnecting two electronic components. Choi [0004]. Moreover, all the claimed elements (e.g., packaging laminate substrate, via stack, layers, vias, via pads) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Choi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Examiner’s Note: The limitations of: (1) “to process images rendered to the display device” and (2) “to interface with multiple types of memory” are directed to a manner in which the claimed subject matter is intended to be employed and, accordingly, do not structurally distinguish the claimed invention from the prior art. MPEP §2114(II) – a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong in view of Shin and Choi as applied to claim 19 above, and further in view of Ayyapureddi (US20250194111A1) and Gao et al. (US20230125131A1).
Regarding claim 21, Jeong as modified by Shim and Choi teaches the system of claim 19, but Jeong does not teach wherein the SoC comprises a neural network accelerator configured to process images rendered to the display device.
However, Jeong teaches in Fig. 1 and paragraph [0032] an SoC (120). A system-on-chip (SoC) is nomenclature for a computing device having a processor, a memory, and an input/output communication port.
In an analogous art, Ayyapureddi teaches in Fig. 8 and paragraph [0042] a computing device (800) having a processor (804), which may be a neural network accelerator. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong’s system as modified by Shim and Choi based on the teachings of Ayyapureddi – such that the processor of Jeong’s SoC is a neural network accelerator – because all the claimed elements (e.g., SoC, neural network accelerator) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Ayyapureddi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Jeong does not teach the neural network accelerator configured to process images rendered to the display device.
In an analogous art, Gao teaches in paragraph [0137] a neural network accelerator configured to process images rendered to a display device. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong’s system as modified by Shim, Choi, and Ayyapureddi based on the teachings of Gao – such that Ayyapureddi’s neural network accelerator is configured to process images rendered to the display device – so a user may make use of the processed imagery. Moreover, all the claimed elements (e.g., neural network accelerator, images, display device) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Gao) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Examiner’s Note: The limitation of “to process images rendered to the display device” is directed to a manner in which the claimed subject matter is intended to be employed and, accordingly, does not structurally distinguish the claimed invention from the prior art. MPEP §2114(II) – a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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