DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following features must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 5, lines 1 and 2, recites “the via stack is configured to provide direct via to via connection of the system on chip to the functional chip,” which is not illustrated by the drawings. Instead, the drawings (e.g., Fig. 2) illustrate that pads (e.g., 210) are disposed between every adjacent pair of indirectly connected vias (e.g., 208).
Claim 14, lines 1 and 2, recites “the via stack is configured to provide direct via to via connection of the system on chip to the functional chip,” which is not illustrated by the drawings. Instead, the drawings (e.g., Fig. 2) illustrate that pads (e.g., 210) are disposed between every adjacent pair of indirectly connected vias (e.g., 208).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-5 and 12-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3, lines 1 and 2, recites “the additional functional chip corresponds to a dynamic random access memory,” which is indefinite because it is unclear whether the additional functional chip is a dynamic random access memory. For the purpose of compact prosecution, the claim will be interpreted to recite “the additional functional chip is a dynamic random access memory.”
Claim 4, lines 1-3, recites “the functional chip corresponds to an in-package high speed local memory that performs analogously to an on-chip static random access memory,” which is indefinite because the specification lacks a standard for measuring the degree intended with respect to the speed. MPEP 2173.05(b). Additionally, the claim is indefinite because it is unclear whether the functional chip is an in-package high speed local memory or an on-chip static random access memory. For the purpose of compact prosecution, the claim will be interpreted to recite “the functional chip is an on-chip static random access memory.”
Claim 4, lines 1 and 2, recites “the functional chip corresponds to an in-package high speed local memory,” which is indefinite because the specification lacks a standard for measuring the degree intended with respect to the speed. MPEP 2173.05(b). For the purpose of compact prosecution, the claim will be interpreted to recite “the functional chip corresponds to an in-package local memory.”Claim 5, lines 1 and 2, recites “the via stack is configured to provide direct via to via connection of the system on chip to the functional chip,” which is indefinite because it is unclear from the application how “direct via to via” connectivity is provided between the system on chip to the functional chip. The application discloses in Fig. 2 and paragraph [0024] that pads (e.g., 210) are disposed between every adjacent pair of indirectly connected vias (e.g., 208). For the purpose of compact prosecution, the claim will be interpreted to recite “the via stack is configured to provide via to via connection of the system on chip to the functional chip.”
Claim 12, lines 1 and 2, recites “the additional functional chip corresponds to a dynamic random access memory,” which is indefinite because it is unclear whether the additional functional chip is a dynamic random access memory. For the purpose of compact prosecution, the claim will be interpreted to recite “the additional functional chip is a dynamic random access memory.”
Claim 13, lines 1 and 2, recites “the functional chip corresponds to an in-package high speed local memory that performs analogously to an on-chip static random access memory,” which is indefinite because the specification lacks a standard for measuring the degree intended with respect to the speed. MPEP 2173.05(b). Additionally, the claim is indefinite because it is unclear whether the functional chip is an in-package high speed local memory or an on-chip static random access memory. For the purpose of compact prosecution, the claim will be interpreted to recite “the functional chip is an on-chip static random access memory.”
Claim 14, lines 1 and 2, recites “the via stack is configured to provide direct via to via connection of the system on chip to the functional chip,” which is indefinite because it is unclear from the application how “direct via to via” connectivity is provided between the system on chip to the functional chip. The application discloses in Fig. 2 and paragraph [0024] that pads (e.g., 210) are disposed between every adjacent pair of indirectly connected vias (e.g., 208). For the purpose of compact prosecution, the claim will be interpreted to recite “the via stack is configured to provide via to via connection of the system on chip to the functional chip.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 6, 10, 12, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (US20240055343A1) in view of Chen et al. (US20230040467A1).
Regarding claim 1, Chung teaches in Fig. 7 a semiconductor device package, comprising:
a system on chip (201) {[0034]};
a functional chip (301) connected to the system on chip (201) by a packaging laminate substrate (101) positioned between the system on chip (201) and the functional chip (301) {[0034]}; and
an additional functional chip (202) mounted on and bonded to the system on chip (201) {[0067]}.
Chung does not explicitly teach a via stack included in a packaging laminate substrate, though Chung implicitly does so in paragraph [0034].
In an analogous art, Chen teaches in Figs. 2A and 2B and paragraphs [0063, 0065] a via stack (e.g., 242-244) included in a packaging laminate substrate (240). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chung’s semiconductor device package based on the teachings of Chen – such that a via stack is included in a packaging laminate substrate – to provide electrical communication between the components disposed on two sides thereof. Chung [0034]. Moreover, all the claimed elements (e.g., via stack, packaging laminate substrate) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Chen) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 3, as interpreted in view of the indefiniteness rejection, Chung as modified by Chen teaches the semiconductor device package of claim 1, and Chung further teaches wherein the additional functional chip (202) is a dynamic random access memory {[0035]}.
Regarding claim 6, Chung as modified by Chen teaches the semiconductor device package of claim 1, and Chung further teaches further comprising a mold material (507) surrounding the system on chip (201) and the additional functional chip (202) {[0047]}.
Regarding claim 10, Chung teaches in Fig. 7 a method, comprising:
positioning a packaging laminate substrate (101) between a system on chip (201) and a functional chip (301), wherein the functional chip (301) is connected to the system on chip (201) by the packaging laminate substrate (301) {[0034]};
mounting an additional functional chip (202) on the system on chip (201) {[0067]}; and
bonding the additional functional chip (202) to the system on chip (201) {[0067]}.
Chung does not explicitly teach a via stack included in a packaging laminate substrate, though Chung implicitly does so in paragraph [0034].
Chen teaches in Figs. 2A and 2B and paragraphs [0063, 0065] a via stack (e.g., 242-244) included in a packaging laminate substrate (240). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chung’s method based on the teachings of Chen – such that a via stack is included in a packaging laminate substrate – to provide electrical communication between the components disposed on two sides thereof. Chung [0034]. Moreover, all the claimed elements (e.g., via stack, packaging laminate substrate) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Chen) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 12, as interpreted in view of the indefiniteness rejection, Chung as modified by Chen teaches the method of claim 10, and Chung further teaches wherein the additional functional chip (202) is a dynamic random access memory {[0035]}.
Regarding claim 15, Chung as modified by Chen teaches the method of claim 10, and Chung further teaches further comprising surrounding the system on chip (201) and the additional functional chip (202) with a mold material (507) {[0047]}.
Claim(s) 2 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of Chen as applied to claim 1 (for claim 2) and claim 10 (for claim 11) above, and further in view of Ye et al. (US20070045803A1).
Regarding claim 2, Chung as modified by Chen teaches the semiconductor device package of claim 1, but Chung does not teach wherein the additional functional chip is mounted back to back on the system on chip by an adhesive and bonded to the system on chip by wire bonding.
In an analogous art, Ye teaches in Fig. 3A and paragraph [0022, 0023] an additional functional chip (22) is mounted back to back on a first chip (18) by an adhesive (20) and bonded to the first chip (18) by wire bonding (26). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chung’s semiconductor device package as modified by Chen based on the teachings of Ye – such that Chung’s additional functional chip is mounted back to back on Chung’s system on chip by an adhesive and bonded to Chung’s system on chip by wire bonding – to form a stacked assembly … [and so] [e]lectrical connections may be made between the two microelectronic package assemblies, by electrically connecting or linking contacts on a first substrate of one microelectronic package with contacts on a second substrate of the other microelectronic package. Ye [0011]. Moreover, all the claimed elements (e.g., multiple chips, adhesive, wire bonding) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Ye) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 11, Chung as modified by Chen teaches the method of claim 10, but Chung does not teach wherein the additional functional chip is mounted back to back on the system on chip by an adhesive and bonded to the system on chip by wire bonding.
Ye teaches in Fig. 3A and paragraph [0022, 0023] an additional functional chip (22) is mounted back to back on a first chip (18) by an adhesive (20) and bonded to the first chip (18) by wire bonding (26). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chung’s method as modified by Chen based on the teachings of Ye – such that Chung’s additional functional chip is mounted back to back on Chung’s system on chip by an adhesive and bonded to Chung’s system on chip by wire bonding – to form a stacked assembly … [and so] [e]lectrical connections may be made between the two microelectronic package assemblies, by electrically connecting or linking contacts on a first substrate of one microelectronic package with contacts on a second substrate of the other microelectronic package. Ye [0011]. Moreover, all the claimed elements (e.g., multiple chips, adhesive, wire bonding) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Ye) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 4, 5, 13, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of Chen as applied to claim 1 (for claims 4 and 5) and claim 10 (for claims 13 and 14) above, and further in view of Choi et al. (US20220077064A1).
Regarding claim 4, as interpreted in view of the indefiniteness rejection, Chung as modified by Chen teaches the semiconductor device package of claim 1, but Chung does not teach wherein the functional chip is an on-chip static random access memory.
In an analogous art, Choi teaches in Fig. 7: (1) a functional chip (202) electrically interconnected with another chip (204) through a packaging laminate substrate (240) disposed between the functional chip (202) and the other chip (204) {[0100]} and (2) the functional chip (202) is an on-chip static random access memory disposed within a package (200a) {[0039]}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chung’s semiconductor device package as modified by Chen based on the teachings of Choi – such that Chung’s functional chip is an on-chip static random access memory – so that data processed by Chung’s system on chip may be stored in the same structure housing the system on chip. Moreover, all the claimed elements (e.g., functional chip, static random access memory) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Choi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 5, as interpreted in view of the indefiniteness rejection, Chung as modified by Chen teaches the semiconductor device package of claim 1, but Chung does not teach wherein the via stack is configured to provide via to via connection of the system on chip to the functional chip.
Choi teaches in Fig. 7 and paragraph [0100] a via stack (240) is configured to provide via (241) to via (241) connection of a chip (204) to a functional chip (202). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chung’s semiconductor device package as modified by Chen based on the teachings of Choi – such that the via stack is configured to provide via to via connection of the system on chip to the functional chip – to provide electrical communication between the components disposed on two sides thereof. Chung [0034]. Moreover, all the claimed elements (e.g., via stack, via to via connection, chip, functional chip) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Choi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 13, as interpreted in view of the indefiniteness rejection, Chung as modified by Chen teaches the method of claim 10, but Chung does not teach wherein the functional chip is an on-chip static random access memory.
Choi teaches in Fig. 7: (1) a functional chip (202) electrically interconnected with another chip (204) through a packaging laminate substrate (240) disposed between the functional chip (202) and the other chip (204) {[0100]} and (2) the functional chip (202) is an on-chip static random access memory disposed within a package (200a) {[0039]}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chung’s method as modified by Chen based on the teachings of Choi – such that Chung’s functional chip is an on-chip static random access memory – so that data processed by Chung’s system on chip may be stored in the same structure housing the system on chip. Moreover, all the claimed elements (e.g., functional chip, static random access memory) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Choi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 14, as interpreted in view of the indefiniteness rejection, Chung as modified by Chen teaches the method of claim 10, but Chung does not teach wherein the via stack is configured to provide via to via connection of the system on chip to the functional chip.
Choi teaches in Fig. 7 and paragraph [0100] a via stack (240) is configured to provide via (241) to via (241) connection of a chip (204) to a functional chip (202). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chung’s method as modified by Chen based on the teachings of Choi – such that the via stack is configured to provide via to via connection of the system on chip to the functional chip – to provide electrical communication between the components disposed on two sides thereof. Chung [0034]. Moreover, all the claimed elements (e.g., via stack, via to via connection, chip, functional chip) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Choi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 7, 8, 16, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of Chen as applied to claim 1 (for claims 7 and 8) and claim 10 (for claims 16 and 17) above, and further in view of Sundaram et al. (US20120106117A1).
Regarding claim 7, Chung as modified by Chen teaches the semiconductor device package of claim 1, but Chung does not teach wherein the via stack has a pitch in a range of forty to eighty micrometers.
In an analogous art, Sundaram teaches in Fig. 3 and paragraph [0063] a via stack (110, 140) has a pitch in a range of forty to eighty micrometers {pitch of 3-50 micrometers}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chung’s semiconductor device package as modified by Chen based on the teachings of Sundaram – such that the via stack has a pitch in a range of forty to eighty micrometers – so ultra-small through vias … can be defined within the interposer … such that each of the through vias … extends from the first side … to the second side … of the interposer. Sundaram [0063]. Moreover, all the claimed elements (e.g., via stack, pitch) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Sundaram) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. MPEP §2144.05(I).
Regarding claim 8, Chung as modified by Chen teaches the semiconductor device package of claim 1, but Chung does not teach wherein individual vias of the via stack have a size in a range of ten to forty micrometers.
Sundaram teaches in Fig. 3 and paragraph [0063] that individual vias (110) of a via stack (110, 140) have a size in a range of ten to forty micrometers (diameter of 1-25 micrometers). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chung’s semiconductor device package as modified by Chen based on the teachings of Sundaram – such that individual vias of the via stack have a size in a range of ten to forty micrometers – so ultra-small through vias … can be defined within the interposer … such that each of the through vias … extends from the first side … to the second side … of the interposer. Sundaram [0063]. Moreover, all the claimed elements (e.g., vias, via stack, size) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Sundaram) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. MPEP §2144.05(I).
Regarding claim 16, Chung as modified by Chen teaches the method of claim 10, but Chung does not teach wherein the via stack has a pitch in a range of forty to eighty micrometers.
Sundaram teaches in Fig. 3 and paragraph [0063] a via stack (110, 140) has a pitch in a range of forty to eighty micrometers {pitch of 3-50 micrometers}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chung’s method as modified by Chen based on the teachings of Sundaram – such that the via stack has a pitch in a range of forty to eighty micrometers – so ultra-small through vias … can be defined within the interposer … such that each of the through vias … extends from the first side … to the second side … of the interposer. Sundaram [0063]. Moreover, all the claimed elements (e.g., via stack, pitch) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Sundaram) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. MPEP §2144.05(I).
Regarding claim 17, Chung as modified by Chen teaches the method of claim 10, but Chung does not teach wherein individual vias of the via stack have a size in a range of ten to forty micrometers.
Sundaram teaches in Fig. 3 and paragraph [0063] that individual vias (110) of a via stack (110, 140) have a size in a range of ten to forty micrometers (diameter of 1-25 micrometers). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chung’s method as modified by Chen based on the teachings of Sundaram – such that individual vias of the via stack have a size in a range of ten to forty micrometers – so ultra-small through vias … can be defined within the interposer … such that each of the through vias … extends from the first side … to the second side … of the interposer. Sundaram [0063]. Moreover, all the claimed elements (e.g., vias, via stack, size) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Sundaram) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. MPEP §2144.05(I).
Claim(s) 9 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of Chen as applied to claim 1 (for claim 9) and claim 10 (for claim 18) above, and further in view of Majhi et al. (US20250112205A1).
Regarding claim 9, Chung as modified by Chen teaches the semiconductor device package of claim 1, but Chung does not teach wherein the packaging laminate substrate further includes a plurality of peripheral stack vias configured to supply power and input-output routing to the system on chip and the functional chip.
In an analogous art, Majhi teaches in Fig. 2G and paragraph [0049] a plurality of peripheral stack vias (287) configured to supply power and input-output routing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chung’s semiconductor device package as modified by Chen based on the teachings of Majhi – such that Chung’s modified packaging laminate substrate further includes a plurality of peripheral stack vias configured to supply power and input-output routing to Chung’s system on chip and Chung’s functional chip – so [t]he redistribution layer region … can further provide the routing of power and ground signals to the integrated circuit dies. Majhi [0049]. Moreover, all the claimed elements (e.g., stack vias) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Majhi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
The Office further notes that the recitation of “configured to supply power and input-output routing” is directed to a manner in which the claimed subject matter is intended to be employed and, accordingly, does not structurally distinguish the claimed invention from the prior art. MPEP §2114(II) – a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Still further, the Office notes that every conductor is implicitly “configured to supply power and input-output routing.”
Regarding claim 18, Chung as modified by Chen teaches the method of claim 10, but Chung does not teach wherein the packaging laminate substrate further includes a plurality of peripheral stack vias configured to supply power and input-output routing to the system on chip and the functional chip.
Majhi teaches in Fig. 2G and paragraph [0049] a plurality of peripheral stack vias (287) configured to supply power and input-output routing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chung’s method as modified by Chen based on the teachings of Majhi – such that Chung’s modified packaging laminate substrate further includes a plurality of peripheral stack vias configured to supply power and input-output routing to Chung’s system on chip and Chung’s functional chip – so [t]he redistribution layer region … can further provide the routing of power and ground signals to the integrated circuit dies. Majhi [0049]. Moreover, all the claimed elements (e.g., stack vias) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Majhi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
The Office notes that every conductor is implicitly “configured to supply power and input-output routing.”
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of Shim et al. (US20190103432A1) and Chen.
Regarding claim 19, Chung teaches in Fig. 7 a system, comprising:
a semiconductor device package (13) {[0034]}, wherein the semiconductor device package (13) includes:
a system on chip (201) {[0034]};
a functional chip (301) connected to the system on chip (201) by a packaging laminate substrate (101) positioned between the system on chip (201) and the functional chip (301) {[0034]}; and
an additional functional chip (202) mounted on and bonded to the system on chip (201) {[0067]}.
Chung does not teach a display device; and a semiconductor device package configured to process images rendered to the display device.
In an analogous art, Shim teaches a display device (1020) {Fig. 16; [0080]}; and a semiconductor device package (1) configured to process images rendered to the display device (1020) {Figs. 1, 16; [0025, 0078]}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chung’s system based on the teachings of Shim – to include a display device; and a semiconductor device package configured to process images rendered to the display device – for communicating processed imagery to a display for viewing by a user. Shim [0028]. Moreover, all the claimed elements (e.g., semiconductor device package, display device) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Shim) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Chung as modified by Shim does not teach a via stack included in a packaging laminate substrate, though Chung implicitly does so in paragraph [0034].
In an analogous art, Chen teaches in Figs. 2A and 2B and paragraphs [0063, 0065] a via stack (e.g., 242-244) included in a packaging laminate substrate (240). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chung’s system as modified by Shim based on the teachings of Chen – such that a via stack is included in a packaging laminate substrate – to provide electrical communication between the components disposed on two sides thereof. Chung [0034]. Moreover, all the claimed elements (e.g., via stack, packaging laminate substrate) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Chen) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of Shim and Chen as applied to claim 19 above, and further in view of Ye.
Regarding claim 20, Chung as modified by Shim and Chen teaches the system of claim 19, but Chung does not teach wherein the additional functional chip is mounted back to back on the system on chip by an adhesive and bonded to the system on chip by wire bonding.
Ye teaches in Fig. 3A and paragraph [0022, 0023] an additional functional chip (22) is mounted back to back on a first chip (18) by an adhesive (20) and bonded to the first chip (18) by wire bonding (26). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chung’s system as modified by Shim and Chen based on the teachings of Ye – such that Chung’s additional functional chip is mounted back to back on Chung’s system on chip by an adhesive and bonded to Chung’s system on chip by wire bonding – to form a stacked assembly … [and so] [e]lectrical connections may be made between the two microelectronic package assemblies, by electrically connecting or linking contacts on a first substrate of one microelectronic package with contacts on a second substrate of the other microelectronic package. Ye [0011]. Moreover, all the claimed elements (e.g., multiple chips, adhesive, wire bonding) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Ye) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee et al. (US20190238134A1) teaches a chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.
Conclusion
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891