DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 5-7 and 12-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al, US Patent Application Publication 2020/0118908
Regarding claim 1, Yu teaches a semiconductor device comprising:
a logic die (Tier1) including a circuit L1 or L2 and a memory M1 and
a plurality of memory dies Tier1, Tier2, including an additional memory M2, M3, M4; wherein the logic die and the plurality of memory dies are stacked three-dimensionally using face-to-face hybrid bonds [0018] that provide non-uniform access to the additional memory by the circuit (figure 8 and [0017])
Regarding claim 5, Yu teaches the non-uniform access is implemented using direct flip-flop to flip-flop connections across dies (figure 8).
Regarding claims 6-7, Yu teaches the additional memory includes a first type of additional memory and a second type of additional memory, wherein the first type of additional memory corresponds to static random access memory and the second type of additional memory corresponds to wide input-output dynamic random access memory [0018]
Regarding claim 12, Yu teaches a method comprising: providing a logic die (Tier1) including a circuit L1 or L2 and a memory M1;
providing a plurality of memory dies Tier1, Tier2, including an additional memory M2, M3, M4; and stacking the logic die and the plurality of memory dies three-dimensionally using face- to-face hybrid bonds [0018] that provide non-uniform access to the additional memory by the circuit (figure 8 and [0017]).
Regarding claim 13, Yu teaches implementing the non-uniform access using direct flip-flop to flip-flop connections across dies (Figure 8).
Regarding claims 14-15, Yu teaches in the additional memory a first type of additional memory and a second type of additional memory, wherein the first type of additional memory corresponds to static random access memory and the second type of additional memory corresponds to wide input-output dynamic random access memory [0018].
Claim(s) 1, 5, 12 and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al, US Patent 9,190,345.
Regarding claim 1, Chen teaches a semiconductor device comprising:
a logic die 130 including a circuit 104 or 102 and a memory 102 or 104; and
a plurality of memory dies 130” , 130” including an additional memory; wherein the logic die and the plurality of memory dies are stacked three-dimensionally using face-to-face hybrid bonds 132 (column 9, lines 19-21) that provide non-uniform access to the additional memory by the circuit (figure 6 and column 9, lines 35-50, which teaches that 104,102,132,134,132’134’ may be comprises logic circuits, memory circuits, and other circuits)
Regarding claim 5, Chen teaches the non-uniform access is implemented using direct flip-flop to flip-flop connections across dies (figure 6).
Regarding claim 12, Chen teaches a method comprising: providing a logic die 130 including a circuit 104 or 102 and a memory 102 or 104; providing a plurality of memory dies 130”, 130’ including an additional memory; and stacking the logic die and the plurality of memory dies three-dimensionally using face- to-face hybrid bonds 132 (column 9, lines 19-21) that provide non-uniform access to the additional memory by the circuit (figure 6 and column 9, lines 35-50, which teaches that 104,102,132,134,132’134’ may be comprises logic circuits, memory circuits, and other circuits).
Regarding claim 13, Chen teaches implementing the non-uniform access using direct flip-flop to flip-flop connections across dies (Figure 6).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4, 8-11, 16, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al, US Patent Application Publication 2020/0118908 or Chen et al, US Patent 9,190,345
Regarding claim 2, Yu and Chen teach the non-uniform access allows one or more subsystem of the circuit to have equal bandwidth access to a plurality of memory banks of the additional memory but with a reduced latency in accessing one or more memory banks of the plurality of memory banks compared to a latency in accessing one or more other memory banks of the plurality of memory banks.
Note: [0017] of Applicant’s originally-filed Application states that this function is a product of using face-to-face bonding that provides uniform access using direct flipflop to flip-flop connection across the dies. MPEP 2112.01 stated that when the structure recited is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. Therefore, these limitations are held to be a matter of obviousness. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best.
Regarding claim 3, Yu and Chen teach a first latency experienced by a subsystem of the circuit in accessing a memory bank of the additional memory that is a first number of router hops away from the subsystem is less than a second latency experienced by the subsystem in accessing an additional memory bank of the additional memory that is a second number of router hops away from the subsystem, wherein the first number of router hops is less than the second number of router hops.
However, these claim are directed towards the functionality, rather than structure. Note: MPEP 2112.01 stated that when the structure recited is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. Therefore, these limitations in this are held to be a matter of obviousness since the claim does not explicitly recite structure that meets this function limitation. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best.
Regarding claim 4, Yu and Chen teach a first set of energy, latency, and bandwidth experienced by a subsystem of the circuit in accessing a first memory bank of the additional memory that is a given number of router hops away from the subsystem is equal to a second set of energy, latency, and bandwidth experienced by the subsystem in accessing a second memory bank of the additional memory that is the given number of router hops away from the subsystem regardless of whether a first plurality of routers used to access the first memory bank and a second plurality of routers used to access the second memory bank are implemented on a same die, on different dies, or combinations thereof.
However, these claim are directed towards the functionality, rather than structure. Note: MPEP 2112.01 stated that when the structure recited is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. Therefore, these limitations in this are held to be a matter of obviousness since the claim does not explicitly recite structure that meets this function limitation. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best.
Regarding claims 8-9, Yu and Chen fail to teach the additional memory has a memory capacity no greater than twenty-five megabytes, the first type of additional memory comprises no more than fifty percent of the additional memory, and the second type of additional memory comprises no more than fifty percent of the additional memory and the additional memory has a memory capacity no less than twenty-five megabytes, the first type of additional memory comprises no more than twenty-five percent of the additional memory, and the second type of additional memory comprises no more than seventy-five percent of the additional memory.
However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claims 10-11, Yu and Chen fail to teach the first type of additional memory and the second type of additional memory are determined by comparing different memory settings according to a metric that evaluates power improvement with respect to area footprint and a partition of the first type of additional memory and the second type of additional memory is determined by comparing different partitions according to a metric that evaluates power consumption with respect to memory capacity.
However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claims 16 and 17, Yu and Chen fail to teach selecting the first type of additional memory and the second type of additional memory by comparing different memory settings according to a metric that evaluates power improvement with respect to area footprint: selecting a partition of the first type of additional memory and the second type of additional memory by comparing different partitions according to a metric that evaluates power consumption with respect to memory capacity.
However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al, US Patent Application Publication 2020/0118908 in view of Kwon, US Patent 9,984,032.
Regarding claim 18, Yu teaches a device and a semiconductor device, wherein the semiconductor device includes: a logic die (Tier1) including a circuit L1 of L2 and a memory M1; and a plurality of memory dies Tier2,Tier 3 including an additional memory M2, M3, M4, wherein the logic die and the plurality of memory dies are stacked three- dimensionally using face-to-face hybrid bonds [0018] that provide non-uniform access to the additional memory by the circuit (figure 8 and [0017])
Yu fails to teach the device is a display device, wherein the semiconductor device configured to process images rendered to the display device,
However, Kwon teaches several generally-known electronic components that uses stacked dies configured to process images rendered to the display device, such as smart phones, digital cameras, and digital video camera (column 5, lines 21-30)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kwon with that of Yu because it is generally known in the art that electronic components that uses stacked dies configured to process images rendered to the display device, which allows the electronic device to work.
Regarding claims 19-20, Yu teaches the additional memory includes a first type of additional memory and a second type of additional memory, wherein the first type of additional memory corresponds to static random access memory and the second type of additional memory corresponds to wide input-output dynamic random access memory [0018].
Conclusion
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/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899