DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5, 6, 11, 15, and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kao et al, US Patent Application Publication 2021/0391302
Regarding claim 1, Kao teaches a semiconductor device comprising:
a first die 106 including a driver gate configured to drive a first via ladder coupled to a first top metal layer;
and a second die 104 including a load gate coupled to a second via ladder coupled to a second top metal layer, wherein the first die and the second die are stacked three-dimensionally using face-to- face hybrid bonds to couple the first top metal layer to the second top metal layer (figure 1, as labeled below).
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Regarding claims 5-6, Kao teaches a network on chip in the first die connects partitioned subsystems of a circuit of the semiconductor device and cross die data communication by the network on chip has a bit width matched to a pin density of the face-to- face hybrid bonds 122, wherein all circuit drivers of the circuit correspond to standard cell drivers (figure 1).
Regarding claim 11, Kao teaches a method comprising of providing a first die 106 including a driver gate configured to drive a first via ladder coupled to a first top metal layer; providing a second die 104 including a load gate coupled to a second via ladder coupled to a second top metal layer; and stacking the first die and the second die three-dimensionally using face-to-face hybrid bonds to couple the first top metal layer to the second top metal layer (figure 1, as labeled above).
Regarding claims 15-16, Kao teaches a network on chip in the first die connects partitioned subsystems of a circuit of a semiconductor device and cross die data communication by the network on chip has a bit width matched to a pin density of the face-to- face hybrid bonds 122, wherein all circuit drivers of the circuit correspond to standard cell drivers (figure 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kao et al, US Patent Application Publication 2021/0391302 in view of Pratt, US Patent 7,800,238.
Regarding claim 20, Kao teaches a system comprising a semiconductor device includes: a first die 104 including a driver gate configured to drive a first via ladder coupled to a first top metal layer; and a second die 106 including a load gate coupled to a second via ladder coupled to a second top metal layer, wherein the first die and the second die are stacked three-dimensionally using face-to-face hybrid bonds to couple the first top metal layer to the second top metal layer (figure 1, as labeled above).
Kao fails to teach a display device; and a semiconductor device configured to process images rendered to the display device.
However, Pratt teaches that display devices are one of several electrical components that uses a three-dimension chip stack (see column 7, line 67). Therefore, the reference of Pratt then teaches the limitations of “a display device; and a semiconductor device configured to process images rendered to the display device”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Pratt with that of Kao because display devices are one of several electrical components that uses a three-dimension chip stack.
Allowable Subject Matter
Claims 2-4 , 7-10, 12-14 and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOVAUNDA JEFFERSON whose telephone number is (571)272-5051. The examiner can normally be reached M-F 7AM-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale E Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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QVJ
/DALE E PAGE/ Supervisory Patent Examiner, Art Unit 2899
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