DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I in the reply filed on 05/28/2026 is acknowledged. The traversal is on the ground(s) that the Groups I, II, and III share substantial overlap in subject matter and they recite the same structural elements. This is found persuasive because the three groups share a substantial overlap in subject matter. The restriction requirements have been withdrawn and claims 1-20 have been examined.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 11, 12, and 18 - 20 recites “a memory die including an additional memory having a same footprint as the circuit and memory in the logic die”. It is unclear if “a memory die having a same footprint as the logic die” or “an additional memory having a same foot print as combined footprint of the circuit and memory”. For purpose of examination, the Examiner interprets this as the logic die and memory dies having the same footprint.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 10 - 12, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Norman et al. (US20210265308A1; hereinafter Norman).
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Norman: FIG. 1
Regarding Claim 1, Norman discloses a semiconductor device (a multi-die QV memory module 100, FIG. 1 reproduced above, [0024]) comprising:
a logic die (controller die 102) including a circuit and a memory, FIG. 1, [0026], [0032]. Norman [0026] discloses the controller die 102 includes a memory controller which includes controller logic circuitry. Norman [0032] discloses the memory controller die may incorporate high speed SRAM. Therefore, the logic die 102 includes a circuit and a memory.
a memory die (memory die 101) including an additional memory (memory die 101 includes memory arrays, [0027]) having a same footprint as the circuit and memory in the logic die, FIG. 1, [0032].
Norman [0032] discloses the memory dies and the controller have substantially the same silicon areas, so that signaling can be achieved over short conductors, which avoids interconnection delays, indicating the memory die and the logic die may have the same footprint.
wherein the logic die (102) and the memory die (101) are stacked three-dimensionally with die-to-die data communication between the circuit and the additional memory by face-to-face hybrid bonds, FIG. 1, [0024].
Norman [0032] discloses the memory die 101 and the controller die 102 are interconnected by copper interconnect conductors (“hybrid bonds” or “studs”) 106 and the copper studs are used in a flip chip bonding method to connect the memory die to the controller die. This indicates the memory die and controller die are stacked and have die-die-data communication between the circuit in the logic die and the additional memory in the memory die by face-to-face hybrid bonds.
Regarding Claim 10, Norman discloses the semiconductor device of claim 1, wherein the face-to-face hybrid bonds (hybrid bonds 106) are positioned directly atop a macro (memory die 101 includes memory arrays organized as a 2-dimensional array of “tiles”) of the additional memory (memory die 101), [0025], [0026].
Norman [0026] discloses on controller die 102, a memory controller for accessing the memory arrays of memory die 101 is formed. The tile-based design of the memory die 101 naturally results in a modular organization of hybrid bonds to controller die 102, which leads to modularization of controller circuitry also, indicating the hybrid bonds may be organized corresponding to the memory tiles (macros) of the additional memory.
Regarding Claim 11, Norman discloses the semiconductor device of claim 1, further comprising:
an additional memory die (301a) including a further memory (memory arrays) having a same footprint as the circuit and memory in the logic die (302), FIGS. 1 & 3, [0032], [0035].
Norman [0032] discloses controller dies include logic circuitry and high speed SRAM. Norman [0032] discloses the memory dies and the controller have substantially the same silicon areas, so that signaling can be achieved over short conductors, which avoids interconnection delays, indicating the memory die and the logic die may have the same footprint.
wherein the logic die (302) and the additional memory die (301a) are stacked three-dimensionally with die-to-die data communication between the circuit and the further memory by a face-to-back through silicon via, FIG. 3, [0035].
Norman [0035] discloses a combination of hybrid bonds and TSVs route signals exchanged between controller 302 and each memory die. This indicates the die-to-die data communication between the circuit and the further memory may be implemented through a face-to-back through silicon via.
Regarding Claim 12, Norman discloses a method comprising:
providing a logic die (controller die 102) including a circuit and a memory, FIG. 1, [0026], [0032]. Norman [0026] discloses the controller die 102 includes a memory controller which includes controller logic circuitry. Norman [0032] discloses the memory controller die may incorporate high speed SRAM. Therefore, the logic die 102 includes a circuit and a memory.
providing a memory die (memory die 101) including an additional memory (memory die 101 includes memory arrays, [0027]) having a same footprint as the circuit and memory in the logic die, FIG. 1, [0032].
Norman [0032] discloses the memory dies and the controller have substantially the same silicon areas, so that signaling can be achieved over short conductors, which avoids interconnection delays, indicating the memory die and the logic die may have the same footprint.
stacking the logic die (102) and the memory die (101) are stacked three-dimensionally with die-to-die data communication between the circuit and the additional memory by face-to-face hybrid bonds, FIG. 1, [0024].
Norman [0032] discloses the memory die 101 and the controller die 102 are interconnected by copper interconnect conductors (“hybrid bonds” or “studs”) 106 and the copper studs are used in a flip chip bonding method to connect the memory die to the controller die. This indicates the memory die and controller die are stacked and have die-die-data communication between the circuit in the logic die and the additional memory in the memory die by face-to-face hybrid bonds.
Regarding Claim 18, Norman discloses the method of claim 12, further comprising:
providing an additional memory die (301a) including a further memory (memory arrays) having a same footprint as the circuit and memory in the logic die (302), FIGS. 1 & 3, [0032], [0035].
Norman [0032] discloses controller dies include logic circuitry and high speed SRAM. Norman [0032] discloses the memory dies and the controller have substantially the same silicon areas, so that signaling can be achieved over short conductors, which avoids interconnection delays, indicating the memory die and the logic die may have the same footprint.
stacking the logic die (302) and the additional memory die (301a) three-dimensionally with die-to-die data communication between the circuit and the further memory by a face-to-back through silicon via, FIG. 3, [0035].
Norman [0035] discloses a combination of hybrid bonds and TSVs route signals exchanged between controller 302 and each memory die. This indicates the die-to-die data communication between the circuit and the further memory may be implemented through a face-to-back through silicon via.
Claims 2, 9, 13, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Norman in view of Malladi et al. (US20200356488A1; hereinafter Malladi).
Regarding Claim 2, Norman discloses the semiconductor device of claim 1.
Norman does not explicitly disclose “wherein the die-to-die data communication by the face-to-face hybrid bonds occurs by a first connection channel having a first bandwidth and a second connection channel having a second bandwidth lower than the first bandwidth.”
In a similar art, Malladi discloses a high bandwidth memory system 100 including a plurality of stacked DRAM dies 110 stacked on top of the logic die 120, FIG. 1, [0040].
Malladi [0042] discloses the interface between the memory stack and the host processor 140 includes a plurality of channels 130. Malladi [0046] discloses the channels 130 may operate as a 128-bit channel or 64-bit channels or 32-bit channels.
The combination of Norman and Malladi discloses: wherein the die-to-die data communication by the face-to-face hybrid bonds (Norman: hybrid bonds between memory die 101 and logic die 102) occurs by a first connection channel having a first bandwidth (Malladi: channels 130 operating as a 128-bit channels) and a second connection channel having a second bandwidth lower than the first bandwidth (Malladi: channels 130 operating as a 64-bit channels).
Malladi discloses that a device as taught increases the number of effective channels and can result in greater bandwidth utilization [0043]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Norman’s device in order to increase the number of effective channels and can result in greater bandwidth utilization as disclosed by Malladi [0043].
Regarding Claim 9, The combination of Norman and Malladi discloses the semiconductor device of claim 2.
The combination of Norman and Malladi discloses: wherein the first connection channel (Malladi: channels 130 operating as a 128-bit channels) is connected to internal wires of the circuit (Norman: controller circuit 814) through local three-dimensional wires (Norman: through silicon vias 830, FIG. 8, [0051]).
Malladi discloses that a device as taught enables greater bandwidth utilization [0043]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Norman’s device in order to enable greater bandwidth utilization [0043].
Regarding Claim 13, Norman discloses the method of claim 12.
Norman does not explicitly disclose “wherein the die-to-die data communication by the face-to-face hybrid bonds occurs by a first connection channel having a first bandwidth and a second connection channel having a second bandwidth lower than the first bandwidth.”
Malladi [0042] discloses the interface between the memory stack and the host processor 140 includes a plurality of channels 130. Malladi [0046] discloses the channels 130 may operate as a 128-bit channel or 64-bit channels or 32-bit channels.
The combination of Norman and Malladi discloses: wherein the die-to-die data communication by the face-to-face hybrid bonds (Norman: hybrid bonds between memory die 101 and logic die 102) occurs by a first connection channel having a first bandwidth (Malladi: channels 130 operating as a 128-bit channels) and a second connection channel having a second bandwidth lower than the first bandwidth (Malladi: channels 130 operating as a 64-bit channels).
Malladi discloses that a method as taught increases the number of effective channels and can result in greater bandwidth utilization [0043]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Norman’s device in order to increase the number of effective channels and can result in greater bandwidth utilization as disclosed by Malladi [0043].
Regarding Claim 17, The combination of Norman and Malladi discloses the method of claim 13.
The combination of Norman and Malladi discloses:
wherein at least one of:
the second connection channel is connected to top input-output ports of the circuit through a protocol managed interface;
the first connection channel (Malladi: channels 130 operating as a 128-bit channels) is connected to internal wires of the circuit (Norman: controller circuit 814) through local three-dimensional wires (Norman: through silicon vias 830, FIG. 8, [0051]); or
the face-to-face hybrid bonds are positioned directly atop a macro of the additional memory.
Malladi discloses that a method as taught enables greater bandwidth utilization [0043]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Norman’s device in order to enable greater bandwidth utilization [0043].
Claims 3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Norman in view of Malladi further in view of Quader et al. (US20200243486A1; hereinafter Quader).
Regarding Claim 3, The combination of Norman and Malladi discloses the semiconductor device of claim 2.
The combination of Norman and Malladi does not disclose “wherein accesses of the first connection channel and the second connection channel to memory banks of the additional memory are controlled by a configuration register that governs a partition of the additional memory.”
In a similar art, Quader discloses a system 400, in which a memory circuit 401 is wafer-bonded to FPGA circuit 402, FIG.4a, [0089].
Quader [0093] discloses the quasi-volatile memory (QVM) portion 401b of the memory circuit 401 is segmented into memory segments 421-1, 421-2, . . . , and 421-n, respectively serving corresponding segments of programmable logic (“tile cells”) 422-1, 422-2, . . . , and 422-n over data buses 423-1, 423-2, . . . , and 423-n.
Quader discloses: wherein accesses of the first connection channel and the second connection channel (data buses 423-1, 423-2, . . . , and 423-n) to memory banks (memory segments 421-1, 421-2, … 421-n) of the additional memory (401) are controlled by a configuration register (configuration cells 370) that governs a partition (memory segmentation) of the additional memory (401), FIG. 4b, [0068], [0093].
Quader [0093] discloses the memory segmentation may be configured using a configuration scheme similar to FIG. 1f. Quader ( FIG. 1f, [0068]) discloses configuration cells 370 may be provided to set one of various organizations of the memory tiles. Therefore, the configuration cells 370 correspond to the configuration register that governs a partition (memory segmentation) of the additional memory 401.
Quader discloses that a device as taught allows the memory circuit to be configured in flexible ways to improve efficiency and adaptability for various applications [0091]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Norman and Malladi’s device in order to improve efficiency and adaptability for various applications as disclosed by Quader [0091].
Regarding Claim 8, The combination of Norman and Malladi discloses the semiconductor device of claim 2.
The combination of Norman, Malladi, and Quader discloses: wherein the second connection channel (Malladi: channels 130 operating as a 64-bit channels) is connected to top input-output ports (Quader: external interface 111) of the circuit (controller circuit 102) through a protocol managed interface (Quader: memory bus conforming to an industry standard, such as DDR4, DDRS and PCIe, FIG. 2, [0078]).
Quader discloses that a device as taught provides the connection channel with an interface protocol conforming to the industry standard [0078]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Norman and Malladi’s device in order to provide the communication channel with an interface protocol conforming to the industry standard as disclosed by Quader [0078].
Claims 4 – 6, 14, and 15 are is rejected under 35 U.S.C. 103 as being unpatentable over Norman in view of Malladi further in view of Quader, still further in view of Mathuriya et al. (US11836102B1; hereinafter Mathuriya).
Regarding Claim 4, The combination of Norman, Malladi, and Quader discloses the semiconductor device of claim 3.
The combination of Norman, Malladi, and Quader does not explicitly disclose “wherein the configuration register governs storage of data types in partitions of the additional memory.”
In a similar art, Mathuriya discloses a computer architecture 500 including a top die (compute die) and a bottom die (memory die), FIG. 5, [col. 19, line 60].
Mathuriya [col. 19, line 63] discloses the bottom die 501 includes a segment of memory to store weights 501a and a segment of memory to store input and /or outputs 501b. The memories 501a and/or 501b can be a single continuous memory that is partitioned into partitions 501a and 501b, FIG. 5.
Mathuriya discloses: wherein the configuration register (configuration registers internal to AI core 725 accessed via CSB725b) governs storage of data types (501a stores weights, 501b stores input and/or outputs) in partitions (partitions 501a, 501b) of the additional memory (501). FIG. 7, [col. 22, line 1], [col. 21, line 56].
Mathuriya [col. 22, line 1] discloses the AI core 725 includes I/O interfaces 725a/b to communicate with microcontroller 724. Mathuriya [col. 22, line 6] discloses the configuration space bus (CSB) 725b passes the configuration setting for each AI Core and allows access to configuration registers internal to compute core 725. Mathuriya [col. 21, line 56] discloses the microcontroller 724 directly communicates with a memory of a memory tile to perform read/write operations. This indicates the AI core 725 which includes a configuration register communicates to the microcontroller 724 and may govern the storage of data types 501a and 501b in partitions in the memory.
Mathuriya discloses that a device as taught including storage of data types in partitions improves computational efficiency [col. 8, line 27]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Norman, Malladi, and Quader’s device in order to improve computational efficiency as disclosed by Mathuriya [col. 8, line 27].
Regarding Claim 5, The combination of Norman, Malladi, Quader, and Mathuriya discloses the semiconductor device of claim 4.
Quader discloses: wherein the circuit (custom logic circuits 424-2, 423-3, . . . , and 424-(n−1)) corresponds to a processor (RISC-type processor) of a neural network accelerator (a neural network application implemented by the configuration), [0095].
Quader discloses that a device as taught enables implementation of a configuration for neural network application [0095]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device in order to enable implementation of a configuration for neural network application as disclosed by Quader [0095].
Regarding Claim 6, The combination of Norman, Malladi, Quader, and Mathuriya discloses the semiconductor device of claim 5.
Mathuriya discloses: wherein the configuration register (configuration registers internal to AI core 725) triggers (communicates with microcontroller 724 which communicates with a memory to perform read/write operations) storage of weights in a first partition (weights stored in memory partition 501a) of the additional memory (501) and storage of activations in a second partition (I/O buffer stored in memory partition 501b) of the additional memory (501), FIG. 5, [col. 19, line 63], [col. 21, line 56], [col. 22, line 1].
Mathuriya discloses that a device as taught improves the efficiency of the matrix multiplication operations [col. 20, line 32]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device in order to improve the efficiency of the matrix multiplication operations as disclosed by Mathuriya [col. 20, line 32].
Regarding Claim 14, The combination of Norman and Malladi discloses the method of claim 13.
The combination of Norman and Malladi does not disclose “wherein accesses of the first connection channel and the second connection channel to memory banks of the additional memory are controlled by a configuration register that governs a partition of the additional memory; the configuration register governs storage of data types in partitions of the additional memory.”
Quader [0093] discloses the quasi-volatile memory (QVM) portion 401b of the memory circuit 401 is segmented into memory segments 421-1, 421-2, . . . , and 421-n, respectively serving corresponding segments of programmable logic (“tile cells”) 422-1, 422-2, . . . , and 422-n over data buses 423-1, 423-2, . . . , and 423-n.
Quader discloses: wherein accesses of the first connection channel and the second connection channel (data buses 423-1, 423-2, . . . , and 423-n) to memory banks (memory segments 421-1, 421-2, … 421-n) of the additional memory (401) are controlled by a configuration register (configuration cells 370) that governs a partition (memory segmentation) of the additional memory (401), FIG. 4b, [0068], [0093].
Quader [0093] discloses the memory segmentation may be configured using a configuration scheme similar to FIG. 1f. Quader ( FIG. 1f, [0068]) discloses configuration cells 370 may be provided to set one of various organizations of the memory tiles. Therefore, the configuration cells 370 corresponds to the configuration register that governs a partition (memory segmentation) of the additional memory 401.
Mathuriya [col. 19, line 63] discloses the bottom die 501 includes a segment of memory to store weights 501a and a segment of memory to store input and/or output 501b. The memories 501a and/or 501b can be a single continuous memory that is partitioned into partitions 501a and 501b, FIG. 5.
Mathuriya discloses: wherein the configuration register (configuration registers internal to AI core 725 accessed via CSB725b) governs storage of data types (501a stores weights, 501b stores input and/or outputs) in partitions (partitions 501a, 501b) of the additional memory (501). FIG. 7, [col. 22, line 1], [col. 21, line 56].
Mathuriya [col. 22, line 1] discloses the AI core 725 includes I/O interfaces 725a/b to communicate with microcontroller 724. Mathuriya [col. 22, line 6] discloses the configuration space bus (CSB) 725 b passes the configuration setting for each AI Core and allows access to configuration registers internal to compute core 725. Mathuriya [col. 21, line 56] discloses the microcontroller 724 directly communicates with a memory of a memory tile to perform read/write operations. This indicates the AI core 725 which includes a configuration register communicates to the microcontroller 724 and may govern the storage of data types 501a and 501b in partitions in the memory.
Mathuriya discloses that a method as taught including storage of data types in partitions improves computational efficiency [col. 8, line 27]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device in order to improve computational efficiency as disclosed by Mathuriya [col. 8, line 27].
Regarding Claim 15, The combination of Norman, Malladi, Quader, and Mathuriya discloses the method of claim 14.
The combination of Norman and Malladi does not disclose “wherein the circuit corresponds to a processor of a neural network accelerator, the configuration register triggers storage of weights in a first partition of the additional memory and storage of activations in a second partition of the additional memory.”
Quader discloses: wherein the circuit (custom logic circuits 424-2, 423-3, . . . , and 424-(n−1)) corresponds to a processor (RISC-type processor) of a neural network accelerator (a neural network application implemented by the configuration), [0095].
Mathuriya discloses: wherein the configuration register (configuration registers internal to AI core 725) triggers (communicates with microcontroller 724 which communicates with a memory to perform read/write operations) storage of weights in a first partition (weights stored in memory partition 501a) of the additional memory (501) and storage of activations in a second partition (I/O buffer stored in memory partition 501b) of the additional memory (501), FIG. 5, [col. 19, line 63], [col. 21, line 56], [col. 22, line 1].
Mathuriya discloses that a method as taught improves the efficiency of the matrix multiplication operations [col. 20, line 32]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device in order to improve the efficiency of the matrix multiplication operations as disclosed by Mathuriya [col. 20, line 32].
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Norman in view of Malladi further in view of Quader, still further in view of Mathuriya, yet still further in view of Henderson et al. (US20210373790A1; hereinafter Henderson).
Regarding Claim 7, The combination of Norman, Malladi, Quader, and Mathuriya discloses the semiconductor device of claim 4.
The combination of Norman, Malladi, and Quader does not disclose “wherein the circuit is configured to set the configuration register to select the partition and two or more data types based on pre-profiled characteristics of a workload.”
Mathuriya [col. 19, line 63] discloses the bottom die 501 includes a segment of memory to store weights 501a and a segment of memory to store input and/or
outputs 501b. The memories 501a and/or 501b can be a single continuous memory that is partitioned into partitions 501a and 501b, FIG. 5.
Mathuriya [col. 22, line 1] discloses the AI core 725 includes I/O interfaces 725a/b to communicate with microcontroller 724. Mathuriya [col. 22, line 6] discloses the configuration space bus (CSB) 725b passes the configuration setting for each AI Core and allows access to configuration registers internal to compute core 725. Mathuriya [col. 21, line 56] discloses the microcontroller 724 directly communicates with a memory of a memory tile to perform read/write operations. Therefore, the AI core 725 may be configured to set the configuration register to select the partition (501a, 501b) and two or more data types (weights and input/output).
Mathuriya does not disclose “selection of the partition and two or more data types based on pre-profiled characteristics of a workload.”
In a similar art, Henderson discloses a method of processing data with a compute core on an enhanced memory module [0085].
Henderson FIG. 2, [0087] discloses the requestor (208) queries an accelerator runtime application (210) to determine how many enhanced memory modules are configured in the system as well as how much memory on those enhanced memory modules is allocated to running acceleration-based workloads. The accelerator runtime application (210) may then query an accelerator driver (216) to get this information. With this information, the requestor (208) can determine if the workload can fit within the configured amount of memory and execute the workload accordingly. In the event that the amount of memory available is insufficient for the workload, the requestor may reconfigure the workload, such as reducing its size or chunking the workload, so that the available memory may be utilized. Therefore, Henderson discloses memory utilization based on workload characteristics.
The combination of Norman, Malladi, Quader, Mathuriya, and Henderson discloses: wherein the circuit (725) is configured to set the configuration register (configuration registers internal to AI core 725 accessed via CSB725b) to select the partition (partitions 501a, 501b) and two or more data types (I/O buffers and weights) based on pre-profiled characteristics of a workload (Henderson: based on workload characteristics, [0087]).
Henderson discloses that a device as taught enhances memory utilization of the device [0087]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device in order to enhance memory utilization as disclosed by Henderson [0087].
Regarding Claim 16, The combination of Norman, Malladi, Quader, and Mathuriya discloses the method of claim 14.
The combination of Norman, Malladi, and Quader does not disclose “wherein the circuit is configured to set the configuration register to select the partition and two or more data types based on pre-profiled characteristics of a workload.”
Mathuriya [col. 19, line 63] discloses the bottom die 501 includes a segment of memory to store weights 501a and a segment of memory to store input and/or outputs 501b. The memories 501a and/or 501b can be a single continuous memory that is partitioned into partitions 501a and 501b, FIG. 5.
Mathuriya [col. 22, line 1] discloses the AI core 725 includes I/O interfaces 725a/b to communicate with microcontroller 724. Mathuriya [col. 22, line 6] discloses the configuration space bus (CSB) 725 b passes the configuration setting for each AI Core and allows access to configuration registers internal to compute core 725. Mathuriya [col. 21, line 56] discloses the microcontroller 724 directly communicates with a memory of a memory tile to perform read/write operations. Therefore, the AI core 725 may be configured to set the configuration register to select the partition (501a, 501b) and two or more data types (weights and input/output).
Mathuriya does not disclose “selection of the partition and two or more data types based on pre-profiled characteristics of a workload.”
Henderson FIG. 2, [0087] discloses the requestor (208) queries an accelerator runtime application (210) to determine how many enhanced memory modules are configured in the system as well as how much memory on those enhanced memory modules is allocated to running acceleration-based workloads. The accelerator runtime application (210) may then query an accelerator driver (216) to get this information. With this information, the requestor (208) can determine if the workload can fit within the configured amount of memory and execute the workload accordingly. In the event that the amount of memory available is insufficient for the workload, the requestor may reconfigure the workload, such as reducing its size or chunking the workload, so that the available memory may be utilized. Therefore, Henderson discloses memory utilization based on workload characteristics.
The combination of Norman, Malladi, Quader, Mathuriya, and Henderson discloses: wherein the circuit (725) is configured to set the configuration register (configuration registers internal to AI core 725 accessed via CSB725b) to select the partition (partitions 501a, 501b) and two or more data types (I/O buffers and weights) based on pre-profiled characteristics of a workload (Henderson: based on workload characteristics [0087]).
Henderson discloses that a method as taught enhances memory utilization of the device [0087]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device in order to enhance memory utilization as disclosed by Henderson [0087].
Claims 19 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Knag et al. (US20200097807A1; hereinafter Knag) in view of Norman.
Regarding Claim 19, Knag discloses a system (computer system 900, FIG. 9, [0079]) comprising:
a display device (display 940), FIG. 9, [0083]; and
a neural network accelerator (Binary Neural Network accelerator 102) configured to process images rendered to the display device (940), FIGS. 1, 9, [0032], [0078].
Knag [0078] discloses the system 900 includes an image classifier 100. Knag [0032] discloses the image classifier 100 includes a Binary Neural Network accelerator 102. The Binary Neural Network accelerator 102 includes a Static Random Access Memory (SRAM) 110 to store an input image 106 and a controller 118 to move portions of the input image 106 from the static Random Access Memory 110 to interleaved memory compute 112 for processing. Therefore, the BNN accelerator 102 is configured to process images rendered to the display device 940.
Knag does not explicitly disclose “wherein the neural network accelerator includes: a logic die including a circuit and a memory; and a memory die including an additional memory having a same footprint as the circuit and memory in the logic die,
wherein the logic die and the memory die are stacked three-dimensionally with die-to-die data communication between the circuit and the additional memory by face-to-face hybrid bonds.”
In a similar art, Norman discloses a semiconductor device (a multi-die QV memory module 100, FIG. 1, [0024]).
The combination of Knag and Norman discloses: wherein the neural network accelerator (Knag: BNN accelerator 102) includes a logic die and a memory die (Norman: controller die 102 and memory die 101, FIG. 1, [0024]).
Norman discloses:
a logic die (controller die 102) including a circuit and a memory, FIG. 1, [0026], [0032]. Norman [0026] discloses the controller die 102 includes a memory controller which includes controller logic circuitry. Norman [0032] discloses the memory controller die may incorporate high speed SRAM. Therefore, the logic die 102 includes a circuit and a memory.
a memory die (memory die 101) including an additional memory (memory die 101 includes memory arrays, [0027]) having a same footprint as the circuit and memory in the logic die, FIG. 1, [0032].
Norman [0032] discloses the memory dies and the controller have substantially the same silicon areas, so that signaling can be achieved over short conductors, which avoids interconnection delays, indicating the memory die and the logic die may have the same footprint.
wherein the logic die (102) and the memory die (101) are stacked three-dimensionally with die-to-die data communication between the circuit and the additional memory by face-to-face hybrid bonds, FIG. 1, [0024].
Norman [0032] discloses the memory die 101 and the controller die 102 are interconnected by copper interconnect conductors (“hybrid bonds” or “studs”) 106 and the copper studs are used in a flip chip bonding method to connect the memory die to the controller die. This indicates the memory die and controller die are stacked and have die-die-data communication between the circuit in the logic die and the additional memory in the memory die by face-to-face hybrid bonds.
Norman discloses that a system as taught enables implementation of a large memory capacity in a compact size while minimizing the length of the signal line connections [0022]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Knag’s system in order to enable implementation of a large memory capacity in a compact size while minimizing the length of the signal line connections as disclosed by Norman [0022].
Regarding Claim 20, The combination of Knag and Norman discloses the system of claim 19.
The combination of Knag and Norman discloses: wherein the neural network accelerator (Knag: BNN accelerator 102) includes a logic die and a memory die (Norman: controller die 102 and memory die 101, FIG. 1, [0024]).
Norman discloses:
an additional memory die (301a) including a further memory (memory arrays) having a same footprint as the circuit and memory in the logic die (302), FIGS. 1 & 3, [0032], [0035].
Norman [0032] discloses controller dies include logic circuitry and high speed SRAM. Norman [0032] discloses the memory dies and the controller have substantially the same silicon areas, so that signaling can be achieved over short conductors, which avoids interconnection delays, indicating the memory die and the logic die have the same footprint.
wherein the logic die (302) and the additional memory die (301a) are stacked three-dimensionally with die-to-die data communication between the circuit and the further memory by a face-to-back through silicon via, FIG. 3, [0035].
Norman [0035] discloses a combination of hybrid bonds and TSVs route signals exchanged between controller 302 and each memory die. This indicates the die-to-die data communication between the circuit and the further memory may be implemented through a face-to-back through silicon via.
Conclusion
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/Krishna J. Palaniswamy/
Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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