CTNF 18/391,023 CTNF 82275 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-25-01 AIA Applicant’s election without traverse of claims 1-5 & 11-20 in the reply filed on 04/21/2026 is acknowledged. Specification 07-29 AIA The disclosure is objected to because of the following informalities: reference numerals 106, 406 & 506 in the drawings are not described in the specification . Appropriate correction is required. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Nogami et al. (US Pub. 2024/0431025) in view of Lee et al. (US Pub. 2025/0105057) . Regarding claim 1, Nogami teaches an integrated circuit structure, comprising: a first conductive interconnect line 304 in a first inter-layer dielectric (ILD) layer 302 above a substrate (it is understood that the first conductive interconnect line 304 and the first ILD layer 302 are on a substrate), the first conductive interconnect line 304 along a first direction (Fig. 3J); a second conductive interconnect line 318 in a second ILD layer 314 above the first ILD layer 302, the second conductive interconnect line 318 along a second direction orthogonal to the first direction (Fig. 3J); and a conductive via 310 coupling the first conductive interconnect line 304 and the second conductive interconnect line 318. Nogami is silent on the conductive via inwardly tapered from a top to a bottom of the conductive via along curved sidewalls along the second direction but not along the first direction, and the conductive via contiguous with but not continuous with the second conductive interconnect line. However, Lee teaches an integrated circuit structure, wherein a conductive via 136/236 is inwardly tapered from a top to a bottom of the conductive via along curved sidewalls along the second direction but not along the first direction, and the conductive via 136/236 contiguous with but not continuous with a second conductive interconnect line (see Fig. 1F & Fig. 4G). This has the advantage of improving contact resistance. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Nogami with the conductive via, as taught by Lee, so as to obtain an improved integrated circuit device. Regarding claim 2, the combination of Nogami and Lee teaches the integrated circuit structure of claim 1, wherein the conductive via has straight sidewalls along the first direction (Nogami’s Fig. 3J and Lee’s Fig. 1F & 4G). Regarding claim 3, the combination of Nogami and Lee teaches the integrated circuit structure of claim 2, wherein the straight sidewalls are inwardly tapered from the top to the bottom of the conductive via (Nogami’s Fig. 3J and Lee’s Fig. 1F & 4G). Regarding claim 4, the combination of Nogami and Lee teaches the integrated circuit structure of claim 2, wherein the straight sidewalls are vertical (Nogami’s Fig. 3J and Lee’s Fig. 1F & 4G). Regarding claim 6, the combination of Nogami and Lee teaches the integrated circuit structure of claim 1, wherein the conductive via is a single damascene conductive via (Nogami’s Fig. 3J, Lee’s Fig. 1F & 4G and associated texts) . 07-21-aia AIA Claim s 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nogami in view of Lee and Naylor et al. (US Pub. 2022/0139775) . Regarding claim 11, Nogami teaches a computing device, comprising: an integrated circuit structure, comprising: a first conductive interconnect line 304 in a first inter-layer dielectric (ILD) layer 302 above a substrate (it is understood that the first conductive interconnect line 304 and the first ILD layer 302 are on a substrate), the first conductive interconnect line 304 along a first direction (Fig. 3J); a second conductive interconnect line 318 in a second ILD layer 314 above the first ILD layer 302, the second conductive interconnect line 318 along a second direction orthogonal to the first direction (Fig. 3J); and a conductive via 310 coupling the first conductive interconnect line 304 and the second conductive interconnect line 318. Nogami is silent on (i) the conductive via inwardly tapered from a top to a bottom of the conductive via along curved sidewalls along the second direction but not along the first direction, and the conductive via contiguous with but not continuous with the second conductive interconnect line; and (ii) a board; and a component coupled to the board, the component including the integrated circuit device. Lee teaches (i) an integrated circuit structure, wherein a conductive via 136/236 is inwardly tapered from a top to a bottom of the conductive via along curved sidewalls along the second direction but not along the first direction, and the conductive via 136/236 contiguous with but not continuous with a second conductive interconnect line (see Fig. 1F & Fig. 4G). This has the advantage of improving contact resistance. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Nogami with the conductive via, as taught by Lee, so as to obtain an improved integrated circuit device. Regarding (ii), the Examiner understands that the use of a board and a component comprising an integrated circuit device comprising metal interconnect structures are widely known and would have been obvious in the semiconductor art. For instance, Naylor teaches a board 1401; and a component coupled to the board, the component including an integrated circuit device (see Fig. 14). As such, said claim features would have been obvious and within the ordinary skill in the art. Regarding claim 12, the combination of Nogami, Lee and Naylor teaches the computing device of claim 11, wherein the conductive via is fabricated using a one-dimensional directional etch process (Nogami’s Fig. 3E-3J, Lee’s Fig. 1F & 4G and associated texts). Regarding claim 13, the combination of Nogami, Lee and Naylor teaches the computing device of claim 11, wherein the conductive via is flared along the second direction (Nogami’s Fig. 3E-3J, Lee’s Fig. 1A-1F & 4G and associated texts). Regarding claim 14, the combination of Nogami, Lee and Naylor teaches the computing device of claim 11, further comprising: a memory coupled to the board (Naylor’s Fig. 14). Regarding claim 15, the combination of Nogami, Lee and Naylor teaches the computing device of claim 11, further comprising: a communication chip coupled to the board (Naylor’s Fig. 14). Regarding claim 16, the combination of Nogami, Lee and Naylor teaches the computing device of claim 11, further comprising: a battery coupled to the board (Naylor’s Fig. 14). Regarding claim 17, the combination of Nogami, Lee and Naylor teaches the computing device of claim 11, further comprising: a camera coupled to the board (Naylor’s Fig. 14). Regarding claim 18, the combination of Nogami, Lee and Naylor teaches the computing device of claim 11, further comprising: a display coupled to the board (Naylor’s Fig. 14). Regarding claim 19, the combination of Nogami, Lee and Naylor teaches the computing device of claim 11, wherein the component is a packaged integrated circuit die (Nogami’s Fig. 3J, Lee’s Fig. 1F & 4G and associated texts). Regarding claim 20, the combination of Nogami, Lee and Naylor teaches the computing device of claim 11, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (Naylor’s Fig. 14). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOR KARIMY whose telephone number is (571)272-9006. The examiner can normally be reached Monday - Friday: 8:30 AM -5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TIMOR KARIMY/Primary Examiner, Art Unit 2818 Application/Control Number: 18/391,023 Page 2 Art Unit: 2818 Application/Control Number: 18/391,023 Page 4 Art Unit: 2818 Application/Control Number: 18/391,023 Page 5 Art Unit: 2818 Application/Control Number: 18/391,023 Page 6 Art Unit: 2818 Application/Control Number: 18/391,023 Page 7 Art Unit: 2818 Application/Control Number: 18/391,023 Page 8 Art Unit: 2818
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