Prosecution Insights
Last updated: April 19, 2026
Application No. 18/391,031

WIDE BAND GAP (WBG) DEVICES BASED THREE-LEVEL ACTIVE NEUTRAL POINT CLAMPED (ANPC) POWER MODULE DESIGNS

Non-Final OA §102
Filed
Dec 20, 2023
Examiner
ULLAH, ELIAS
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
UNIVERSITY OF TENNESSEE RESEARCH FOUNDATION
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
92%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
700 granted / 829 resolved
+16.4% vs TC avg
Moderate +8% lift
Without
With
+8.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
22 currently pending
Career history
851
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
32.8%
-7.2% vs TC avg
§102
55.7%
+15.7% vs TC avg
§112
7.8%
-32.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 829 resolved cases

Office Action

§102
DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-3, 6, and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Barrenscheen et al. (Barrenscheen, US 11,626,826). Regarding claim 1, Barrenscheen shows a power module (module 400 in FIG. 4) comprising: an upper arm structure that includes a first semiconductor switch ( High-side switch 450A in FIG. 4), a second semiconductor switch (Switch 450B) and a fifth semiconductor switch (Switch 450C); a lower arm structure that includes a third semiconductor switch ( Switch 460A), a fourth semiconductor switch (Switch 460B) and a sixth semiconductor switch (Switch 460C); a first gate driving board, attached with the upper arm, wherein the first gate driving board includes a first gate driver (drive 418A) connected to a first gate of the first semiconductor switch (Switch 450A), a second gate driver (drive 418B) connected to a second gate of the second semiconductor switch (switch 450B), and a third gate driver (driver 418C) connected to a fifth gate of the fifth semiconductor switch (switch 450C); a second gate driving board, attached with the lower arm, wherein the second gate driving board includes a third gate driver (driver 420A) connected to a third gate of the third semiconductor switch ( switch 460A), a fourth gate driver (driver 420B) connected to a fourth gate of the fourth semiconductor switch (switch 460B), and a sixth gate driver (driver 420C) connected to a sixth gate of the sixth semiconductor switch (switch 460C). Regarding claim 2, Barrenscheen shows a power module (module 400 in FIG. 4) comprising, wherein the power module is configured to be operable in first operational states in which first electric currents of equal magnitudes flow in two short communication loops (underlined limitations considered as function of Barrenscheen’s system 400 in FIG. 4). Regarding claim 3, Barrenscheen shows a power module (module 400 in FIG. 4) comprising, wherein the power module is configured to be operable in second operational states in which second electric currents of equal magnitudes flow in two long commutation loops (underlined limitations considered as a function of Barrenscheen’s system 400 in FIG. 4). Regarding claim 6, Barrenscheen shows a power module (module 400 in FIG. 4) further comprising: a direct current (DC) positive terminal (DC+); a DC negative terminal (DC-) (see FIG. 2 with respect to FIG. 4). Regarding claim 15, Barrenscheen shows a power module (module 400 in FIG. 4) further comprising an alternate current (AC) terminal (see FIG. 2 with respect to FGI. 4). Allowable Subject Matter Claims 4-5 and 6-14 and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ELIAS ULLAH/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Dec 20, 2023
Application Filed
Mar 07, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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2y 5m to grant Granted Apr 14, 2026
Patent 12604779
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2y 5m to grant Granted Apr 14, 2026
Patent 12599050
MULTI-LEVEL DIE COUPLED WITH A SUBSTRATE
2y 5m to grant Granted Apr 07, 2026
Patent 12593729
POWER MODULE HAVING AT LEAST THREE POWER UNITS
2y 5m to grant Granted Mar 31, 2026
Patent 12593697
INTEGRATED PASSIVE DEVICES (IPD) HAVING A BASEBAND DAMPING RESISTOR FOR RADIOFREQUENCY POWER DEVICES AND DEVICES AND PROCESSES IMPLEMENTING THE SAME
2y 5m to grant Granted Mar 31, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
92%
With Interview (+8.1%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 829 resolved cases by this examiner. Grant probability derived from career allow rate.

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