DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claim 13, Claim 13 recites and a plurality of piers extending through the stack of materials, wherein each pier of the plurality of piers is electrically isolated from each pillar of the plurality of pillars.
Applicant has not set forth the pier are electrically conductive it is unclear if applicant is inferring this material is conductive. Paragraph 47 of the disclosure indicates the piers are a dielectric liner with a dielectric or semiconductor. None of which are electrically conductive or active. The polysilicon maybe conductive with sufficient dopants but applicant does not teach the polysilicon is doped. The piers to not provide a current flow so it is unclear how they are electrically isolated from the pillars
Electrical isolation is defined as the protection mechanism that prevents failures in one instrumentation and control (I&C) system from interfering with another, achieved through the absence of electronic connections, the use of isolating devices, or physical separation within equipment.
It appears the piers are used for electrical isolation of the pillars as opposed to being electrically isolated from the pillars.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13-18 and 20 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin (20220238550) in view of Villa (20220180926) both references cited on IDs
a. As to claims 13-14 and 17-18, Shin teaches An apparatus, comprising: a plurality of bit line plates item 93 figures 1 and 2 or items 92 figure 1); a stack of materials located above the plurality of bit line plates (item 51-52), the stack of materials comprising alternating layers of a dielectric material (item 55 figure 1) and respective word lines of a plurality of word lines (item 56), wherein each word line of the plurality of word lines comprises a conductive material (item 63 paragraph 29); a plurality of pillars extending through the stack of materials, wherein each pillar of the plurality of pillars is in contact with a respective bit line plate of the plurality of bit line plates, and wherein the plurality of pillars comprise a semiconductive material (item 70); a liner in contact with one or more sidewalls of each pillar (items 75 and 76); and a plurality of piers extending through the stack of materials, wherein each pier of the plurality of piers ( item 80) is electrically isolated from each pillar of the plurality of pillars (they are not electrically conductive so they are inherently isolated from the pillars (paragraph 96).
Shin does not teach the plurality of pillars comprise a conductive material and a plurality of chalcogenide memory cells coupled with the plurality of pillars and a respective word line of the plurality of word lines.
Villa teaches providing the pillars 220 figure 3 paragraph 30 as conductive pillars (paragraph 30) and providing the word lines as chalcogenide word lines (paragraphs 15-16 and paragraph 31).
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide the plurality of pillars comprise a conductive material and a plurality of chalcogenide memory cells coupled with the plurality of pillars and a respective word line of the plurality of word lines for forming chalcogenide memory device for the desired retention times and faster switching times.
Shin in view of Villa would therefore teach wherein the plurality of piers comprise one or more materials that are different than a material comprised by the plurality of pillars. Villa teaches conductive materials for the pillars ( items 220 paragraph 30) and Shin teaches, paragraph 96, purely insulators (items 75/76).
b. As to claims 15 and 20, Both Shin and Villa teach a plurality of transistors, wherein each transistor of the plurality of transistors is coupled with a respective bit line plate of the plurality of bit line plates (items 27 transistors and 31 paragraph 101 figure 45 the peripheral circuit is the decoder and the pillars are connected to the decoder) Villa explicitly teaches direct connection (each 225 figure3 connected to the pillars).
As to claims 16, Shin teaches wherein at least a portion of each pier of the plurality of piers comprises a second dielectric material (paragraph 96).
Allowable Subject Matter
Claims 1-12 are allowed.
As to claim 1 prior art fails to teach and or suggest forming a plurality of cavities extending through the stack of materials, wherein a bottom surface of each cavity is coplanar with an upper surface of each plug of the plurality of plugs; removing the sacrificial material from the plurality of plugs based at least in part on forming the plurality of cavities, wherein the bottom surface of each cavity extends below the upper surface of each plug in the first direction based at least in part on removing the sacrificial material; and forming a plurality of pillars in the plurality of cavities based at least in part on removing the sacrificial material from the plurality of plugs in conjunction with the other elements of claim 1.
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Prior art fails to teach and or suggest wherein at least a portion of the plurality of piers comprise a second dielectric material, and wherein for a pier of the plurality of piers, the second dielectric material is in contact with a chalcogenide memory material of the plurality of chalcogenide memory cells in conjunction with the other elements claims 18 and 17. Pellizzer teaches a portion of the plurality of piers comprise a second dielectric material, and wherein for a pier of the plurality of piers, the second dielectric material is in contact with a chalcogenide memory material of the plurality of chalcogenide memory cells but does not teach the elements of claim 17 a plurality of bit line plates; a stack of materials located above the plurality of bit line plates.
Conclusion
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/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/Primary Examiner, Art Unit 2896