Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-14 and 23-29 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sio et al., US 2022/0254769.
Sio et al. shows the invention as claimed including a chip, comprising:
A first transistor comprising:
A first source/drain (203b);
A second source/drain (203d);
A gate (303) between the first source/drain and the second source/drain; and
A first backside contact (VB3) coupled to a bottom surface of the first source/drain;
A pass-through structure comprising:
A first diffusion region (203) extending in a first direction;
A second backside contact (VB8) coupled to a bottom surface of the first diffusion region; and
A topside contact coupled to a top surface of the first diffusion region; and a backside metal routing (702) coupled between the first backside contact and the second backside contact (see figs. 5a-5d, 6a-6c, and paragraphs 0056-0073).
Regarding dependent claims 2, 13, and 16, note that Sio et al. discloses a second transistor between the first transistor and the pass-through structure, wherein the backside metal routing (702) extends under the second transistor (see fig. 5C).
Concerning dependent claim 3, note that Sio et al. discloses that the backside metal routing (702) includes a backside line extending in the first direction (see fig. 5C).
With respect to dependent claims 4 and 25, Sio et al. discloses a first topside metal line (506) extending in the first direction, wherein the topside metal contact is coupled to the first topside metal line (see fig. 5C).
As to dependent claims 5 and 26, Sio et al. shows a second topside metal line (601) extending in a second direction perpendicular to the first direction, wherein the second topside metal line is coupled to the first topside metal line (506) (see figures 5A-5C).
Concerning dependent claim 6, Sio et al. discloses wherein the first topside metal line (506) is formed from a first metal layer, and the second topside metal layer (601) is formed from a second metal layer above the first metal layer (see fig. 3F).
Regarding dependent claims 7 and 27, Sio et al. discloses a first backside via (VB3) disposed between the first backside contact and the backside metal routing; and a second backside via (VB8) disposed between the second backside contact and the backside metal routing (see fig. 5C).
With respect to dependent claim 8, Sio et al. teaches the pass-through structure further comprising a second diffusion region (202), the second backside contact is coupled to a bottom surface of the second diffusion region, and the topside contact is coupled to a top surface of the second diffusion region (see fig. 5A).
Concerning dependent claims 9 and 20, Sio et al. discloses the first diffusion region (202) and the second diffusion region (203) are spaced apart in a second direction perpendicular to the first direction (see fig. 5A).
As to dependent claim 10, Sio et al. shows the first diffusion region is a p-type diffusion region (202) and the second diffusion region is an n-type diffusion region (203) (see fig. 5A and paragraph 0061).
With respect to dependent claim 11, note that in Sio et al. if the first and second diffusion regions are designated as second and first diffusion regions, then the first diffusion region is a n-type diffusion region and the second diffusion region is a p-type diffusion region.
Regarding independent claim 12, Sio et al. shows the invention as claimed including a chip, comprising:
A first transistor comprising:
A first source/drain (203b);
A second source/drain (203d);
A gate (303) between the first source/drain and the second source/drain; and
A backside contact (VB3) coupled to a bottom surface of the first source/drain;
Pass-through structures;
A backside metal routing (704) coupled to the backside contact and extending under the first transistor to the pass-through structures; and
A topside metal line (409) extending over the pass-through structures, wherein the pass-through structures are coupled in parallel between the backside metal routing (704) and the topside metal line, and each of the pass-through structures provides a respective signal path between the backside metal routing and the topside metal line (see paragraphs 0056-0073 and figs. 5a-5d and 6a-6c).
Regarding dependent claims 14 and 17, Sio et al. discloses the backside metal routing includes a backside metal line (702) (see fig. 5C).
With respect to independent claim 23, Sio et al. shows the invention as claimed including a chip, comprising:
A first cell comprising:
A first diffusion region (203) extending in a first direction;
Gates (303) formed over the first diffusion region, wherein each of the gates is elongated and extends in a second direction perpendicular to the first direction; and
A first backside contact (VB3) coupled to a bottom surface of the first diffusion region;
A pass-through filler cell comprising:
A second diffusion region (202);
A second backside contact (VB8) coupled to a bottom surface of the second diffusion region; and
A topside contact coupled to a top surface of the second diffusion region; and
A backside metal routing (704) coupled between the first backside contact and the second backside contact (see paragraphs 0056-0073 and figs. 5a-5d and 6a-6c).
As to dependent claim 24, Sio et al. discloses a second cell between the first cell and the pass-through filler cell, wherein the backside metal routing extends under the second cell (see fig. 5C).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 15-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sio et al., US 2022/0254769.
Sio et al. shows the invention substantially as claimed including a chip, comprising:
A first transistor comprising:
A first source/drain (203b);
A second source/drain (203d);
A first gate (303) between the first source/drain and the second source/drain; and
A first backside contact (VB3) coupled to a bottom surface of the first source/drain; and
A pass-through structure comprising:
A first diffusion region (203) extending in a first direction;
A second backside contact (VB8) coupled to a bottom surface of first diffusion region;
A first topside contact coupled to a top surface of the first diffusion region; and
A backside metal routing (702) coupled to the first backside contact and the second backside contact, wherein the backside metal routing extends under the first transistor to the pass-through structure; and
A topside metal line extending in the first direction, wherein the topside metal line is coupled to the first topside contact (see paragraphs 0056-0073 and figs. 5a-5d and 6a-6c).
Sio et al. does not expressly disclose the claimed second topside contact and third backside contact. However, Sio et al. discloses the possibility of forming more transistors in the device (see, for example, paragraph 0066). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Sio et al. so as to form a second topside contact and third backside contact if it is desired to form more transistors in the device as suggested by Sio et al..
Concerning dependent claim 16, note that Sio et al. discloses a second transistor between the first transistor and the pass-through structure, wherein the backside metal routing (702) extends under the second transistor (see fig. 5C).
Regarding dependent claim 17, Sio et al. discloses the backside metal routing includes a backside metal line (702) (see fig. 5C).
With respect to dependent claim 18, note that Sio et al. discloses the pass-through structure comprises a second gate (202f) between the first and second topside contacts (see fig. 6C).
Concerning dependent claims 19 and 28-29, Sio et al. does not expressly disclose the claimed second/third diffusion region configuration. However, official notice is taken that it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Sio et al. so as to include the claimed second diffusion region configuration as a conventional means to provide contacts to the additional transistors structure that are formed if desired.
As to dependent claim 21, Sio et al. shows the first diffusion region is a p-type diffusion region (202) and the second diffusion region is an n-type diffusion region (203) (see fig. 5A and paragraph 0061).
With respect to dependent claim 22, note that in Sio et al. if the first and second diffusion regions are designated as second and first diffusion regions, then the first diffusion region is a n-type diffusion region and the second diffusion region is a p-type diffusion region.
Additional Cited Relevant Prior Art
Both US Patent 12,581,692 (see fig. 5 and its description) and US 2023/0299068 (see paragraph 0070) disclose the state of the art in pass through structures but fail to disclose the claimed limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
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/RICHARD A BOOTH/ Primary Examiner, Art Unit 2812
May 12, 2026
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