DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (Pub. No.: US 2020/0279911 A1).
Regarding claim 1, Kim discloses a semiconductor device in Fig. 2 comprising: a substrate (substrate 105) comprising an epitaxial layer (layer 121) (see [0043-0046]); a first gate electrode (one of gate structure 140) and a second gate electrode (another adjacent gate structure 140) disposed on the substrate (see [0051-0052]); a first type
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body region (body region 150 as similar to body region 250) disposed within the substrate between the first gate electrode and the second gate electrode (see Fig. 2, 10 and [0095]); a pillar region (pillar 126) extending from the first type body region toward a lower surface of the substrate and disposed within the epitaxial layer (see [0043-0045]); and a first region (upper portion R1 of pillar 126 as illustrated in annotated Fig. 2 above) and a second region of the pillar region (lower portion R2 of pillar 126 as illustrated in annotated Fig. 2 above), each comprising a portion whose width decreases and then increases along a first direction (as illustrated in annotated Fig. 2 above) from an upper surface of the substrate toward the lower surface (see annotated Fig. 2 above), wherein the first region is disposed between the first type body region and the second region (see annotated Fig. 2 above), the first region comprises a first width (width W1) that is a minimum width of widths of the pillar region and a second width (width W2) that is greater than the first width, the second region comprises a third width (width W3) that is greater than the first width and less than the second width (see annotated Fig. 2 above), and the first region and the second region are divided with the second width as a boundary (see annotated Fig. 2 above).
Regarding claim 2, Kim discloses the semiconductor device of claim 1, wherein the first region is a region that decreases from a fourth width (width W4) to the first width along the first direction and then increases from the first width to the second width along the first direction (see annotated Fig. 2 above), the second region is a region that decreases from the second width to the third width along the first direction and then increases from the third width to a fifth width (width W5) along the first direction, and a third region directly below the second region comprises a portion of the pillar region where a width of the pillar region decreases along the first direction from the fifth width (see annotated Fig. 2 above).
Regarding claim 3, Kim discloses the semiconductor device of claim 2, wherein the first width is less than the fourth width and the fifth width (W1 <W4 and W5) (see annotated Fig. 2 above).
Regarding claim 4, Kim discloses the semiconductor device of claim 2, wherein the first region is disposed directly below the first type body region (region R1), and the second region (region R2) and the third region (region R3) are divided with the fifth width as a boundary (see annotated Fig. 2 above).
Regarding claim 5, Kim discloses the semiconductor device of claim 2, wherein a first thickness of the first region (thickness D1) measured along the first direction is greater than a second thickness of the second region (thickness D2) measured along the first direction (see annotated Fig. 2 above).
Regarding claim 6, Kim discloses the semiconductor device of claim 1, wherein the first region is disposed directly below the first type body region (see annotated Fig. 2 above).
Regarding claim 7, Kim discloses semiconductor device of claim 6, wherein the second region is disposed directly below the first region (region R2 directly below region R1) (see annotated Fig. 2 above).
Regarding claim 8, Kim discloses a semiconductor device in Fig. 2 comprising: a substrate (substrate 105) comprising an epitaxial layer (layer 121) (see [0043-0046]); a first gate electrode (one of gate structure 140) and a second gate electrode (another adjacent gate structure 140) disposed on the substrate (see [0051-0052]); a first type body region (body region 150 as similar to body region 250) disposed within the substrate between the first gate electrode and the second gate electrode (see Fig. 2, 10 and [0095]); a pillar region (pillar 126) extending from the first type body region toward a lower surface of the substrate and disposed within the epitaxial layer (see [0043-0045]); and a first region (upper portion R1 of pillar 126 as illustrated in annotated Fig. 2 above) and a second region of the pillar region (lower portion R2 of pillar 126 as illustrated in annotated Fig. 2 above), each comprising a portion whose width decreases and then increases along a first direction (as illustrated in annotated Fig. 2 above) from an upper surface of the substrate toward the lower surface (see annotated Fig. 2 above), wherein the first region is disposed between the first type body region and the second region (see annotated Fig. 2 above), wherein a first thickness of the first region (thickness D1) measured along the first direction is greater than a second thickness of the second region (thickness D2) measured along the first direction (see annotated Fig. 2 above).
Regarding claim 9, Kim discloses the semiconductor device of claim 8, wherein the first region comprises a first width (width W1) that is a minimum width of widths of the pillar region and a second width (width W2) that is greater than the first width, the second region comprises a third width (width W3) that is greater than the first width and less than the second width (see annotated Fig. 2 above), and the first region and the second region are divided with the second width as a boundary (see annotated Fig. 2 above).
Regarding claim 10, Kim discloses the semiconductor device of claim 9, wherein the first region is a region that decreases from a fourth width (width W4) to the first width along the first direction and then increases from the first width to the second width along the first direction (see annotated Fig. 2 above), the second region is a region that decreases from the second width to the third width along the first direction and then increases from the third width to a fifth width (width W5) along the first direction, and a third region directly below the second region comprises a portion of the pillar region where a width of the pillar region decreases along the first direction from the fifth width (see annotated Fig. 2 above).
Regarding claim 11, Kim discloses the semiconductor device of claim 10, wherein the first width is less than the fourth width and the fifth width (W1 <W4 and W5) (see annotated Fig. 2 above).
Regarding claim 12, Kim discloses the semiconductor device of claim 10, wherein the first region is disposed directly below the first type body region (region R1), and the second region (region R2) and the third region (region R3) are divided with the fifth width as a boundary (see annotated Fig. 2 above).
Regarding claim 13, Kim discloses the semiconductor device of claim 8, wherein the first region is disposed directly below the first type body region (see annotated Fig. 2 above).
Regarding claim 14, Kim discloses semiconductor device of claim 13, wherein the second region is disposed directly below the first region (region R2 directly below region R1) (see annotated Fig. 2 above).
Regarding claim 15, Kim discloses a semiconductor device in Fig. 2 comprising: a substrate (substrate 105) comprising an epitaxial layer (layer 121) (see [0043-0046]); a first gate electrode (one of gate structure 140) and a second gate electrode (another adjacent gate structure 140) disposed on the substrate (see [0051-0052]); a first type body region (body region 150 as similar to body region 250) disposed within the substrate between the first gate electrode and the second gate electrode (see Fig. 2, 10 and [0095]); a pillar region (pillar 126) extending from the first type body region toward a lower surface of the substrate and disposed within the epitaxial layer (see [0043-0045]); and a first region (upper portion R1 of pillar 126 as illustrated in annotated Fig. 2 above) and a second region of the pillar region (lower portion R2 of pillar 126 as illustrated in annotated Fig. 2 above), each comprising a portion whose width decreases and then increases along a first direction (as illustrated in annotated Fig. 2 above) from an upper surface of the substrate toward the lower surface (see annotated Fig. 2 above), wherein the first region is disposed between the first type body region and the second region (see annotated Fig. 2 above), wherein a first thickness of the first region (thickness D1) measured along the first direction is greater than a second thickness of the second region (thickness D2) measured along the first direction (see annotated Fig. 2 above) and the first region is disposed directly below the first type body region (see annotated Fig. 2 above).
Regarding claim 16, Kim discloses the semiconductor device of claim 15, wherein the first region is a region that decreases from a fourth width (width W4) to the first width along the first direction and then increases from the first width to the second width along the first direction (see annotated Fig. 2 above), the second region is a region that decreases from the second width to the third width along the first direction and then increases from the third width to a fifth width (width W5) along the first direction, and a third region directly below the second region comprises a portion of the pillar region where a width of the pillar region decreases along the first direction from the fifth width (see annotated Fig. 2 above).
Regarding claim 17, Kim discloses the semiconductor device of claim 16, wherein the first width is less than the fourth width and the fifth width (W1 <W4 and W5) (see annotated Fig. 2 above).
Regarding claim 18, Kim discloses the semiconductor device of claim 16, wherein the second region (region R2) and the third region (region R3) are divided with the fifth width as a boundary (see annotated Fig. 2 above).
Regarding claim 19, Kim discloses the semiconductor device of claim 15, wherein the first region is disposed directly below the first type body region (see annotated Fig. 2 above) and the second region (region R2) and the third region (region R3) are divided with the fifth width as a boundary (see annotated Fig. 2 above).
Regarding claim 20, Kim discloses semiconductor device of claim 15, wherein the second region is disposed directly below the first region (region R2 directly below region R1) (see annotated Fig. 2 above).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818