Prosecution Insights
Last updated: October 01, 2026
Application No. 18/391,222

IMAGE SENSOR

Non-Final OA §102§103
Filed
Dec 20, 2023
Priority
Jul 19, 2019 — FR 1908191 +1 more
Examiner
NARAGHI, ALI
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
STMicroelectronics N.V.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
678 granted / 785 resolved
+18.4% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
28 currently pending
Career history
820
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
63.8%
+23.8% vs TC avg
§102
18.1%
-21.9% vs TC avg
§112
13.1%
-26.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 785 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of group 1 in the reply filed on 07/14/2026 is acknowledged. The traversal is on the ground(s) that the groups are mutually exclusive. Examiner agrees partially with applicant, because claim 16 is mutually exclusive from the group one, nowhere in the group 1 the limitations of claim 16 is mentioned. The requirement is still deemed proper and is therefore made FINAL. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1,10-13,17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Roy et al (US Pub No. 20090266973). With respect to claim 1, Roy et al discloses an image sensor pixel (Fg.4B), comprising: forming a charge collection region (P+) by doping a portion of an upper surface of a substrate (27,25) that includes a photosensitive region (27, because it forms a pn junction with 25) of a first conductivity type (p), the charge collection region being above the photosensitive region (FIug.4B) and being more heavily doped with the first conductivity type than the photosensitive region (Fig.4B); and forming a vertical stack (37,41) that includes a vertical transfer gate (TG) and a vertical electric insulation wall (portion of 41), the vertical stack crossing the substrate and being in contact with the charge collection region (Fig.4B), the vertical transfer gate being arranged at the upper surface of the substrate (Fig.4B) and penetrating into the substrate deeper than the charge collection region (Fig.4B), the vertical transfer gate including a gate electrode (37) and a gate dielectric (41 contain stack of material, the one next to the gate electrode is gate dielectric layer, para 50) that are arranged on the vertical electric insulation wall (the layer below the gate dielectric layer, para 50). With respect to claim 10, Roy et al discloses wherein the gate dielectric electrically insulates the substrate from the gate electrode of the vertical transfer gate (Fig.4B). With respect to claim 11, Roy et al discloses further comprising: forming a doped well (25) of a second conductivity type (N) extending in the substrate from the upper surface to the photosensitive region (Fig.4B). With respect to claim 12, Roy et al discloses wherein the vertical transfer gate penetrates into the substrate at least down to a level of a lower surface of the doped well (Fig.4B). With respect to claim 13, Roy et al discloses forming a photosensitive region (27,25,Fig.4B) of a first conductivity type in a substrate ( the p portion); forming a first charge collection region in the substrate (P+), the first charge collection region being more heavily doped with the first conductivity type than the photosensitive region (Fig.4B), the first charge collection region extending in the substrate from a surface of the substrate (Fig.4B) and being arranged above the photosensitive region (Fig.4B); and forming a vertical stack in the substrate (33), the vertical stack including a vertical transfer gate (37) and a vertical electric insulation wall (41), the vertical stack being in contact with the first charge collection region (Fig.4B), the vertical transfer gate being arranged at the surface of the substrate and penetrating into the substrate deeper than the first charge collection region (Fig.4B), the vertical transfer gate including a gate electrode (37) and a gate dielectric (upper portion of 41,para 50) that are arranged on the vertical electric insulation wall (Fig.4B). With respect to claim 17, Roy et al discloses: forming a photosensitive region (27,25,Fig.4B) of a first conductivity type (portion 27) in a substrate (25,27 and more); forming a charge collection region (P+) of the first conductivity type at a surface of the substrate (Fig.4B), the charge collection region being more heavily doped than the photosensitive region (Fig.4B); and forming a stack in the substrate (33), the stack including a transfer gate (37) and an electric insulation wall (41), the stack being in contact with the charge collection region (Fig.4B), the transfer gate being arranged at the surface of the substrate (Fig.4B) and extending into the substrate deeper than the charge collection region (Fig.4B), the transfer gate including a gate electrode (37) and a gate dielectric (upper portion of the 41,para 50) on the electric insulation wall (Para 50). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roy et al (US Pub No. 20090266973). With respect to claim 9, Roy et al does not explicitly disclose wherein the vertical transfer gate of each stack is common to the pixel and a neighboring pixel. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Roy et al such that vertical transfer gate is shared between two pixels, in order to decrease the size of the device. Allowable Subject Matter Claims 2-8,14-15,18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALI N NARAGHI whose telephone number is (571)270-5720. The examiner can normally be reached 10am-6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALI NARAGHI/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Dec 20, 2023
Application Filed
Sep 23, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
92%
With Interview (+5.1%)
2y 7m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 785 resolved cases by this examiner. Grant probability derived from career allowance rate.

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