Prosecution Insights
Last updated: April 19, 2026
Application No. 18/391,416

PUMP-OUT RESISTANT COLDPLATE

Non-Final OA §102
Filed
Dec 20, 2023
Examiner
PAGE, STEVEN MITCHELL CHR
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Microsoft Technology Licensing, LLC
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
92%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
359 granted / 433 resolved
+14.9% vs TC avg
Moderate +9% lift
Without
With
+8.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
33 currently pending
Career history
466
Total Applications
across all art units

Statute-Specific Performance

§101
3.4%
-36.6% vs TC avg
§103
38.4%
-1.6% vs TC avg
§102
36.1%
-3.9% vs TC avg
§112
21.5%
-18.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 433 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-20 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Shen et al. (US 20200350228 A1, hereinafter Shen ) With regards to claim 1 , Shen discloses a semiconductor assembly, (FIG. 3) comprising: a semiconductor including a heat-producing die, (flip chip 161 including semiconductor) the semiconductor having a broad area surfa ce through which heat is conducted from the die; (See FIG. 3) a heat exchanger (at least lid 200) having a mating broad area surface that interfaces with the semiconductor; (see FIG. 3, showing the mating) thermal interface material (TIM) (TIM liquid material 222A) disposed in a TIM-receiving volume (gap 222) formed between the respective broad area surfaces of the semiconductor and the heat exchanger; (See FIG. 3 and Paragraph [0028]) and a seal (seal ring 211A) disposed around an outer perimeter of the receiving volume formed between the semiconductor and the heat exchanger that traps the TIM within the TIM-receiving volume. (See FIG. 3, showing the trapping) With regards to claim 2 , Shen discloses the semiconductor assembly of claim 1 in which the seal comprises one of gasket, O-ring, (seal ring 211A, i.e. O-ring) knife-edge gasket, or edgebond adhesive. With regards to claim 3 , Shen discloses the semiconductor assembly of claim 1 in which the TIM comprises one of phase change material, thermal grease, thermal paste, thermal putty, thermal gel, graphite-based material, silicone-based material, or metal-based material. (Paragraph [0003]) With regards to claim 4 , Shen discloses the semiconductor assembly of claim 1 further including a seal-receiving feature disposed in one or more of the heat exchanger or semiconductor, the seal- receiving feature comprising one of slot, groove, (See FIG. 3, showing the groove of the seal 211A) lip, offset edge, or surface texture. With regards to claim 5 , Shen discloses the semiconductor assembly of claim 1 in which the heat exchanger comprises one of heatsink or coldplate. (lid is a heat sink, see Paragraph [0003]) With regards to claim 6 , Shen discloses the semiconductor assembly of claim 5 in which the coldplate is liquid-cooled. (Since the device may require a heat sink or cold plate, and the device is being interpreted as requiring a heat sink, the claim limitation is met) With regards to claim 7 , Shen discloses the semiconductor assembly of claim 1 in which the semiconductor includes an integrated heat spreader (heat sink/lid 200) providing the broad area surface through which heat is conducted from the die. (see FIG. 3) With regards to claim 8 , Shen discloses a semiconductor assembly, (FIG. 3) comprising: a semiconductor including a heat-producing die, (flip chip 161 including semiconductor) the semiconductor having a broad area surface through which heat is conducted from the die; ; (See FIG. 3) a heat exchanger (at least lid 200) disposed on the semiconductor, the heat exchanger having a broad area surface interfacing with the broad area surface of the semiconductor; (See FIG. 3) thermal interface material (TIM) (TIM liquid material 222A) disposed as a layer in an interstitial air gap (gap 211) between mating broad area surfaces of the semiconductor and heat exchanger, the TIM being flowable in the interstitial air gap; (See FIGS. 2-3, and paragraph [0030]) and a capillary tube (connecting hole 213) disposed in the heat exchanger extending from the broad area surface of the heat exchanger to an opening in the heat exchanger that is exposed to an atmosphere surrounding the semiconductor assembly, wherein the capillary tube provides a reservoir (reservoir 214) into which the TIM is displaced and from which the TIM is recoverable as the TIM flows in the interstitial air gap. (See FIG. 3, showing the recoverable TIM) With regards to claim 9 , Shen discloses the semiconductor assembly of claim 8 in which the TIM comprises a viscous liquid material and the capillary tube has a radius dimension between a central axis of the tube and a sidewall of the tube, (See FIG. 3, showing the radius) the radius dimension being selected to maintain a target pressure differential across a vapor-liquid interface between the TIM and air in the capillary tube from the atmosphere surrounding the semiconductor assembly, wherein the pressure differential is determined by the radius dimension, surface tension of the liquid TIM in the capillary tube, and a contact angle between the liquid TIM and the sidewall. (See FIG. 3 and paragraphs [0027]-[0030], where the tube is designed in order to maintain a pressure differential) With regards to claim 10 , Shen discloses the semiconductor assembly of claim 8 in which the broad area surface of the semiconductor comprises a lid, (heat sink/lid 200) wherein the lid has flexure motion relative to the heat exchanger as the semiconductor is operated. (Paragraph [0031]: “ It is noted that the reservoir 212 of the lid 200 and its corresponding lidded flip chip package 222 as showed in FIG. 3 can be flexibly designed according to a specific application. ”) With regards to claim 11 , Shen discloses the semiconductor assembly of claim 10 in which the capillary tube is axially located in line with a point of local maximum excursion of the lid. (see FIG. 3, where the tube 213 is located along an imaginary line in line with a point of local maximum excursion) With regards to claim 12 , Shen discloses the semiconductor assembly of claim 10 in which the capillary tube is axially located in line with a point of local maximum temperature of the lid. (see FIG. 3, where the tube 213 is located along an imaginary line in line with a point of local maximum temperature) With regards to claim 13 , Shen discloses the semiconductor assembly of claim 8 in which the capillary tube is axially located in line with a point of local maximum pressure of the TIM. (see FIG. 3, where the tube 213 is located along an imaginary line in line with a point of local maximum pressure) With regards to claim 14 , Shen discloses the semiconductor assembly of claim 8 in which the capillary tube has an aspect ratio that maximizes resistance to air intrusion into the interstitial air gap through the opening in the heat exchanger exposed to the surrounding atmosphere. (Paragraph [0028]: “ the reservoir 212 can take in the excessive amount of liquid material from the sealed gap 222 to its empty space 212 B, keeping the pressure inside the sealed gap 222 not to be high, and when the volume of the sealed gap 222 gets larger, the reservoir 212 can release the needed amount of liquid material into the sealed gap 222 from its stored liquid material 212 A, keeping the sealed gap 222 to be fully filled. ” Thus, the device is designed to maximize resistance to air intrusion, or “keep[ing] the sealed gap to be fully filled.”) With regards to claim 1 5 , Shen discloses a semiconductor assembly, (FIG. 3) comprising: a semiconductor including a heat-producing die, (flip chip 161 including semiconductor) the semiconductor having a broad area surface through which heat is conducted from the die, wherein the broad area surface deforms with a membrane-like pumping motion as the semiconductor undergoes cyclical thermal loading through operations of the heat-producing die; (It should be noted that, at high enough temperatures, all materials will deform when introduced to extreme enough temperature cycles during operation) a heat exchanger (heat sink/lid 201) having a broad area surface interfacing with the broad area surface of the semiconductor; (see FIG. 3) thermal interface material (TIM) (TIM liquid material 222A) filling a gap between mating broad area surfaces of the semiconductor and heat exchanger, the TIM being flowable with the membrane-like pumping motion of the semiconductor; (see FIG. 3 and at least Paragraphs [0027]-[0028]) a seal (at least ring seal 211A) around a seam between the semiconductor and the heat exchanger that limits excursion of the TIM from the gap as the broad area surface of the semiconductor deforms with the membrane-like pumping motion; (see FIG. 3 and at least Paragraphs [0027]-[0030]) and a capillary tube (connecting hole/tube 213) disposed in the heat exchanger extending from the broad area surface of the heat exchanger to an opening in the heat exchanger that is exposed to an atmosphere surrounding the semiconductor assembly, wherein the capillary tube provides a volume to receive the flowable TIM and wherein the TIM is restorable from the capillary tube. (see FIG. 3 and at least Paragraphs [0027]-[0030], showing the reserve of flowable TIM) With regards to claim 16 , Shen discloses the semiconductor assembly of claim 15 in which the broad area surface of the semiconductor is incorporated into a lid or integrated heat spreader. (lid/heat spreader 201) With regards to claim 17 , Shen discloses the semiconductor assembly of claim 15 in which the TIM is cyclically flowable and restorable from the capillary tube with cyclical thermal loading of the semiconductor. (See FIG. 3 and at least Paragraphs [0027]-[0030]) With regards to claim 18 , Shen discloses the semiconductor assembly of claim 15 further comprising a plurality of capillary tubes (tubes 212/213) distributed in the heat exchanger. (See FIG. 3, see also FIG. 15B, showing another embodiment having multiple tubes) With regards to claim 19 , Shen discloses the semiconductor assembly of claim 15 in which the seal comprises a reworkable edgebond adhesive. (adhesive 253A) With regards to claim 20 , Shen discloses the semiconductor assembly of claim 15 in which the seal around the seam is airtight. (Paragraph [0030]: under a compression force so that the gap 222 becomes a vacuum gap tightly sealed by the seal ring 211A …”) Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Dhane et al. ( US 20200203254 A1 ) – die having heat spreading TIM Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT STEVEN M Page whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-3249 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F: 10:00AM-6:00PM . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Christine S. Kim can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571-272-8548 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEVEN M PAGE/ Primary Patent Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Dec 20, 2023
Application Filed
Mar 24, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
92%
With Interview (+8.6%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 433 resolved cases by this examiner. Grant probability derived from career allow rate.

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