We have DETAILED ACTION
This correspondence is in response to the communications received 06/16/2026. Claim 8 has been withdrawn. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species B in the reply filed on 06/16/2026 is acknowledged.
Claim 8 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/16/2026.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/20/2023, 04/23/2024, and 05/31/2024 have been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 and 9-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 requires “a second staircase structure horizontally extending from the vertical stack structure of a second of the two of the memory array regions and comprising second steps at horizontal edges of the conductive structures of the vertical stack structure of the first of the two of the memory array regions”. It is unclear how the second staircase structure which extends from the second of the two of the memory array regions has second steps at horizontal edges of the conductive structures of the vertical stack structure of the first of the two of the memory array regions. Based on Fig. 1A, each memory array region interpreted as 102 has separate instances of the conductive structures interpretated as 132. Therefore, for the purposes of examination, the above limitation will be interpretated as “a second staircase structure horizontally extending from the vertical stack structure of a second of the two of the memory array regions and comprising second steps at horizontal edges of the conductive structures of the vertical stack structure of the second of the two of the memory array regions”. Claims 2-7 and 9-11 are rejected for their dependence on claim 1.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, a microelectronic device (100), comprising:
memory array regions (102) individually comprising:
a vertical stack of memory cells (120), comprising:
a vertical stack of access devices (130); and
a vertical stack of capacitors (150) horizontally neighboring the vertical stack of access devices (see Fig. 1B); and
a vertical stack structure (135) comprising conductive structures (132) vertically spaced from one another and horizontally extending through the vertical stack of memory cells (see Fig. 1C), the conductive structures neighboring the memory cells of the vertical stack of memory cells (see Fig. 1B);
a staircase region (103) horizontally between two of the memory array regions horizontally neighboring one another (see Fig. 1A), the staircase region comprising:
a first staircase structure ("a first staircase structure 174 horizontally extending (e.g., in the X-direction) from a sub-array 105 horizontally extends (e.g., in the X-direction) into a first staircase region 103", [0080]) horizontally extending from the vertical stack structure of a first of the two of the memory array regions and comprising first steps at horizontal edges of the conductive structures of the vertical stack structure of the first of the two of the memory array regions (see Fig. 1A);
a second staircase structure ("a second staircase structure 174 horizontally extending (e.g., in the X-direction) from the sub-array 105 horizontally extends (e.g., in the X-direction) into a second staircase region 103 horizontally neighboring (e.g., in the X-direction) the first staircase region103", [0080]) horizontally extending from the vertical stack structure of a second of the two of the memory array regions and comprising second steps at horizontal edges of the conductive structures of the vertical stack structure of the first of the two of the memory array regions(see Fig. 1A); and
lateral conductive contacts (190) providing a conductive path between the first steps of the first staircase structure and the second steps of the second staircase structure (see Fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-12, and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Simsek-Ege (US 20220399309 A1, published 12/15/2022) in view of Choi (US 9,361,949 B2, published 06/07/2016).
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Regarding claim 1, Figs. 1A-1K of Simsek-Ege disclose a microelectronic device (“first microelectronic device structure 100”, [0024]), comprising:
memory array regions (“array region 105”, [0025], where “array region 105 may include greater than eight vertical stacks of memory cells 110”, [0026], thus 105 is a memory array region) individually comprising:
a vertical stack of memory cells (110, [0026]), comprising:
a vertical stack of access devices (“vertical stack of access devices 112”, [0026]); and
a vertical stack of capacitors (“vertical stack of storage devices 114”, [0026], where “storage devices 114 individually comprise capacitors”, [0038]) horizontally neighboring the vertical stack of access devices (as seen in Fig. 1E, 114 are horizontally neighboring 112); and
a vertical stack structure (“stack structure 125”, [0029]) comprising conductive structures (together “first conductive structure 120”, [0027] and “conductive pillar structures 126”, [0032], form a conductive structure) vertically spaced from one another (as seen in Fig. 1E, 120 are vertically spaced from one another) and horizontally extending through the vertical stack of memory cells (as seen in Fig. 1A, 120 extend horizontally through 110), the conductive structures neighboring the memory cells of the vertical stack of memory cells (as seen in Fig. 1A, 120 are neighboring 112);
a staircase region (“one or more peripheral regions 150”, [0025], as seen in Fig. 1C, 150 forms a staircase structure) horizontally between two of the memory array regions horizontally neighboring one another (Simsek-Ege does not disclose a staircase region horizontally between two of the memory array regions, therefore a secondary reference will be used to teach this limitation below), the staircase region comprising:
a first staircase structure horizontally extending from the vertical stack structure of a first of the two of the memory array regions (as seen in Fig. 1C, 150 includes a first staircase structure horizontally extending from the vertical stack structure of 105, for reference, the instance of 150 as seen on the right side of Fig. 1C comprises the first staircase structure) and comprising first steps at horizontal edges of the conductive structures of the vertical stack structure of the first of the two of the memory array regions (as seen in Fig. 1C, 150 has first steps at horizontal edges of 120);
Simsek-Ege fails to disclose “a staircase region horizontally between two of the memory array regions horizontally neighboring one another,
a second staircase structure horizontally extending from the vertical stack structure of a second of the two of the memory array regions and comprising second steps at horizontal edges of the conductive structures of the vertical stack structure of the first of the two of the memory array regions; and
lateral conductive contacts providing a conductive path between the first steps of the first staircase structure and the second steps of the second staircase structure.”
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However, in a similar field of endeavor, Figs. 2-4 of Choi teach a staircase region (as seen in Figs. 3A and 4, “contact region CONTACT”, col. 5, lines 26-27, is a staircase region) horizontally between two of the memory array regions horizontally neighboring one another (as seen in Fig. 3A, CONTACT is horizontally between “stacked structures S11 to S13 and S21 to S23”, col. 5, line 25, where each of S11-S13 and S21-S23 are equivalent to a separate instance of 110 of Simsek-Ege, further, as seen in Figs. 3A and 4, S11-S13 and S21-S23 are all horizontally neighboring one another, for ease of reference, the left instance of “cell region CELL”, col. 5, line 26, is a first memory array region, and the staircase structure corresponding to S11 as seen in Fig. 4 is a first staircase structure),
a second staircase structure (the staircase structure corresponding to S21 as seen in Fig. 4 is a second staircase structure) horizontally extending from the vertical stack structure of a second of the two of the memory array regions (as seen in Fig. 4, the staircase structure corresponding to S21 is horizontally extending from the right instance of CELL which is a second of the two memory array regions) and comprising second steps at horizontal edges of the conductive structures of the vertical stack structure of the first of the two of the memory array regions (as the staircase structure corresponding to S21 is a second instance of 110 of Simsek-Ege, it comprises second steps at horizontal edges of 150 of Simsek-Ege); and
lateral conductive contacts (“first to n-th drain selection lines DSL1 to DSLn”, col. 5, lines 33-34) providing a conductive path between the first steps of the first staircase structure and the second steps of the second staircase structure (as seen in Fig. 4, DSLn provides a conductive path between the steps of the staircase structure corresponding to S11 and the steps of the staircase structure corresponding to S21).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a staircase region horizontally between two of the memory array regions horizontally neighboring one another,
a second staircase structure horizontally extending from the vertical stack structure of a second of the two of the memory array regions and comprising second steps at horizontal edges of the conductive structures of the vertical stack structure of the first of the two of the memory array regions; and
lateral conductive contacts providing a conductive path between the first steps of the first staircase structure and the second steps of the second staircase structure” as taught by Choi in the system of Simsek-Ege for the purpose of increasing memory density by compactly packing the contact region of neighboring memory cells.
Regarding claim 2, Figs. 1A-1K of Simsek-Ege in combination with Figs. 2-4 of Choi disclose the microelectronic device of claim 1, Figs. 2-4 of Choi further disclose wherein a vertically uppermost one of the first steps of the first staircase structure shares a conductive path with a vertically lowermost one of the second steps of the second staircase structure by means of one of the lateral conductive contacts (as seen in Fig. 4, a vertically uppermost one of the first steps of the staircase structure corresponding to S11 shares a conductive path via DSLn with a vertically lower most one of the second steps of the staircase structure corresponding to S21).
Regarding claim 3, Figs. 1A-1K of Simsek-Ege in combination with Figs. 2-4 of Choi disclose the microelectronic device of claim 1, Figs. 2-4 of Choi further disclose wherein:
the vertical stack structure of the first of the two of the memory array regions extends in a first horizontal direction (as seen in Fig. 4, S11 extends in the horizontal I/I’ direction); and
the first staircase structure horizontally neighbors the second staircase structure in a second horizontal direction orthogonal to the first horizontal direction (as seen in Fig. 4, the staircase structure corresponding to S11 horizontally neighbors the staircase structure corresponding to S21 in the second horizontal direction II/II’ which is orthogonal to I/I’).
Regarding claim 4, Figs. 1A-1K of Simsek-Ege in combination with Figs. 2-4 of Choi disclose the microelectronic device of claim 3, Figs. 2-4 of Choi further disclose wherein the first steps of the first staircase structure horizontally overlap the second steps of the second staircase structure in the first horizontal direction (as seen in Fig. 4, the first steps of the staircase structure corresponding to S11 horizontally overlap the second steps of the staircase structure corresponding to S21 in the I/I’ direction).
Regarding claim 5, Figs. 1A-1K of Simsek-Ege in combination with Figs. 2-4 of Choi disclose the microelectronic device of claim 4, Figs. 2-4 of Choi further disclose wherein:
an uppermost one of the first steps of the first staircase structure is substantially aligned with a lowermost one of the second steps of the second staircase structure in the first horizontal direction (as seen in Figs. 3A and 4, an uppermost one of the first steps of the staircase structure corresponding to S11 is substantially aligned with a lowermost one of the second steps of the staircase structure corresponding to S21); and
an uppermost one of the second steps of the second staircase structure is substantially aligned with a lowermost one of the first steps of the first staircase structure in the first horizontal direction (as seen in Figs. 3A and 4, an uppermost one of the second steps of the staircase structure corresponding to S21 is substantially aligned with a lowermost one of the first steps of the staircase structure corresponding to S11).
Regarding claim 6, Figs. 1A-1K of Simsek-Ege in combination with Figs. 2-4 of Choi disclose the microelectronic device of claim 1, Figs. 1A-1K of Simsek-Ege further disclose wherein the first steps of the first staircase structure comprise every other one of the conductive structures of the vertical stack structure of the first of the two of the memory array regions (as seen in Fig. 1C, the first steps of 150 comprise every other one of 120).
Regarding claim 7, Figs. 1A-1K of Simsek-Ege in combination with Figs. 2-4 of Choi disclose the microelectronic device of claim 6, Figs. 1A-1K of Simsek-Ege further disclose further comprising an additional staircase region (as seen in Fig. 1C, the left instance of 150 is an additional staircase region) comprising additional staircase structures horizontally extending from the vertical stack structure of the first of the two of the memory array regions and the vertical stack structure of the second of the two of the memory array regions (after combination with Choi, there will be additional staircase structures horizontally extending from the both S11 and S21 of Choi), the additional staircase region horizontally spaced from the staircase region by one of the two of the memory array regions (as seen in Fig. 1C, the left and right instances of 150 are horizontally spaced by 105).
Regarding claim 9, Figs. 1A-1K of Simsek-Ege in combination with Figs. 2-4 of Choi disclose the microelectronic device of claim 1, Figs. 2-4 of Choi further disclose wherein the vertical stack of memory cells of a first of the memory array regions is horizontally offset from the vertical stack of memory cells of a second of the memory array regions in a horizontal direction in which the lateral conductive contacts extend (as seen in Fig. 3A, S11 is horizontally offset from S21 in the horizontal direction in which DSL1-DSLn extend).
Regarding claim 10, Figs. 1A-1K of Simsek-Ege in combination with Figs. 2-4 of Choi disclose the microelectronic device of claim 1, Figs. 1A-1K of Simsek-Ege further disclose wherein the conductive structures of the vertical stack structure of the first of the two of the memory array regions comprise word lines configured to be electrical communication with access devices of the first of the two of the memory array regions (“conductive structures 120 (also referred to herein as “first conductive lines” or “word lines”) ... The conductive structures 120 may be configured to provide sufficient current through a channel region (e.g., channel material 151 (FIG. 1B)) of each of the access devices 112”, [0027]).
Regarding claim 11, Figs. 1A-1K of Simsek-Ege in combination with Figs. 2-4 of Choi disclose the microelectronic device of claim 1, Figs. 1A-1K of Simsek-Ege further disclose wherein the conductive structures of the vertical stack structure of the first of the two of the memory array regions comprise digit lines (“The conductive pillar structures 126 may also be referred to herein as “digit lines”, “second conductive lines”, or “digit line pillar structures”. The conductive pillar structures 126 may be electrically coupled to the access devices 112”, [0032]) vertically overlying the access devices of the first of the two of the memory array regions (as seen in Fig. 1A and 1B, 126 are vertically overlying 112).
Regarding claim 12, Figs. 1A-1K of Simsek-Ege disclose a microelectronic device (“first microelectronic device structure 100”, [0024]), comprising:
a memory array bank comprising a first memory array (“array region 105”, [0025], where “array region 105 may include greater than eight vertical stacks of memory cells 110”, [0026], thus 105 is a memory array region) and a second memory array (Simsek-Ege does not disclose a second memory array, however a secondary reference will be used to teach this limitation below), the first memory array and the second memory array individually comprising (while the secondary reference will be used to teach the secondary memory array and the arrangement between the memory arrays, the structure disclosed by Simsek-Ege will be applicable to both the first and second memory arrays):
vertical stacks of dynamic random access memory (DRAM) cells (110, [0026], where 100 is “a memory device, such as a 3D DRAM memory device”, thus 110 can be DRAM cells), each DRAM cell comprising a storage device (“storage device 114”, [0027]) horizontally neighboring an access device (“access devices 112”, [0027], and as seen in Fig. 1E, 114 are horizontally neighboring 112); and
a vertical stack structure (“stack structure 125”, [0029]) comprising vertically spaced conductive structures (“first conductive structure 120”, [0027], as seen in Fig. 1E, 120 are vertically spaced from one another) horizontally extending through the vertical stacks of DRAM cells (as seen in Fig. 1A, 120 extend horizontally through 110), the conductive structures of the vertical stack structure neighboring the DRAM cells of the vertical stacks of DRAM cells (as seen in Fig. 1A, 120 are neighboring 112 and 114); and
a staircase region (“one or more peripheral regions 150”, [0025], as seen in Fig. 1C, 150 forms a staircase structure) horizontally between the first memory array and the second memory array (this limitation will also be taught by the secondary reference below), the staircase region comprising:
a first staircase structure horizontally extending from the vertical stack structure of the first memory array (as seen in Fig. 1C, 150 includes a first staircase structure horizontally extending from the vertical stack structure of 105, for reference, the instance of 150 as seen on the right side of Fig. 1C comprises the first staircase structure);
Simsek-Ege fails to disclose “a memory array bank comprising a first memory array and a second memory array,
a staircase region horizontally between the first memory array and the second memory array the staircase region comprising:
a second staircase structure horizontally extending from the vertical stack structure of the second memory array; and
lateral conductive contacts horizontally extending from the first staircase structure to the second staircase structure, each lateral conductive contact operably coupled to one step of the first staircase structure and one step of the second staircase structure.”
However, in a similar field of endeavor, Figs. 2-4 of Choi teach a memory array bank comprising a first memory array and a second memory array (as seen in Fig. 3A, the left instance of “cell region CELL”, col. 5, line 26, is a first memory array, and the right instance of CELL is a second memory array, where together the two instances of CELL are equivalent to two instances of 105 of Simsek-Ege and comprise a memory array bank, further “stacked structures S11 to S13 and S21 to S23”, col. 5, line 25 are equivalent to separate instances of 110 of Simsek-Ege),
a staircase region (as seen in Figs. 3A and 4, “contact region CONTACT”, col. 5, lines 26-27, is a staircase region and equivalent to 150 of Simsek-Ege) horizontally between the first memory array and the second memory array the staircase region (as seen in Fig. 3A, CONTACT is between the left and right instances of CELL) comprising:
a second staircase structure (the staircase structure corresponding to S21 as seen in Fig. 4 is a second staircase structure) horizontally extending from the vertical stack structure of the second memory array (as seen in Fig. 4, the staircase structure corresponding to S21 is horizontally extending from the right instance of CELL); and
lateral conductive contacts (“first to n-th drain selection lines DSL1 to DSLn”, col. 5, lines 33-34, here DSLn and DSLn-1 are interpretated as the lateral conductive contacts) horizontally extending from the first staircase structure to the second staircase structure (as seen in Fig. 4, DSLn extends from the staircase structure corresponding to S11 and the staircase structure corresponding to S21), each lateral conductive contact operably coupled to one step of the first staircase structure and one step of the second staircase structure (as seen in Fig. 4, DSLn is operable coupled to one step of the staircase structure corresponding to S11 and one step of the staircase structure corresponding to S21).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement a memory array bank comprising a first memory array and a second memory array,
a staircase region horizontally between the first memory array and the second memory array the staircase region comprising:
a second staircase structure horizontally extending from the vertical stack structure of the second memory array; and
lateral conductive contacts horizontally extending from the first staircase structure to the second staircase structure, each lateral conductive contact operably coupled to one step of the first staircase structure and one step of the second staircase structure” as taught by Choi in the system of Simsek-Ege for
the purpose of increasing memory density by compactly packing the contact region of neighboring memory cells.
Regarding claim 14, Figs. 1A-1K of Simsek-Ege in combination with Figs. 2-4 of Choi disclose the microelectronic device of claim 12, Figs. 2-4 of Choi further disclose wherein a lower one half of the steps of the first staircase structure horizontally overlap with a lower one half of the steps of the second staircase structure (as seen in Fig. 4, a lower one half of the steps of the staircase structure corresponding to S11 horizontally overlap with a lower one half of the steps of the staircase structure corresponding to S21).
Regarding claim 15, Figs. 1A-1K of Simsek-Ege in combination with Figs. 2-4 of Choi disclose the microelectronic device of claim 12, Figs. 2-4 of Choi further disclose further comprising additional lateral conductive contacts (DSL1 - DNSLn-2 are additional lateral conductive contacts) horizontally extending between a third staircase structure extending from an additional vertical stack structure of the first memory array and a fourth staircase structure horizontally extending from an additional vertical stack structure of the second memory array (as seen in Figs. 3A and 4, DSL1 - DNSLn-2 horizontally extend between a third staircase structure horizontally extending from S12 and a fourth staircase structure horizontally extending from S22).
Regarding claim 16, Figs. 1A-1K of Simsek-Ege disclose a memory (“first microelectronic device structure 100 (e.g., a memory device, such as a 3D DRAM memory device)”, [0024]), comprising:
a first memory array region comprising first vertical stacks of first dynamic random access memory (DRAM) cells (“array region 105”, [0025], where “array region 105 may include greater than eight vertical stacks of memory cells 110”, [0026], thus 105 is a memory array region, and as 100 may be a DRAM memory device, 110 may be DRAM memory cells), each of the first DRAM cells comprising a storage device of a vertical stack of storage devices “vertical stack of storage devices 114”, [0026]) and a horizontally neighboring access device of a vertical stack of access devices (“vertical stack of access devices 112”, [0026], and as seen in Fig. 1E, 114 are horizontally neighboring 112);
a first vertical stack structure (“stack structure 125”, [0029]) comprising vertically spaced first conductive structures (“first conductive structure 120”, [0027], as seen in Fig. 1E, 120 are vertically spaced from one another) horizontally extending through the first memory array region (as seen in Fig. 1C, 120 horizontally extend through 105) and terminating at a first staircase structure in a staircase region horizontally neighboring the first memory array region (as seen in Fig. 1C, 120 terminate at a first staircase structure in “peripheral regions 150”, [0025], which is a staircase region, where 150 is horizontally neighboring 105);
Simsek-Ege fails to disclose “a second memory array region comprising second vertical stacks of second DRAM cells;
a second vertical stack structure comprising second vertically spaced conductive structures horizontally extending through the second memory array region and terminating at a second staircase structure in the staircase region; and
lateral conductive contacts electrically connecting steps of the first staircase structure to steps of the second staircase structure.”
However, in a similar field of endeavor, Figs. 2-4 of Choi teach a second memory array region comprising second vertical stacks of second DRAM cells (as seen in Fig. 3A, the left instance of “cell region CELL”, col. 5, line 26, is a first memory array, and the right instance of CELL is a second memory array, where together the two instances of CELL are equivalent to two instances of 105 of Simsek-Ege, thus both instances of CELL comprise vertical stacks of DRAM cells, while Choi is used for the overall device structure, the specifics of the second array will mirror those of the first array disclosed by Simsek-Ege);
a second vertical stack structure comprising second vertically spaced conductive structures horizontally extending through the second memory array region and terminating at a second staircase structure in the staircase region (as discussed above, the second vertical stack structure is formed identically to a second instance 125 of Simsek-Ege including a second 120 horizontally extend through 105 and terminating at a second staircase region in 150, where “stacked structures S11 to S13 and S21 to S23”, col. 5, line 25 of Choi are equivalent to separate instances of 125 of Simsek-Ege, the first and second vertical stack structures corresponding to S11 and S21 of Choi respectively, further as seen in Fig. 4, each of S11-S13 and S21-S23 have a corresponding staircase structure); and
lateral conductive contacts “first to n-th drain selection lines DSL1 to DSLn”, col. 5, lines 33-34) electrically connecting steps of the first staircase structure to steps of the second staircase structure (as seen in Fig. 4, DSLn provides a conductive path between the steps of the staircase structure corresponding to S11 and the steps of the staircase structure corresponding to S21).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a second memory array region comprising second vertical stacks of second DRAM cells;
a second vertical stack structure comprising second vertically spaced conductive structures horizontally extending through the second memory array region and terminating at a second staircase structure in the staircase region; and
lateral conductive contacts electrically connecting steps of the first staircase structure to steps of the second staircase structure” as taught by Choi in the system of Simsek-Ege for the purpose of increasing memory density by compactly packing the contact region of neighboring memory cells.
Regarding claim 17, Figs. 1A-1K of Simsek-Ege in combination with Figs. 2-4 of Choi further disclose the microelectronic device of claim 16, Figs. 2-4 of Choi further disclose wherein the staircase region horizontally intervenes between the first memory array region and the second memory array region (as seen in Fig. 3A, CONTACT horizontally intervenes between the left and right instances of CELL).
Regarding claim 18, Figs. 1A-1K of Simsek-Ege in combination with Figs. 2-4 of Choi disclose the microelectronic device of claim 16, Figs. 2-4 of Choi further disclose wherein:
the first memory array region is horizontally spaced from the second memory array region in a first horizontal direction (as seen in Fig. 3A, the left instance of CELL is horizontally spaced from the right instance of Cell in the I/II’ direction); and
the lateral conductive contacts horizontally extend in a second horizontal direction (as seen in Fig. 3A, DSL1-DSLn extend in the II/II’ direction) orthogonal to the first horizontal direction (as seen in Fig. 3A, the II/II’ direction is orthogonal to the I/I’ direction).
Regarding claim 19, Figs. 1A-1K of Simsek-Ege in combination with Figs. 2-4 of Choi disclose the microelectronic device of claim 16, Figs. 2-4 of Choi further disclose wherein the first DRAM cells are horizontally offset from the second DRAM cells in a first horizontal direction and a second horizontal direction (as seen in Fig. 4, S11 are horizontally offset from S21 in the I/I’ direction and the II/II’ direction, where as previously mentioned, S11 and S21 of Choi are equivalent to 125 of Simsek-Ege which contains DRAM cells).
Regarding claim 20, Figs. 1A-1K of Simsek-Ege in combination with Figs. 2-4 of Choi disclose the microelectronic device of claim 16, Figs. 2-4 of Choi further disclose further comprising conductive contact structures (“first contact plugs CP1”, col. 5, lines 30-31 and “second contact plugs CP2”, col. 5, line 32), individually in contact with the steps of the first staircase structure and the steps of the second staircase structure (as seen in Fig. 4, CP1 and CP2 are individually in contact with the steps of the staircase structure corresponding to S11 and the staircase structure corresponding to S21), the lateral conductive contacts in contact with the conductive contact structures (as seen in Fig. 4, CP1 and CP2 are in contact with DSLn).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Simsek-Ege (US 20220399309 A1, published 12/15/2022) in view of Choi (US 9,361,949 B2, published 06/07/2016) in view of Redaelli (US 10,658,427 B2, published 05/19/2020).
Regarding claim 13, Figs. 1A-1K of Simsek-Ege in combination with Figs. 2-4 of Choi disclose the microelectronic device of claim 12, Figs. 1A-1K of Simsek-Ege further disclose further comprising vertically extending word lines (Simsek-Ege does not disclose vertically extending word lines, however Simsek-Ege does disclose “conductive pillar structures 126”, [0032], which as seen in Fig. 1E, extend in the vertical direction, further Simsek-Ege discloses “The conductive pillar structures 126 may also be referred to herein as “digit lines””, [0032], a secondary reference will be used below to equate word lines and digit lines), each vertically extending word line vertically extending along sides of access devices of a vertical stack of DRAM cells of the vertical stacks of DRAM cells (as seen in Fig. 1E, 126 vertically extend along sides of 112).
Simsek-Ege in combination with Choi fails to disclose “vertically extending word lines”.
However, in a similar field of endeavor, Redaelli teaches vertically extending word lines (“In some examples, word lines 110 and bit lines 115 may be referred to as access lines, and bit lines 115 may also be known digit lines 115. References to access lines, word lines, and bit lines, or their analogues, are interchangeable without loss of understanding or operation”, col. 5, lines 22-27, thus 126 of Simsek-Ege can be considered vertically extending word lines).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “vertically extending word lines” as taught by Redaelli in the system of Simsek-Ege in combination with Choi for the purpose of clarifying conductive element functionality.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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