Prosecution Insights
Last updated: August 17, 2026
Application No. 18/391,566

STORAGE DEVICE, OPERATION METHOD OF STORAGE DEVICE, AND OPERATION METHOD OF STORAGE CONTROLLER

Final Rejection §103
Filed
Dec 20, 2023
Priority
Feb 01, 2023 — RE 10-2023-0013596
Examiner
LEIBOVICH, YAIR
Art Unit
2114
Tech Center
2100 — Computer Architecture & Software
Assignee
Samsung Electronics Co., Ltd.
OA Round
2 (Final)
90%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
867 granted / 964 resolved
+34.9% vs TC avg
Moderate +11% lift
Without
With
+10.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
15 currently pending
Career history
983
Total Applications
across all art units

Statute-Specific Performance

§101
16.5%
-23.5% vs TC avg
§103
34.1%
-5.9% vs TC avg
§102
23.8%
-16.2% vs TC avg
§112
19.4%
-20.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 964 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicants’ arguments with respect to independent claim have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Allowable Subject Matter Claims 2-3, 5-15, and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 4, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon (US 2023/0087 A1), and further in view of Huang (US 2008/0018651 A1). For claim 1, Yoon teaches a storage device comprising: a nonvolatile memory device including a memory circuit configured to store first device information, and the nonvolatile memory device configured to operate based on the first device information (see abstract, figure 1, paragraphs [0003], [0005],[0031[, and other locations: view write operations as store operation: view boot; view boot information as said first device information; view executing boot as said operate based on;); a storage controller configured to control the nonvolatile memory device (see figure 1: view block 200 as said controller); and a buffer memory configured to store map data managed by the storage controller and to store second device information being a backup of the first device information (see [0039]: view system data loaded into buffer as said backup; system data includes mapping), wherein the first device information includes information about an operation parameter and an operation frequency of the nonvolatile memory device (see [0039]: view number of operation per memory block as said operation frequency), and wherein the storage controller is further configured to perform a recovery operation on the first device information stored in the memory circuit of the nonvolatile memory device (see abstract and other locations: view restore system data as said recovery operation), [], and wherein, during the recovery operation, the storage device is configured such that the storage controller reads the second device [] memory and reloads the second device information to the memory circuit (see abstract and other locations: using after recovering means dat was reloaded; also booting/rebooting always includes loading/reloading). Yoon does not explicitly teach “based on the second device information stored in the buffer memory” and “information from the buffer”. However, Huang teaches based on the second device information stored in the buffer memory (see [0011]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoon to include “teaches based on the second device information stored in the buffer memory” and “information from the buffer”, as taught by Huang, because each one of Yoon and Huang teach booting from flash therefore they are analogous arts and because buffer is fast memory that stores available copy (see [0011]). For claim 16, The claim recites essentially similar limitations as claim 1; recovery suggests failure; claim 16 is a method. For claim 20, Yoon teaches an operation method of a storage device which includes a storage controller, a nonvolatile memory device, and a buffer memory, the method comprising: setting, by the nonvolatile memory device, first device information to a memory circuit included in the nonvolatile memory device; obtaining, by the storage controller, the first device information from the nonvolatile memory device and storing the first device information in the buffer memory as second device information (see rejection to claim 1); and when an operation count of the nonvolatile memory device reaches a threshold value, performing, by the storage controller, a recovery operation on the first device information stored in the memory circuit based on the second device information stored in the buffer memory (see rejection to claim 1 or 16: view first failure as said threshold value), wherein the operation count of the nonvolatile memory device includes a read count, a program count, or the number of P/E cycles of the nonvolatile memory device (see [0039], [0112]: failure/error occurs when first read or write fails), and wherein the first device information includes information about an operation parameter and an operation frequency of the nonvolatile memory device (see rejection to claim 1). For claim 4, The claim recites essentially similar limitations as claim 20. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to YAIR LEIBOVICH whose telephone number is (571)270-3796. The examiner can normally be reached 8:00am-5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached at 571-272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YAIR LEIBOVICH/Primary Examiner, Art Unit 2114
Read full office action

Prosecution Timeline

Dec 20, 2023
Application Filed
Sep 05, 2025
Non-Final Rejection mailed — §103
Oct 02, 2025
Interview Requested
Dec 01, 2025
Response Filed
Aug 03, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12705129
PAUSING MEMORY SYSTEM BASED ON CRITICAL EVENT
1y 8m to grant Granted Aug 11, 2026
Patent 12699530
MEMORY SYSTEM AND CONTROL METHOD
2y 1m to grant Granted Aug 04, 2026
Patent 12688107
PREDICTIVE MONITORING OF SOFTWARE APPLICATION FRAMEWORKS USING MACHINE-LEARNING-BASED TECHNIQUES
1y 10m to grant Granted Jul 21, 2026
Patent 12688082
DETECTING INJECTION OF FAULTS IN PROGRAM COUNTERS ALTERING EXECUTION OF BASIC BLOCKS OF INSTRUCTIONS
1y 8m to grant Granted Jul 21, 2026
Patent 12664055
NETWORK SYSTEM FOR RUNNING DISTRIBUTED ENVIRONMENT APPLICATIONS AND FAULT TOLERANCE METHOD USING THE SAME
2y 3m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
90%
Grant Probability
99%
With Interview (+10.9%)
2y 6m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 964 resolved cases by this examiner. Grant probability derived from career allowance rate.

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