DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/21/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the second horizontal direction” in line 8 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 2 recites “a vertical direction” in line 5 of the claim, however “a vertical direction” element was already introduced earlier in line 16 of claim 1, which claim 2 depends from, and thereby it is unclear whether the “a vertical direction” in line 5 of the claim is directed to that same element and therefore should be properly amended to “the vertical direction” or directed to an entirely different element and therefore should be amended with specific language to distinguish it from the already introduced element.
Claim 8 recites the limitation “the second horizontal direction” in line 8 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation “the sidewall of the peripheral circuit offset layer” in line 8 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites “a first horizontal direction” in line 5 of the claim, however “a first horizontal direction” element was already introduced earlier in line 4 of claim 8, which claim 11 depends from, and thereby it is unclear whether the “a first horizontal direction” in line 5 of the claim is directed to that same element and therefore should be properly amended to “the first horizontal direction” or directed to an entirely different element and therefore should be amended with specific language to distinguish it from the already introduced element.
Claim 13 recites “a sidewall of the peripheral circuit gate structure” in lines 3-4 of the claim, however “a sidewall of the peripheral circuit gate structure” element was already introduced earlier in lines 10-11 of claim 8, which claim 13 depends from, and thereby it is unclear whether the “a sidewall of the peripheral circuit gate structure” in lines 3-4 of the claim is directed to that same element and therefore should be properly amended to “the sidewall of the peripheral circuit gate structure” or directed to an entirely different element and therefore should be amended with specific language to distinguish it from the already introduced element.
Claim 16 recites the limitation “the second horizontal direction” in line 8 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 19 recites “a sidewall of the peripheral circuit gate structure” in lines 3-4 of the claim, however “a sidewall of the peripheral circuit gate structure” element was already introduced earlier in lines 10-11 of claim 16, which claim 19 depends from, and thereby it is unclear whether the “a sidewall of the peripheral circuit gate structure” in lines 3-4 of the claim is directed to that same element and therefore should be properly amended to “the sidewall of the peripheral circuit gate structure” or directed to an entirely different element and therefore should be amended with specific language to distinguish it from the already introduced element.
Note the dependent claims 2-7, 9-15 and 17-20 necessarily inherit the indefiniteness of the claims on which they depend.
Allowable Subject Matter
Claims 1-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Regarding independent claim 1, Figures 54-56 of Park et al. (US 2022/0262731 A1, hereinafter “Park”) disclose a semiconductor device comprising:
a substrate 500 (“substrate”- ¶0119) including a cell region I (“cell region”- ¶0120) and a peripheral circuit region II (“peripheral circuit region”- ¶0120);
an active region 503 (“active patterns”- ¶0119) defined by a device isolation layer 510 (“isolation patterns”- ¶0119) in the substrate 500 in the cell region I;
a cell word line 1060 (“electrode”- ¶0181) extending across the active region 503 in a first horizontal direction within the substrate 500 in the cell region I;
a cell bit line 795 (“bit line”- ¶0140) extending in a second horizontal crossing the first horizontal direction on the substrate 500 in the cell region I;
a peripheral circuit gate structure 720 (“gate structure”- ¶0130) extending in the second horizontal direction on the substrate 500 in the peripheral circuit region II;
a peripheral circuit spacer structure 750 (“gate spacer structure”- ¶0130) disposed on a sidewall of the peripheral circuit gate structure 720;
a peripheral circuit etch stop layer 760 (“etch stop layer”- ¶0134) disposed on the substrate 500 in the peripheral circuit region II; and
a peripheral circuit contact 970 (“contact plug”- ¶0172) connected to the peripheral circuit region II of the substrate 500 by penetrating the peripheral circuit etch stop layer 760 in a vertical direction, and
wherein the peripheral circuit spacer structure 750 includes nitride (¶¶0027, 0130).
Park does not expressly disclose the peripheral circuit etch stop layer separated from the peripheral circuit gate structure and the peripheral circuit spacer structure and the peripheral circuit etch stop layer has an end portion positioned between the peripheral circuit contact and the peripheral circuit spacer structure.
Thus, regarding independent claim 1 (which claims 2-7 depend from), the prior art of record including Park, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “a peripheral circuit etch stop layer… separated from the peripheral circuit gate structure and the peripheral circuit spacer structure” and “the peripheral circuit etch stop layer has an end portion positioned between the peripheral circuit contact and the peripheral circuit spacer structure”.
Regarding independent claim 8, Figures 54-56 of disclose a semiconductor device comprising:
a substrate 500 (“substrate”- ¶0119) including a cell region I (“cell region”- ¶0120) and a peripheral circuit region II (“peripheral circuit region”- ¶0120);
an active region 503 (“active patterns”- ¶0119) defined by a device isolation layer 510 (“isolation patterns”- ¶0119) in the substrate 500 in the cell region I;
a cell word line 1060 (“electrode”- ¶0181) extending across the active region 503 in a first horizontal direction within the substrate 500 in the cell region I;
a cell bit line 795 (“bit line”- ¶0140) extending in a second horizontal crossing the first horizontal direction on the substrate 500 in the cell region I;
a peripheral circuit gate structure 720 (“gate structure”- ¶0130) extending in the second horizontal direction on the substrate 500 in the peripheral circuit region II;
a peripheral circuit offset layer 750 (“gate spacer structure”- ¶0130) arranged on a sidewall of the peripheral circuit gate structure 720 and including nitride (¶¶0027, 0130);
a peripheral circuit etch stop layer 760 (“etch stop layer”- ¶0134) arranged on the substrate 500 in the peripheral circuit region II, wherein the peripheral circuit etch stop layer 760 (which is analogous to 220) includes nitride (¶0029); and
a peripheral circuit contact 970 (“contact plug”- ¶0172) connected to the peripheral circuit region II of the substrate 500 by penetrating a peripheral circuit interlayer insulating layer 770 (“insulating interlayer”- ¶0135) and the peripheral circuit etch stop layer 760 in a vertical direction.
Park does not expressly disclose the peripheral circuit etch stop layer separated from the peripheral circuit offset layer with the peripheral circuit interlayer insulating layer disposed between the peripheral circuit etch stop layer and the peripheral circuit offset layer.
Thus, regarding independent claim 8 (which claims 9-15 depend from), the prior art of record including Park, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “a peripheral circuit etch stop layer… separated from the peripheral circuit offset layer with the peripheral circuit interlayer insulating layer disposed between the peripheral circuit etch stop layer and the peripheral circuit offset layer”.
Regarding independent claim 16, Figures 54-56 of disclose a semiconductor device comprising:
a substrate 500 (“substrate”- ¶0119) including a first region I (“cell region”- ¶0120) and a second region II (“peripheral circuit region”- ¶0120);
an active region 503 (“active patterns”- ¶0119) defined by a device isolation layer 510 (“isolation patterns”- ¶0119) in the substrate 500 in the first region I;
a cell word line 1060 (“electrode”- ¶0181) extending across the active region 503 in a first horizontal direction within the substrate 500 in the first region I;
a cell bit line 795 (“bit line”- ¶0140) extending in a second horizontal crossing the first horizontal direction on the substrate 500 in the first region I;
a peripheral circuit gate structure 720 (“gate structure”- ¶0130) extending in the second horizontal direction on the substrate 500 in the second region II;
a peripheral circuit spacer structure 750 (“gate spacer structure”- ¶0130) arranged on a sidewall of the peripheral circuit gate structure 720 and including a peripheral circuit offset layer 730 (“gate spacers”- ¶0133), which includes silicon nitride (¶¶0027, 0130), and a peripheral circuit spacer 740 (“gate spacers”- ¶0133) that is separated from the peripheral circuit gate structure 720 with the peripheral circuit offset layer 730 disposed between peripheral circuit spacer 740 and the peripheral circuit gate structure 720 and includes silicon oxide (¶¶0027, 0130);
a peripheral circuit etch stop layer 760 (“etch stop layer”- ¶0134) arranged on the substrate 500 in the second region II, wherein the peripheral circuit etch stop layer 760 (which is analogous to 220) includes silicon nitride (¶0029);
a peripheral circuit contact 970 (“contact plug”- ¶0172) connected to the substrate 500 in the second region II by penetrating a peripheral circuit interlayer insulating layer 770 (“insulating interlayer”- ¶0135) and the peripheral circuit etch stop layer 760 in a vertical direction; and
a peripheral circuit top spacer insulating layer 780 (“capping layer”- ¶0135, analogous to 240) arranged on an upper surface of the peripheral circuit offset layer 730 and including nitride (¶0032),
wherein a side surface of the peripheral circuit offset layer 730 includes a portion that does not overlap with the peripheral circuit top spacer insulating layer 780 in the first horizontal direction.
Park does not expressly disclose the peripheral circuit etch stop layer separated from the peripheral circuit offset layer with a peripheral circuit interlayer insulating layer disposed between the peripheral circuit etch stop layer and the peripheral circuit offset layer.
Thus, regarding independent claim 16 (which claims 17-20 depend from), the prior art of record including Park, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “a peripheral circuit etch stop layer… separated from the peripheral circuit offset layer with a peripheral circuit interlayer insulating layer disposed between the peripheral circuit etch stop layer and the peripheral circuit offset layer”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kim et al. (US 2023/0328960 A1), which discloses a semiconductor device comprising a peripheral circuit gate structure, a peripheral circuit spacer structure, a peripheral circuit etch stop layer and a peripheral circuit contact.
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/JAY C CHANG/Primary Examiner, Art Unit 2817