DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claims 1, 16-17 and 19-20 have been amended; and claims 1-20 are currently pending.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d).
Information Disclosure Statement
The information disclosure statement filed on 5/27/2026 has been acknowledged and a signed copy of the PTO-1449 is attached herein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10, 12-13, 15-16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US 2021/0066304 A1, hereinafter “Kang”) in view of Park et al. (US 2021/0035613 A1, hereinafter “Park”) and Chuang (US 2023/0238276 A1, hereinafter “Chuang”).
In regards to claim 1. Kang discloses (See, for example, Fig. 2) a semiconductor device comprising:
a first line structure (30) and a second line structure (30) extending parallel with each other;
a plurality of spacer structures (41, AG, 44), wherein each of the plurality of spacer structures (41, AG, 44) is disposed on a corresponding side surface of side surfaces of the first (30) and second (30) line structures;
a contact structure (60/51) including a lower portion disposed between the first line structure (30) and the second line structure (30) and an upper portion on the lower portion (a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure, See abstract);
an insulating separation pattern (75) on a side surface of the upper portion of the contact structure (60); and
a protective layer (70) including a first protective portion disposed between the insulating separation pattern (75) and the upper portion of the contact structure (60/51),
wherein the plurality of spacer structures (41, AG, 44) include a first spacer structure (41, AG, 44) on a first side surface of the first line structure (30) and a second spacer structure (41, AG, 44) on a second side surface of the second line structure (30),
wherein the first side surface of the first line structure (30) and the second side surface of the second line structure (30) face each other (the first sidewall of the first bit line structure facing the corresponding sidewall of the second bit line structure across the storage contact region),
wherein at least a portion of the first spacer structure (first inner spacer 41/first outer spacer 44/ first air gap AG disposed between the first bit line structure 30 sidewall and storage contact 51) is disposed between the first side surface of the first line structure (30) and the lower portion of the contact structure (51/60),
wherein at least a portion of the second spacer structure (Second inner spacer 41/second outer spacer 44/ second air gap AG disposed between the second bit line structure 30 sidewall and storage contact 51) is disposed between the second side surface of the second line structure (30) and the lower portion of the contact structure (51/60),
wherein the first spacer structure includes:
an internal spacer (41) contacting the first side surface of the first line structure (30);
an external spacer (44) spaced apart from the first side surface of the first line structure (30); and
an air gap (AG) between the internal spacer (41) and the external spacer (44),
wherein the air gap (AG) is disposed between the first region (41) and the second region (44).
Kang is silent to teach wherein the internal spacer includes a first region having an oxide and the external spacer includes a second region having an oxide.
Park while disclosing a semiconductor device teaches (Fig. 3) the internal spacer includes a first region (141) having an oxide (See, for example, Par [0060]) and the external spacer includes a second region (144) having an oxide (See, for example, Par [0060]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to form the inner spacer and outer spacer of Kang from oxide containing materials of Park because this would help reduce parasitic capacitance between the bit line and storage node contact to minimize operating efficiency degradation.
Kang as modified above does not teach
wherein the internal spacer includes a first region and a third region, the first region having an oxide of a material of the third region,
wherein the external spacer includes a second region and a fourth region, the second region having an oxide of a material of the fourth region, and
wherein the air gap is disposed between the first region and the second region,
wherein the first region is disposed between the air gap and the third region, and wherein the second region is disposed between the air gap and the fourth region.
Chuang while disclosing a semiconductor structure teaches (See, for example, Figs. 21-23)
wherein the internal spacer includes a first region (18/18a, See Par [0098]), and a third region (15, silicon nitride See Par [0067]), the first region (18/18a, See Par [0098]) having an oxide of a material (“ the dielectric layer 18 is naturally formed when the first spacer layer 15 … expose to ambient environment… a native oxide layer”, See Par [0098]) of the third region (15, silicon nitride, See Par [0067]),
wherein the external spacer includes a second region (18b(18)) and a fourth region (17B), the second region (18b(18)) having an oxide (“the dielectric layer 18 is naturally formed when … the second spacer layer 17B expose to ambient environment … the dielectric layer 18 is a native oxide layer,” See Par [0098]) of a material of the fourth region (17B), and
wherein the air gap (AG1) is disposed between the first region (18a (18)) and the second region (18b(18)),
wherein the first region (18a(18)) is disposed between the air gap (AG1) and the third region (15), and wherein the second region (18b(18)) is disposed between the air gap (AG1) and the fourth region (17B).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to provide Chuang’s gap-facing oxide on Kang’s nitride spacers because this would help reduce bit line to storge contact parasitic capacitance.
In regards to claim 16, Kang discloses (See, for example, Fig. 2) a semiconductor device comprising:
a lower structure (See, for example, 10/15);
a line structure (30) disposed on the lower structure and including a conductive pattern (See, for example, contact 31, barrier 33, electrode 55) and an insulating capping pattern (37) on the conductive pattern;
a contact structure (See, for example, 51/60) including a lower portion (51) disposed adjacent to a side surface of the line structure (30) and an upper portion (Se, for example, 60) disposed on the lower portion (51/55) and disposed at a higher level than an upper surface of the line structure (30);
a spacer structure (41/AG/44) between a side surface of the lower portion of the contact structure (51) and the side surface of the line structure (30);
an insulating separation pattern (75) on the spacer structure; and
a protective layer (70) between the upper portion of the contact structure (60) and the insulating separation pattern (75),
wherein the spacer structure includes:
an internal spacer (41);
an external spacer (44); and
an air gap (AG) between the internal spacer (41) and the external spacer (44), and
wherein the insulating separation pattern (75) seals at least a portion of an upper portion of the air gap (See, for example, Abstract).
Park teaches (Fig. 3) wherein regions of the internal spacer (41) and the external spacer (44) exposed by the air gap (AG) include an oxide (See, for example, Par [0060]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to form the inner spacer and outer spacer of Kang from oxide containing materials of Park because this would help reduce parasitic capacitance between the bit line and storage node contact to minimize operating efficiency degradation.
Kang as modified above fails to explicitly teach that wherein each of the internal spacer and external spacer exposed by the air gap includes a first region and a second region, the first region having an oxide of a material of the second region, and wherein the first region is disposed between the air gap and the second region.
Chuang discloses (See, for example, Figs. 21-23) that
wherein each of the internal spacer and the external spacer exposed by the air gap (AG1) includes a first region (18a, 18b) and a second region (15, 17B),
the first region (18a, 18b) having an oxide of (“the dielectric layer 18 is naturally formed when the first spacer layer 15 and the second spacer layer 17B expose to ambient environment. In some embodiments, the dielectric layer 18 is a native oxide layer.” See Par [0098]) a material of the second region (15, 17B), and wherein the first region (18a, 18b) is disposed between the air gap (AG1) and the second region (15, 17B).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to provide Chuang’s gap-facing oxide on Kang’s nitride spacers because this would help reduce bit line to storge contact parasitic capacitance.
In regards to claim 2, Kang as modified above discloses (See, for example, Fig. 2A) that wherein each of the first and second line structures (30) includes a conductive pattern (31/33/35) and an insulating capping pattern (37) on the conductive pattern (31/33/35).
In regards to claim 3, Kang as modified above discloses (See, for example, Fig. 2) that wherein the lower portion of the contact structure (51/60) includes a plug pattern (51/55), wherein the upper portion of the contact structure (51/60) includes a pad pattern (LP) contacting the plug pattern (51), and
wherein a material of the plug pattern (51/55) is different from (See, for example, Pars [0026], and [0052]) a material of the pad pattern (LP).
In regards to claim 4, Kang as modified above discloses (See, for example, Fig. 2A) that wherein the plug pattern (51/55) includes a doped silicon pattern (51, See, Par [0026]) and a metal-semiconductor compound layer (55, See, Par [0027]) on the doped silicon pattern (51), and wherein the pad pattern (60) includes a barrier layer (61) and a pad layer (63) on the barrier layer (61).
In regards to claim 5, Kang as modified above discloses (See, for example, Fig. 2A) that wherein an upper surface of the plug pattern (51/55) is disposed at a higher level than an upper surface of the conductive pattern (35).
In regards to claim 6, Kang as modified above discloses (See, for example, Fig. 2A/2B) an upper surface of the pad pattern (60) is at a higher level than an upper surface of the insulating capping pattern (37), and wherein a lower surface of the pad pattern (60) is at a lower level than the upper surface of the insulating capping pattern (37).
In regards to claim 7, Kang as modified above discloses (See, for example, Fig. 2A) that wherein a portion of the upper portion of the contact structure (51/60) vertically overlaps (See, Fig. 2B) at least a portion of the second line structure (30).
In regards to claim 8, Kang as modified above discloses (See, for example, Fig. 3, Park) wherein at least one of the first region of the internal spacer and the second region of the external spacer includes a SiOCN material (See, for example, Par [0060]).
In regards to claim 10, Kang as modified above discloses (See, for example, Fig. 14, Park) that one of the first and second regions includes a SiOCN material (See, Par [0060]), and wherein the other of the first and second regions includes a SiON material (See, for example, Par [0060]).
In regards to claim 11, Kang as modified above discloses (See, for example, Fig. 3, Park) that wherein the first region of the internal spacer includes a SiOCN material (See, Par [0060]), and wherein the second region of the external spacer includes a SiON material (See, Par [0060]).
In regards to claim 12, Kang as modified above discloses (See, for example, Fig. 2A) an oxide layer (70)between the insulating separation pattern (75) and the upper portion of the contact structure (60), wherein the upper portion of the contact structure (60) includes a first portion contacting the protective layer (71)and a second portion contacting the oxide layer (See, Par [0056] and See also Par [0056], deposition using Si source, Oxygen source, nitrogen source, carbo source and boron source).
In regards to claim 13, Kang as modified above discloses (See, for example, Fig. 11-13B) that wherein the contact structure (51/60) includes a first conductive material (63, tungsten (W), See Par [0052])), and wherein the oxide layer (the conductive material is exposed to oxygen gas as described in Par [0056]) includes an oxide of the first conductive material (the formation of tungsten oxide during the exposure to an oxidizing gas is obvious, and the conductive material would form at the surface as a structural matter).
In regards to claim 15, Kang as modified above discloses (See, for example, Fig. 2A) a data storage structure (80) electrically connected to the contact structure (51/60) and on the contact structure (51/60).
Inn regards to claim 18, Kang as modified above discloses all limitations of claim 16 except that wherein a thickness of the external spacer is greater than a thickness of the internal spacer.
Notwithstanding, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Furthermore, the specification contains no disclosure of either the critical nature of the claimed thickness range or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. See In re Woodruff, 919, f.2d 1575, 1578, 16 USPQ2d, 1936 (Fed. Cir. 1990).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Park and Chuang as applied to claim 1 above, and further in view of Wang et al. (USPN 11437384 B1, hereinafter “Wang”).
In regards to claim 14, Kang as modified above disclose (See, for example, Fig. 2A) the protective layer (70).
However, Kang fails to explicitly teach that the protective layer includes at least one of silicon oxide, SiON, and SiOCN.
Wang while disclosing a semiconductor memory device teaches (See, for example, Fig. 2) the protective layer includes at least one of silicon oxide, SiON, and SiOCN (“In step S203, an etch process, … may be continuously performed until a desired depth of the trench 313 is achieved. … After the etch process, a bottom layer (not shown) may be correspondingly formed and attached to sidewalls and a bottom of the trench 313. The bottom layer may be formed of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide …”, See Col. 5 lines 46-55).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Kang by Wang because having the pad isolation insulating layer provide separation of the adjacent landing pads.
Claims 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Park and Chuang as applied to claim 16 above, and further in view of Ngo et al. (USPN 6521529 B1, hereinafter “Ngo”).
In regards to claim 17, Kang as modified above discloses (See, for example, Figs. 21-23, Chuang) wherein the material of the second region (15, 17B) includes nitride or carbonitride (See, for example, Par [0078]), and wherein the first region (18) is disposed between the air gap (AG1) and the second region (15, 17B).
However, Kang as modified above further fails to explicitly teach wherein the oxide includes oxynitride or oxycarbonitride.
Ngo while disclosing a fabrication of semiconductor device teaches (See, for example, Fig. 4) the oxide includes oxynitride or oxycarbonitride (Silicon nitride sidewall spacer 24, Col. 4 lines 42-45; and a surface layer 40… silicon oxynitride, See Col. 5 lines 48-50).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Kang by Ngo because this would help prevent bridging along the insulating sidewall spacers.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Borsari (US 20180301412 A1, hereinafter “Borsari”) in view of Park, Kang, Chuang and Ngo.
In regards to claim 19, Borsari discloses (See, for example, Figs. 2 and 3) a semiconductor device comprising:
an active region (12);
an isolation region (14) on a side surface of the active region (12);
a gate structure (22/20) within a gate trench (See Par [0020]) intersecting the active region (12) and extending into the isolation region (14);
a first impurity region (24) and a second impurity region (26) disposed within the active region (12) on opposite sides of the gate structure (22) and spaced apart from each other;
first and second line structures (28) extending parallel with each other and disposed at a higher level than the gate structure (22/access line construction 18, See Fig. 6);
a contact structure (54, See Fig. 12) including a plug pattern disposed between the first and second line structures (28) and electrically connected to the first impurity region (24), and
a plurality of spacer structures (46,48, 50) wherein each of the plurality of spacer structures is disposed on a corresponding side surface of side surfaces of the first and second line structures (28, See Fig. 6);
an insulating separation pattern (72, Fig. 11) covering (covering at least a portion of the side surfaces of conductor material 54)at least a portion of a side surface of the pad pattern (54);
a data storage structure (80) on the pad pattern (54),
wherein the first line structure (28) includes a first bit line including a bit line contact portion (36) electrically connected to the second impurity region (26), and a first insulating capping pattern (40) on the first bit line (34/36),
wherein the second line structure (28) includes a second bit line and a second insulating capping pattern (40) on the second bit line (34/36),
wherein the first line structure has a first side surface facing the second line structure (the opposing sides 33/35 of the of the first line structure 28 facing the corresponding sides of the second line structure 28 across the elevationally)-extending conductor material 54; See for example, Par [0021]),
wherein the second line structure has a second side surface facing the first line structure (the corresponding side surface of the second structure 28 facing the first structure 28),
wherein the plurality of spacer structures (46, 48, 50) include a first spacer structure (46, 48, 50) on the first side surface of the first line structure (28) and a second spacer structure (46, 48, 50) on the second side surface of the second line structure (28),
wherein the first spacer structure (46, 48, 50) is disposed between the contact structure (54) and the first line structure (28),
wherein the second spacer structure (46, 48, 50) is disposed between the contact structure (54) and the second line structure (28),
wherein the first spacer structure (46, 48, 50) includes:
a first internal spacer (46);
a first external spacer (50); and
a first air gap (75, See Fig. 13) between the first internal spacer (46) and the first external spacer (50),
wherein the second spacer structure (46, 48, 50) includes:
a second internal spacer (46);
a second external spacer (50); and
a second air gap (75, See Fig. 13) between the second internal spacer (46) and the second external spacer (50),
wherein the first internal spacer (46) is adjacent to or contacting the first side surface of the first line structure (28),
wherein the first external spacer (50) is adjacent to or contacting the contact structure (54),
wherein the second internal spacer (46) is adjacent to or contacting the second side surface of the second line structure (28),
wherein the second external spacer (50) is adjacent to or contacting the contact structure (54),
wherein the first internal spacer (46), the first external spacer (50), the second internal spacer (46), and the second external spacer (50) exposed by the first air gap (75, See, Fig. 13) or the second air gap (75, See, Fig. 13) include an oxide (See, for example, Pars [0022]-[0023]),
wherein the first internal spacer (46) and the first external spacer (50) are exposed by the first air gap (75, See, Fig. 13),
wherein the second internal spacer (46) and the second external spacer (50) are exposed by the second air gap (75, See, Fig. 13),
Borsari fails to explicitly teach
a pad pattern on the plug pattern and electrically connected to the plug pattern;
wherein the plurality of spacer structures further include an upper insulating spacer disposed between the pad pattern and the second insulating capping pattern and defining an upper portion of the second air gap,
Park discloses a pad pattern (133) on the plug pattern (131) and electrically connected to the plug pattern (See, for example, Pars [0066]-[0069], and [0077]; wherein the plurality of spacer structures (140) further include an upper insulating spacer disposed between the pad pattern (133) and the second insulating capping pattern (125) and defining an upper portion of the second air gap (443, See Fig. 14).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Borsari by incorporating the landing-pad geometry of Park because this would help improve cell density and electrical contact reliability between the storage contact and the storage capacitor.
Borsari fails to explicitly teach
a protective layer, wherein at least a portion of the protective layer is disposed between the insulating separation pattern and the pad pattern;
wherein the insulating separation pattern seals an upper portion of the first air gap,
wherein the pad pattern includes a portion vertically overlapping the second insulating capping pattern and disposed on the second insulating capping pattern.
Kang discloses (See, for example, fig. 2A) a protective layer (70, wherein at least a portion of the protective layer (70) is disposed between the insulating separation pattern (75) and the pad pattern (60); wherein the insulating separation pattern (70) seals an upper portion of the first air gap (AG), wherein the pad pattern (133, as it is higher than the upper surface of the bit line structure 120) includes a portion vertically overlapping the second insulating capping pattern (125) and disposed on the second insulating capping pattern (125).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to apply Kang’s sealing-layer geometry to Borsari as modified above because this would reliably seal the top of the air gap during subsequent processing and provide an additional barrier protecting the contact pad from process damage.
Borsari further fails to explicitly teach that
wherein at least one of the first internal spacer, the first external spacer, the second internal spacer, and the second external spacer includes a first region and a second region,
wherein a material of the second region includes nitride or carbonitride,
wherein the first region includes an oxide of the material of the second region, and
wherein the oxide of the first region includes oxynitride or oxycarbonitride.
Chuang discloses (See, for example, Figs. 21-23) wherein at least one of the first internal spacer (15, left side of bit line 13), the first external spacer (17B, left side of the bit line 13), the second internal spacer (15, right side of bit line 13), and the second external spacer (17B, right side of the bit line 13) includes a first region (18) and a second region (15, 17B),
wherein a material of the second region (15, 17B) includes nitride or carbonitride ( “the third spacer layer 19 includes a dielectric material same as the second spacer layer 17B or the first spacer layer 15. In some embodiments, the third spacer layer 19 is a nitride layer. In some embodiments, the third spacer layer 19 includes silicon nitride.”, See Par [0078])
wherein the first region (18) includes an oxide (“he dielectric layer 18 is naturally formed when the first spacer layer 15 and the second spacer layer 17B expose to ambient environment. In some embodiments, the dielectric layer 18 is a native oxide layer.”, See Par [0098]) of the material of the second region (15, 17B).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to provide Chuang’s gap-facing oxide on Kang’s nitride spacers because this would help reduce bit line to storge contact parasitic capacitance.
However, Borsari as modified above fails to explicitly teach that wherein the oxide of the first region includes oxynitride or oxycarbonitride.
Ngo teaches (See, for example, Fig. 4) the oxide includes oxynitride or oxycarbonitride (Silicon nitride sidewall spacer 24, Col. 4 lines 42-45; and a surface layer 40… silicon oxynitride, See Col. 5 lines 48-50).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Kang by Ngo because this would help prevent bridging along the insulating sidewall spacers.
In regards to claim 20, Borsari as modified above discloses (See, for example, Figs. 21-2, Chuang) wherein the first region (18) is disposed between the first air gap (AG1) or the second air gap (AG1) and the second region (15, 17B).
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim 8, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1, 16, 17, 19 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893
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