DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 16 is objected to because of the following informalities: in line 5, replace “the vias electrode” with --the via electrodes-- for consistency with the limitation in lines 2-3. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, and 4-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang et al (US Patent Application Publication 2022/0045008).
Regarding claim 1, Kang et al disclose a semiconductor package comprising:
a package substrate 100 comprising a glass core substrate 110, a semiconductor bridge interposer 120, and a multi-layer wiring layer 140 disposed under the glass core substrate and the semiconductor bridge interposer [see Fig. 1; see also paragraphs 0018 and 0019]; and
at least two semiconductor devices 200, 300 stacked on the package substrate,
wherein a cavity CA is formed in a central portion of the glass core substrate, and the semiconductor bridge interposer is embedded in the cavity [see Fig. 1; see also paragraph 0031].
Regarding claim 2, Kang et al disclose the semiconductor package of claim 1, furthermore wherein the glass core substrate comprises a glass body having formed therein the cavity, via electrodes 116 penetrating through the glass body, and upper pads 115 and lower pads 117 respectively on a top surface and a bottom surface of the glass body [see Fig. 1; see also paragraph 0019], and
the via electrodes respectively connect the upper pads and the lower pads to each other.
Regarding claim 4, Kang et al disclose the semiconductor package of claim 2, furthermore wherein the glass core substrate further comprises a protective layer 142, 132 surrounding an outer surface of the glass body [see Fig. 1; see also paragraph 0033], and
each upper pad and respective lower pad are connected to a respective via electrode through a respective via penetrating through the protective layer [see Fig. 1].
Regarding claim 5, Kang et al disclose the semiconductor package of claim 4, furthermore wherein a vertical cross-section of each via has a trapezoidal structure in which a portion connected to the via electrode is relatively narrow and a portion connected to the respective upper pad or the lower pad is relatively wide [see Fig. 1].
Regarding claim 6, Kang et al disclose the semiconductor package of claim 4, furthermore wherein a horizontal cross-section of each via is larger than a horizontal cross-section of each via electrode [see Fig. 1], and
at a junction between each via and each respective via electrode, a horizontal distance between an end of the via and an end of the via electrode is from about 5 µm to about 30 µm [see paragraphs 0019 and 0023, wherein the horizontal distance would fall in the claimed range].
Regarding claim 7, Kang et al disclose the semiconductor package of claim 4, furthermore wherein the glass core substrate further comprises a seed layer disposed between each via electrode and each respective via [see Fig. 2, wherein a seed layer 128 is disposed between the electrode 127 and the via 126; see also paragraph 0026].
Regarding claim 8, Kang et al disclose the semiconductor package of claim 4, furthermore wherein the protective layer 142, 132 is entirely formed of the same material or at least a portion thereof is formed of a different material, and a distinct interface is formed in at least a portion of the protective layer [see Fig. 1].
Regarding claim 9, Kang et al disclose the semiconductor package of claim 1, furthermore wherein the semiconductor bridge interposer connects the at least two semiconductor devices to each other [see Fig. 1], and
each of the at least two semiconductor devices comprises a logic chip or a memory chip [see paragraph 0035].
Regarding claim 10, Kang et al disclose the semiconductor package of claim 9, furthermore wherein any one of the at least two semiconductor devices has a package structure comprising a plurality of memory chips [see paragraph 0035].
Regarding claim 11, Kang et al disclose the semiconductor package of claim 1, furthermore wherein the at least two semiconductor devices are stacked on the package substrate in a single package structure or each of the at least two semiconductor devices is stacked on the package substrate as a separate structure [see Fig. 1].
Regarding claim 12, Kang et al disclose the semiconductor package of claim 1, furthermore wherein the glass core substrate is disposed in an asymmetrical structure in a vertical direction within the package substrate [see Fig. 1].
Regarding claim 13, Kang et al disclose a semiconductor package comprising:
a package substrate comprising a glass core substrate 110 and a multi-layer wiring layer 140 disposed on at least one of a bottom surface and a top surface of the glass core substrate [see Fig. 1; see also paragraphs 0018 and 0019];
a semiconductor interposer 120 disposed on the package substrate; and
at least two semiconductor devices 200, 300 arranged on the semiconductor interposer [see Fig. 1].
Regarding claim 14, Kang et al disclose the semiconductor package of claim 13, furthermore wherein a cavity CA is formed in a central portion of the glass core substrate, and
the semiconductor package further comprises a passive device disposed in the cavity [see paragraph 0030].
Regarding claim 15, Kang et al disclose the semiconductor package of claim 13, furthermore wherein the glass core substrate is disposed in a central portion of the package substrate in a vertical direction [see Fig. 1], and
the package substrate comprises an upper multi-layer wiring layer 130 disposed on the top surface of the glass core substrate and a lower multi-layer wiring layer 140 disclosed on the bottom surface of the glass core substrate.
Regarding claim 16, Kang et al disclose the semiconductor package of claim 13, furthermore wherein the glass core substrate comprises a glass body 110, in which a cavity CA is formed in a central portion, via electrodes 116 penetrating through the glass body, and upper pads 115 and lower pads 117 respectively on a top surface and a bottom surface of the glass body, and
the via electrodes connect the upper pads and the lower pads to each other [see Fig. 1].
Regarding claim 17, Kang et al disclose the semiconductor package of claim 16, furthermore wherein the glass core substrate further comprises a protective layer 142, 132 surrounding an outer surface of the glass body, and
the upper pads and the lower pads are connected to the via electrodes through respective vias penetrating through the protective layer [see Fig. 1].
Regarding claim 18, Kang et al disclose the semiconductor package of claim 17, furthermore wherein a horizontal cross-section of each via is larger than a horizontal cross-section of each via electrode,
a vertical cross-section of each via has a trapezoidal structure in which a portion connected to a respective via electrode is narrow and a portion connected to a respective upper pad or lower pad is wide [see Fig. 1].
Regarding claim 19, Kang et al disclose the semiconductor package of claim 17, furthermore wherein the semiconductor interposer connects the at least two semiconductor devices to each other, and
each of the at least two semiconductor devices comprises a logic chip or a memory chip [see paragraph 0035].
Regarding claim 20, Kang et al disclose a semiconductor package comprising:
a package substrate comprising a glass core substrate 110 and a multi-layer wiring layer 140 disposed on at least one of a bottom surface and a top surface of the glass core substrate [see Fig. 1; see also paragraphs 0018-0019[;
a semiconductor interposer 120 disposed within the package substrate or disposed on a top surface of the package substrate; and
at least two semiconductor devices 200, 300 arranged on the package substrate or the semiconductor interposer,
wherein:
a cavity CA is formed in a central portion of the glass core substrate,
when the semiconductor interposer is disposed within the package substrate, the semiconductor interposer is disposed in the cavity [see Fig. 1], and
when the semiconductor interposer is disposed on the top surface of the package substrate, a passive device is disposed in the cavity.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kang et al (US Patent Application Publication 2022/0045008) in view of Lu (US Patent Application Publication 2021/0202395).
Regarding claim 3, Kang et al disclose the semiconductor package of claim 2. Kang et al are silent as to the materials used for the via electrode, and thus do not disclose wherein each via electrode comprises a metal electrode layer extending between a respective upper pad and a respective lower pad and an adhesive layer surrounding the metal electrode layer. One such as Lu discloses a via electrode 22, wherein each via electrode comprises a metal electrode layer 222 extending between a respective upper pad and a respective lower pad and an adhesive layer 221 surrounding the metal electrode layer. It would have been obvious to one of ordinary skill in the art at the time of invention to form the via electrodes of Kang et al from the materials of Lu because Lu discloses wherein these materials are known in the art for the purpose. It has been held that simple substitution of one known material for another to obtain predictable results is obvious. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). See MPEP 2143.
Conclusion
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/C.E.S./Examiner, Art Unit 2899 /VICTOR A MANDALA/
Primary Examiner, Art Unit 2899
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