DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action responds to the Amendment filed 4 August 2026. By this amendment, claims 1-4, 6, 9 and 13-20 are amended.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 5 and 7-20 are rejected under 35 U.S.C. 103 as being unpatentable over Paital et al (US Patent Application Publication 2023/0085411) in view of Sankman et al (US Patent Application Publication 2021/0305108).
Regarding claim 1, Paital et al disclose a semiconductor package comprising:
a package substrate 102 comprising a glass core substrate 104, a semiconductor bridge interposer 108, and a multi-layer wiring layer 122, 124 disposed under the glass core substrate and the semiconductor bridge interposer [see Fig. 1; see also paragraphs 0068-0071]; and
at least two semiconductor devices 112, 114 stacked on the package substrate,
wherein a cavity 106 is formed in a central portion of the glass core substrate, and the semiconductor bridge interposer is embedded in the cavity [see Fig. 1],
wherein the multi-layer wiring layer comprises an insulating body 122, wiring lines and vertical vias 124,
wherein a bottom surface of the glass core substrate is surrounded by the insulating body.
Paital et al do not disclose wherein the side surfaces of the glass core substrate are surrounded by the insulating body. One such as Sankman et al disclose a package substrate comprising a glass core substrate 72, wherein a bottom surface and side surfaces of the glass core substrate are surrounded by the insulating body 80 [see Fig. 2; see also paragraphs 0018 and 0067]. It would have been obvious to one of ordinary skill in the art at the time of invention to form the dielectric body to surround the side surfaces of the glass core substrate of Paital et al, as taught by Sankman et al, in order to encapsulate and mechanically support the glass core substrate while permitting formation of the package redistribution/build-up structure around the core.
Regarding claim 2, the prior art of Paital et al and Sankman et al disclose the semiconductor package of claim 1. Furthermore, Paital et al disclose wherein:
the glass core substrate comprises a glass body having formed therein the cavity, via electrodes 118 penetrating through the glass body, and upper pads and lower pads respectively on a top surface and a bottom surface of the glass body [see Fig. 1], and
the via electrodes respectively connect the upper pads and the lower pads to each other [see Fig. 1].
Regarding claim 4, the prior art of Paital et al and Sankman et al disclose the semiconductor package of claim 2. Furthermore to the side surfaces of the glass core substrate, Sankman et al disclose wherein:
the glass core substrate further comprises a protective layer 80 surrounding an outer surface of the glass body, and
each upper pad and respective lower pad are connected to a respective via electrode through a respective via penetrating through the protective layer [see Fig. 2].
Regarding claim 5, the prior art of Paital et al and Sankman et al disclose the semiconductor package of claim 4. Furthermore, Paital et al disclose wherein a vertical cross-section of each via has a trapezoidal structure in which a portion connected to the via electrode is relatively narrow and a portion connected to the respective upper pad or the lower pad is relatively wide [see Fig. 1].
Regarding claim 7, the prior art of Paital et al and Sankman et al disclose the semiconductor package of claim 4. Furthermore, Paital et al disclose wherein the glass core substrate further comprises a seed layer disposed between each via electrode and each respective via [see paragraph 0086].
Regarding claim 8, the prior art of Paital et al and Sankman et al disclose the semiconductor package of claim 4. Furthermore to the protective layer, Sankman et al disclose wherein the protective layer is entirely formed of the same material or at least a portion thereof is formed of a different material, and a distinct interface is formed in at least a portion of the protective layer [see Fig. 2; see also paragraph 0068].
Regarding claim 9, the prior art of Paital et al and Sankman et al disclose the semiconductor package of claim 1. Furthermore, Paital et al disclose wherein:
the semiconductor bridge interposer connects the at least two semiconductor devices to each other, and
each of the at least two semiconductor devices comprises a logic chip or a memory chip [see Fig. 1; see also paragraph 0069].
Regarding claim 10, the prior art of Paital et al and Sankman et al disclose the semiconductor package of claim 9. Furthermore, Paital et al disclose wherein any one of the at least two semiconductor devices has a package structure comprising a plurality of memory chips [see paragraph 0069].
Regarding claim 11, the prior art of Paital et al and Sankman et al disclose the semiconductor package of claim 1. Furthermore, Paital et al disclose wherein the at least two semiconductor devices are stacked on the package substrate in a single package structure or each of the at least two semiconductor devices is stacked on the package substrate as a separate structure [see Fig. 1].
Regarding claim 12, the prior art of Paital et al and Sankman et al disclose the semiconductor package of claim 1. Furthermore, Paital et al disclose wherein the glass core substrate is disposed in an asymmetrical structure in a vertical direction within the package substrate [see Fig. 1].
Regarding claim 13, Paital et al disclose a semiconductor package comprising:
a package substrate 102 comprising a glass core substrate 104 and a multi-layer wiring layer 122, 124 disposed on at least one of a bottom surface and a top surface of the glass core substrate [see Fig. 1; see also paragraphs 0068-0071];
a semiconductor interposer 108 disposed on the package substrate; and
at least two semiconductor devices 112, 114 arranged on the semiconductor interposer,
wherein the multi-layer wiring layer comprises an insulating body 122, wiring lines and vertical vias 124,
wherein a bottom surface of the glass core substrate is surrounded by the insulating body.
Paital et al do not disclose wherein the side surfaces of the glass core substrate are surrounded by the insulating body. One such as Sankman et al disclose a package substrate comprising a glass core substrate 72, wherein a bottom surface and side surfaces of the glass core substrate are surrounded by the insulating body 80 [see Fig. 2; see also paragraphs 0018 and 0067]. It would have been obvious to one of ordinary skill in the art at the time of invention to form the dielectric body to surround the side surfaces of the glass core substrate of Paital et al, as taught by Sankman et al, in order to encapsulate and mechanically support the glass core substrate while permitting formation of the package redistribution/build-up structure around the core.
Regarding claim 14, the prior art of Paital et al and Sankman et al disclose the semiconductor package of claim 13. Furthermore, Paital et al disclose wherein:
a cavity 106 is formed in a central portion of the glass core substrate, and
the semiconductor package further comprises a passive device 108 disposed in the cavity.
Regarding claim 15, the prior art of Paital et al and Sankman et al disclose the semiconductor package of claim 13. Furthermore, Paital et al disclose wherein:
the glass core substrate is disposed in a central portion of the package substrate in a vertical direction, and
the package substrate comprises an upper multi-layer wiring layer disposed on the top surface of the glass core substrate and a lower multi-layer wiring layer disposed on the bottom surface of the glass core substrate [see Fig. 1].
Regarding claim 16, the prior art of Paital et al and Sankman et al disclose the semiconductor package of claim 13. Furthermore, Paital et al disclose wherein the glass core substrate comprises a glass body, in which a cavity is formed in a central portion, via electrodes penetrating through the glass body, and upper pads and lower pads respectively on a top surface and a bottom surface of the glass body [see Fig. 1], and
the via electrodes connect the upper pads to the lower pads.
Regarding claim 17, the prior art of Paital et al and Sankman et al disclose the semiconductor package of claim 16. Furthermore to the side surfaces of the glass core substrate, Sankman et al disclose wherein:
the glass core substrate further comprises a protective layer 80 surrounding an outer surface of the glass body, and
the upper pads and the lower pad are connected to the via electrodes through respective vias penetrating through the protective layer [see Fig. 2].
Regarding claim 18, the prior art of Paital et al and Sankman et al disclose the semiconductor package of claim 17. Furthermore, Paital et al disclose wherein:
a horizontal cross-section of each via is larger than a horizontal cross-section of each via electrode,
a vertical cross-section of each via has a trapezoidal structure in which a portion connected to a respective via electrode is narrow and a portion connected to a respective upper pad or lower pad is wide [see Fig. 1].
Regarding claim 19, the prior art of Paital et al and Sankman et al disclose the semiconductor package of claim 17. Furthermore, Paital et al disclose wherein:
the semiconductor interposer connects the at least two semiconductor devices to each other, and
each of the at least two semiconductor devices comprises a logic chip or a memory chip [see Fig. 1; see also paragraph 0069].
Regarding claim 20, Paital et al disclose a semiconductor package comprising:
a package substrate 102 comprising a glass core substrate 104 and a multi-layer wiring layer 122, 124 disposed on at least one of a bottom surface and a top surface of the glass core substrate [see Fig. 1; see also paragraphs 0068-0071];
a semiconductor interposer 108 disposed within the package substrate or disposed on a top surface of the package substrate; and
at least two semiconductor devices 112, 114 arranged on the package substrate or the semiconductor interposer,
wherein:
a cavity 106 is formed in a central portion of the glass core substrate,
when the semiconductor interposer is disposed within the package substrate, the semiconductor interposer is disposed in the cavity,
when the semiconductor interposer is disposed on the top surface of the package substrate, a passive device is disposed in the cavity,
the multi-layer wiring layer comprises an insulating body 122, wiring lines and vertical vias 124,
wherein a bottom surface of the glass core substrate is surrounded by the insulating body.
Paital et al do not disclose wherein the side surfaces of the glass core substrate are surrounded by the insulating body. One such as Sankman et al disclose a package substrate comprising a glass core substrate 72, wherein a bottom surface and side surfaces of the glass core substrate are surrounded by the insulating body 80 [see Fig. 2; see also paragraphs 0018 and 0067]. It would have been obvious to one of ordinary skill in the art at the time of invention to form the dielectric body to surround the side surfaces of the glass core substrate of Paital et al, as taught by Sankman et al, in order to encapsulate and mechanically support the glass core substrate while permitting formation of the package redistribution/build-up structure around the core.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Paital et al (US Patent Application Publication 2023/0085411) in view of Sankman et al (US Patent Application Publication 2021/0305108) as applied to claim 1 above, and further in view of Park et al (US Patent Application Publication 2021/0167001).
Regarding claim 3, the prior art of Paital et al and Sankman et al disclose the semiconductor package of claim 2. Neither Paital et al nor Sankman et al disclose specifically wherein each via electrode comprises a metal electrode layer extending between a respective upper pad and a respective lower pad and an insulating adhesive layer surrounding the metal electrode layer. One such as Park et al disclose a stacked chip structure, as that of Paital et al, wherein there is a metal electrode layer 240 extending between a respective upper pad and a respective lower pad, and furthermore disclose an insulating adhesive layer 350 surrounding the metal electrode layer [see Fig. 5A; see also paragraph 0090]. It would have been obvious to one of ordinary skill in the art at the time of invention to include the insulating adhesive of Park et al in the semiconductor package of Paital et al, as modified by Sankman et al, in order to electrically insulate and physically secure the vertical conductive interconnect while simultaneously bonding adjacent package structures.
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: regarding dependent claim 6, the prior art of record fails to teach or make reasonably obvious, in combination with the other claimed elements and with sufficient specificity, wherein a horizontal distance between an end of the via and an end of the via electrode is from about 5 µm to about 30 µm.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.E.S./Examiner, Art Unit 2899 /VICTOR A MANDALA/Primary Examiner, Art Unit 2899
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