DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 12/21/2023, 12/26/2023, 01/23/2025, 01/27/2025, and 09/16/2025 have been considered.
Drawings
The drawings filed on 03/27/2024 are acceptable.
Specification
The abstract of the disclosure and the specification filed on 12/21/2023 are acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 22 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Lilak (US 2022/0115372).
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Regarding claim 1, Lilak (US 2022/0115372) discloses:
A semiconductor structure, comprising:
a first transistor (110, ¶0040); and
a second transistor (130, ¶0040) vertically stacked over the first transistor;
wherein the first transistor and the second transistor have horizontally aligned cell boundaries (¶0045 discloses cell boundaries 143 and 123 have the same distance D4 and D3); and
wherein a first set of one or more channels (111, ¶0041) of the first transistor (110) are horizontally offset from a second set of one or more channels (131, ¶0042) of the second transistor (130) within the horizontally aligned cell boundaries (L1 and L3 have different values, ¶0043).
Regarding claim 22, Lilak discloses:
An integrated circuit comprising: a semiconductor structure comprising:
a first transistor (110); and
a second transistor (130) vertically stacked over the first transistor (110);
wherein the first transistor and the second transistor have horizontally aligned cell boundaries (¶0045 discloses cell boundaries 143 and 123 have the same distance D4 and D3); and
wherein a first set of one or more channels (111) of the first transistor are horizontally offset from a second set of one or more channels (131) of the second transistor within the horizontally aligned cell boundaries (L1 and L3 have different values, ¶0043).
Claim(s) 1, 2, 4, 6, 22, 23 and 25 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Goktepeli (US 2018/0061766).
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Regarding claim 1, Goktepeli discloses:
A semiconductor structure, comprising:
a first transistor (714, ¶0088); and
a second transistor (712, ¶0088) vertically stacked over the first transistor;
wherein the first transistor and the second transistor have horizontally aligned cell boundaries (figure 7a); and
wherein a first set of one or more channels of the first transistor (714) are horizontally offset from a second set of one or more channels of the second transistor (130) within the horizontally aligned cell boundaries (¶0091, figure 7a).
Regarding claim 2, Goktepeli further discloses:
the first set of one or more channels of the first transistor (714) have a first distance to the horizontally aligned cell boundaries at a first lateral side of the semiconductor structure and a second distance to the horizontally aligned cell boundaries at a second lateral side of the semiconductor structure opposite the first lateral side of the semiconductor structure, the first distance being greater than the second distance (figure 7a); and
the second set of one or more channels of the second transistor (712) have a third distance to the horizontally aligned cell boundaries at the first lateral side of the semiconductor structure and a fourth distance to the horizontally aligned cell boundaries at the second lateral side of the semiconductor structure opposite the first lateral side of the semiconductor structure, the third distance being less than the fourth distance (figure 7a).
Regarding claim 4, Goktepeli further discloses:
wherein the first transistor (714) is proximate a backside of the semiconductor structure and the second transistor (712) is proximate a frontside of the semiconductor structure, and further comprising at least one contact (730, ¶0092) extending from a backside power delivery network of the semiconductor structure to at least one semiconductor terminal (726, ¶0092) of at least one of the second transistor (712), the at least one contact being underneath at least a portion of the at least one semiconductor terminal, the portion of the at least one semiconductor terminal being laterally adjacent to the second set of one or more channels (figure 7a).
Regarding claim 6, Goktepeli further discloses:
at least one contact (730) to at least one of the first transistor (714) and the second transistor (712) which is within the horizontally aligned cell boundaries.
Regarding claim 22, Goktepeli discloses:
An integrated circuit comprising:
a semiconductor structure comprising:
a first transistor (714); and
a second transistor (712) vertically stacked over the first transistor;
wherein the first transistor (714) and the second transistor (712) have horizontally aligned cell boundaries; and
wherein a first set of one or more channels of the first transistor (714) are horizontally offset from a second set of one or more channels of the second transistor (712) within the horizontally aligned cell boundaries (figure 7a).
Regarding claim 23, Goktepeli further discloses:
the first set of one or more channels of the first transistor have a first distance to the horizontally aligned cell boundaries at a first lateral side of the semiconductor structure and a second distance to the horizontally aligned cell boundaries at a second lateral side of the semiconductor structure opposite the first lateral side of the semiconductor structure, the first distance being greater than the second distance; and the second set of one or more channels of the second transistor have a third distance to the horizontally aligned cell boundaries at the first lateral side of the semiconductor structure and a fourth distance to the horizontally aligned cell boundaries at the second lateral side of the semiconductor structure opposite the first lateral side of the semiconductor structure, the third distance being less than the fourth distance (figure 7a).
Regarding claim 25, Goktepeli further discloses:
wherein the semiconductor structure further comprises at least one contact (730) to at least one of the first transistor (714) and the second transistor (712) which is within the horizontally aligned cell boundaries.
Allowable Subject Matter
Claims 8-21 are allowed.
Regarding claim 8, the prior art does not disclose “a second stacked transistor cell comprising a third transistor and a fourth transistor vertically stacked over the third transistor, wherein a third set of one or more channels of the third transistor are horizontally offset from a fourth set of one or more channels of the fourth transistor within cell boundaries of the second stacked transistor cell; wherein the second stacked transistor cell is laterally adjacent to the first stacked transistor cell” in combination with the remaining claimed features.
Regarding claim 14, the prior art does not disclose “wherein a first set of one or more channels of the first transistor are laterally closer to the first dielectric spacer than the second dielectric spacer; and wherein a second set of one or more channels of the second transistor are laterally closer to the second dielectric spacer than the first dielectric spacer” in combination with the remaining claimed features.
Regarding claim 18, the prior art does not disclose “wherein a first set of one or more channels of the first transistor have a first lateral distance to the dielectric wall and a second set of one or more channels of the second transistor have a second lateral distance to the dielectric wall, the first lateral distance being different than the second lateral distance; and wherein a third set of one or more channels of the third transistor have a third lateral distance to the dielectric wall and a fourth set of one or more channels of the fourth transistor have a fourth lateral distance to the dielectric wall, the third lateral distance being different than the fourth lateral distance” in combination with the remaining claimed features.
Claims 3, 5, 7 and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, the prior art does not disclose “a gate merge contact between a first gate region of the first transistor and a second gate region of the second transistor, wherein the gate merge contact is disposed within the horizontally aligned cell boundaries on a first side of the second set of channels and over a portion of the first set of channels” in combination with the remaining claimed features.
Regarding claim 5, the prior art does not disclose “a contact which connects to a semiconductor terminal of the first transistor at the backside of the semiconductor structure, the contact having a first portion with a first width proximate a bottom surface of the semiconductor terminal of the first transistor and a second portion with a second width proximate a backside of the first portion, the first width being greater than the second width” in combination with the remaining claimed features.
Regarding claim 7, the prior art does not disclose “a first power rail which connects to a first semiconductor terminal of one of the first transistor and the second transistor and a second power rail which connects to a second semiconductor terminal of one of the first transistor and the second transistor, wherein the first power rail has a different width than the second power rail” in combination with the remaining claimed features.
Regarding claim 24, the prior art does not disclose “wherein the semiconductor structure further comprises a gate merge contact between a first gate region of the first transistor and a second gate region of the second transistor, wherein the gate merge contact is disposed within the horizontally aligned cell boundaries on a first side of the second set of channels and over a portion of the first set of channels” in combination with the remain claimed features.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is (571)270-3897. The examiner can normally be reached Mon-Fri, 9AM-5PM.
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/WILLIAM A HARRISTON/ Primary Examiner, Art Unit 2899