Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Applicant’s response of 10/13/2026 has been entered in the record and considered. With respect to the rejection claims 35 USC 102 (a)(1) and 35 USC 103 (a) are withdrawn in view of applicants’ amendments. With respect to the rejection claims 35 USC 112 (b) is withdrawn in view of applicants’ amendments. Claims 1, 3-11 and 13-20 are under consideration. The following new rejection to claims 1, 3-4, 9-11, 13-14 and 17-20 is under 35 USC 103 (a). Claims 5-8 and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 2 and 12 are cancelled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2020/0235026 to Kurokawa et al. (Kurokawa 026’) in view of US Pub # 2021/0407937 to Kurata.
Regarding independent claim 1, Kurokawa 026” discloses a semiconductor device (Fig. 1) comprising:
an emitter junction wiring (E1, Fig. 1, ¶0032);
a metal pillar (E2, Fig. 1, ¶0034); and
a plurality of unit transistors (Fig. 1: 60), each of which is disposed on a semiconductor substrate (30), each of the plurality of unit transistors (60) comprising:
a collector electrode (C0) configured to output an output signal (Fig. 1, ¶0027);
a base electrode (B0) configured to receive an input signal (Fig. 1, ¶0028); and
an emitter electrode (E0) (Fig. 1, ¶0028);
wherein the emitter junction wiring (E1) is configured to interconnect the emitter electrodes of the plurality of unit transistors (E1 electrically connected through E2, Fig. 1, ¶0032-0034);
wherein the metal pillar (E2 and ¶0034, Under the broadest reasonable interpretation consistent with the specification, the Examiner construes disclosed a second-layer emitter wiring as the claimed a metal pillar) is disposed to form an interface with the emitter junction wiring (E1) and is disposed to be in contact with the emitter junction wiring (E2 contacting E1 through cavities 54E, Fig. 1, ¶0034).
Kurokawa 026’ does not expressly disclose wherein the metal pillar comprises a plurality of slits, each of which comprises a cavity, the plurality of slits being disposed adjacent to the emitter junction wiring and interfacing the emitter junction wiring and the metal pillar.
However, Kurata teaches a metal pillar (metal post electrode 70) comprising a plurality of slits (Figs. 7-9: recesses 74; The Examiner interprets the recesses (74) of Kurata as corresponding to the claimed slits because the recesses extend inwardly from the surface of the metal pillar (70), thereby forming recessed openings in the metal pillar), each of which comprises a cavity (internal spaces 77 and 80), and a slit disposed adjacent to and interfacing a wiring and the metal pillar (recess 81 at the interface between rewiring layer 33 and metal post electrode 70, Figs. 7-9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the metal pillar (E2) of Kurokawa to include a plurality of slits, each comprising a cavity, in order to improve adhesion between the metal pillar and surrounding resin material and prevent separation, as taught by Kurata (¶0191 and 0194).
Regarding claim 3, Kurokawa 026” discloses the semiconductor device of claim 1, as discussed above.
Kurokawa 026’ does not expressly disclose wherein the plurality of slits are disposed apart from each other at preset intervals.
However, Kurata teaches wherein the plurality of slits (electrode recesses 74) are disposed apart from each other (plurality of electrode recesses 74 formed at separate positions along the electrode lateral surface 73 of post electrode 70, Figs. 7 and 9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the metal pillar (E2) of Kurokawa such that the plurality of slits are disposed apart from each other at preset intervals, as suggested by Kurata, in order to provide a plurality of recessed surface portions for improving adhesion between the metal pillar and surrounding resin material and preventing separation, as taught by Kurata (¶0191 and 0194).
Regarding claim 9, Kurokawa 026” discloses wherein each of the plurality of unit transistors (60) is a bipolar transistor (¶0026) that comprises:
a collector layer (Fig. 1: 31 or 32 and ¶0027) disposed in an area where the collector electrode (C0) is disposed,
a base layer (Fig. 1: 33 and ¶0027) disposed in an area where the base electrode (B0) is disposed, and
an emitter layer (Fig. 1: 34 and ¶0027) disposed in an area where the emitter electrode (E0) is disposed.
Regarding claim 10, Kurokawa 026” discloses wherein the emitter junction wiring (E1) comprises a gold (Au) material (¶0032).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2020/0235026 to Kurokawa et al. (Kurokawa 026’) in view of US Pub # 2021/0407937 to Kurata and further in view of US Pub # 2020/0258980 to Carlson.
Regarding claim 4, Kurokawa 026” discloses the semiconductor device of claim 1, as discussed above (Fig. 1, ¶0025-0034).
Kurokawa 026’ does not expressly disclose wherein air is filled within the plurality of slits to form an air layer.
Kurata teaches a metal pillar (post electrode 70) comprising a plurality of slits (electrode recesses 74), each of which comprises a cavity (internal spaces 77 and 80, Figs. 7-9), as discussed in the rejection of claim 1.
However, Kurokawa 026’ in view of Kurata does not expressly disclose wherein air is filled within the plurality of slits to form an air layer.
Carlson teaches a conductive pillar (255) comprising a hollow or empty portion (center region 258), wherein the hollow or empty portion is surrounded by a conductive channel (280M), thereby maintaining an electrically conductive path through the conductive pillar (Fig. 2D).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the plurality of slits (recesses 74) of Kurata, as applied to the metal pillar (E2) of Kurokawa, to retain air within the plurality of slits to form an air layer, in view of Carlson’s teaching of a hollow or empty portion (258) within a conductive pillar (255), in order to provide an internal empty region while maintaining an electrically conductive path through the metal pillar, as taught by Carlson (Fig. 2D and ¶0058-0059, 0079).
Claims 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2019/0172773 to Kurokawa et al. (Kurokawa 773’) in view of US Pub # 2021/0407937 to Kurata.
Regarding independent claim 11, Kurokawa 773” discloses a power amplifier that amplifies a radio frequency (RF) input signal and outputs an RF output signal (Fig. 7, ¶0112-0117), the power amplifier comprising:
an emitter junction wiring (first-layer emitter wiring E1, Fig. 2, ¶0054);
a metal pillar (second-layer emitter wiring E2, Fig. 2, ¶0054 Under the broadest reasonable interpretation consistent with the specification, the Examiner construes disclosed a second-layer emitter wiring as the claimed a metal pillar); and
a plurality of unit transistors (Fig. 2: 60), each of which is disposed on a semiconductor substrate (30, Figs. 1 and 2), and each of the plurality of unit transistors (60) comprises:
a collector electrode configured to output an output signal (collector electrode C0, Fig. 2, ¶0051);
a base electrode configured to receive an input signal (base electrode B0, Fig. 2, ¶0051); and
an emitter electrode (emitter electrode E0, Fig. 2, ¶0051);
wherein the emitter junction wiring (E1) is configured to interconnect the emitter electrodes of the plurality of unit transistors (first-layer emitter wiring E1 electrically connected to emitter electrodes E0 and first-layer emitter wirings E1 electrically interconnected through second-layer emitter wiring E2, Figs. 1-3, ¶0054-0055);
wherein the metal pillar (E2) is disposed to form an interface with the emitter junction wiring (E1), and is disposed to be in contact with the emitter junction wiring (second-layer emitter wiring E2 connected to first-layer emitter wiring E1 through a cavity formed in second-layer insulating film 51, Fig. 2, ¶0054); and
a circuit board on which the plurality of unit transistors are mounted (mounting substrate 90 on which semiconductor chip 70 comprising the plurality of unit transistors 60 is mounted, Fig. 11, ¶0141; Under the broadest reasonable interpretation, the Examiner interprets mounting substrate (90) as the claimed circuit board because it includes conductive wiring for electrical interconnections and supports semiconductor chip (70), ¶0114, 0123, and 0141).
Kurokawa 773’ does not expressly disclose wherein the metal pillar comprises a plurality of slits each of which comprises a cavity, the plurality of slits being disposed adjacent to the emitter junction wiring and interfacing the emitter junction wiring and the metal pillar.
However, Kurata teaches a metal pillar (post electrode 70) comprising a plurality of slits (Figs. 7-9: recesses 74; The Examiner interprets the recesses (74) of Kurata as corresponding to the claimed slits because the recesses extend inwardly from the surface of the metal pillar (70), thereby forming recessed openings in the metal pillar), each of which comprises a cavity (internal spaces 77 and 80), and a recessed portion disposed adjacent to and interfacing a wiring and the metal pillar (wiring/electrode recess 81 having internal space 83 at the connection between rewiring layer 33 and post electrode 70, Figs. 7-9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the metal pillar (E2) of Kurokawa such that the plurality of slits are disposed apart from each other at preset intervals, as suggested by Kurata, in order to provide a plurality of recessed surface portions for improving adhesion between the metal pillar and surrounding resin material and preventing separation, as taught by Kurata (¶0191 and 0194).
Regarding claim 13, Kurokawa 773” discloses the semiconductor device of claim 11, as discussed above.
Kurokawa 773’ does not expressly disclose wherein the plurality of slits are disposed apart from each other at preset intervals.
However, Kurata teaches wherein the plurality of slits (electrode recesses 74) are disposed apart from each other (plurality of electrode recesses 74 formed at separate positions along the electrode lateral surface 73 of post electrode 70, Figs. 7 and 9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the metal pillar (E2) of Kurokawa such that the plurality of slits are disposed apart from each other at preset intervals, as suggested by Kurata, in order to provide a plurality of recessed surface portions for improving adhesion between the metal pillar and surrounding resin material and preventing separation, as taught by Kurata (¶0191 and 0194).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2019/0172773 to Kurokawa et al. (Kurokawa 773’) in view of US Pub # 2021/0407937 to Kurata and further in view of US Pub # 2020/0258980 to Carlson.
Regarding claim 14, Kurokawa 773” discloses the semiconductor device of claim 11, as discussed above (Figs. 2 and 7, ¶0112-0117).
Kurokawa 773” does not expressly disclose wherein air is filled within the plurality of slits to form an air layer.
Kurata teaches a metal pillar (post electrode 70) comprising a plurality of slits (electrode recesses 74), each of which comprises a cavity (internal spaces 77 and 80, Figs. 7-9), as discussed in the rejection of claim 1.
However, Kurokawa in view of Kurata does not expressly disclose wherein air is filled within the plurality of slits to form an air layer.
Carlson teaches a conductive pillar (255) comprising a hollow or empty portion (center region 258), wherein the hollow or empty portion is surrounded by a conductive channel (280M), thereby maintaining an electrically conductive path through the conductive pillar (Fig. 2D).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the plurality of slits (recesses 74) of Kurata, as applied to the metal pillar (E2) of Kurokawa, to retain air within the plurality of slits to form an air layer, in view of Carlson’s teaching of a hollow or empty portion (258) within a conductive pillar (255), in order to provide an internal empty region while maintaining an electrically conductive path through the metal pillar, as taught by Carlson (Fig. 2D and ¶0058-0059, 0079).
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2020/0235026 to Kurokawa et al. (Kurokawa 026’) in view of US Pub # 2021/0407937 to Kurata and further in view of US Pub # 2020/0258980 to Carlson.
Regarding independent claim 17, Kurokawa 026” discloses a semiconductor device (Fig. 1) comprising:
a collector electrode (Fig. 1: C0) disposed on a collector layer (31 and ¶0027);
a base electrode (B0) disposed on a base layer (33, Fig. 1, ¶0028); and
an emitter electrode (E0) disposed on an emitter layer (34, Fig. 1, ¶0028);
wherein an emitter junction wiring (E1) connected to the emitter electrode (E0 through first emitter cavities 51E, Fig. 1, ¶0032); and
wherein the metal pillar (E2) is disposed to contact the emitter junction wiring (E1 through second emitter cavities 54E, Fig. 1, ¶0034);
wherein the collector electrode (C0), the base electrode (B0), and the emitter electrode (E0) are disposed in a single transistor (60, Fig. 1, ¶0025-0028).
Kurokawa does not expressly disclose wherein a plurality of air cavities are disposed in the metal pillar adjacent to the emitter junction wiring, and interface the emitter junction wiring and the metal pillar.
However, Kurata teaches a metal pillar (post electrode 70) comprising a plurality of cavities (electrode recesses 74 having internal spaces 77 and 80), and a cavity disposed adjacent to and interfacing a wiring and the metal pillar (wiring/electrode recess 81 having internal space 83 at the interface between rewiring layer 33 and post electrode 70, Figs. 7-9).
Kurokawa in view of Kurata does not expressly disclose wherein a plurality of air cavities are disposed in the metal pillar adjacent to the emitter junction wiring, and interface the emitter junction wiring and the metal pillar.
However, Carlson teaches a conductive pillar (255) comprising a hollow or empty portion (258) surrounded by a conductive channel (280M), wherein the conductive channel provides an electrical current path through the conductive pillar (Fig. 2D, ¶0058-0059).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the metal pillar (E2) of Kurokawa, as modified by Kurata, to include a plurality of air cavities adjacent to the emitter junction wiring (E1) and interfacing the emitter junction wiring and the metal pillar, in view of Carlson’s teaching of a hollow or empty portion (258) within a conductive pillar (255), in order to provide hollow regions within the metal pillar while maintaining an electrically conductive path through the metal pillar, as taught by Carlson (Fig. 2D, ¶0058-0059).
Regarding claim 18, Kurokawa 026” in view of Kurata and Carlson further teaches wherein the metal pillar comprises a copper material (Kurata’s post electrode 70 comprising copper (Cu), Fig. 7, ¶0180) and it would have been obvious to one of ordinary skill in the art at the time of the invention to have selected copper for the undisclosed metal as mere selection of an art recognized metal suitable for the intended use of Kurokawa (MPEP §2144.07).
Regarding claim 19, Kurokawa discloses the semiconductor device of claim 17, as discussed above, including a collector layer (32, Fig. 1, ¶0027).
Kurata teaches a plurality of cavities (recesses 74 having internal spaces 77 and 80) in a metal pillar (post electrode 70), as discussed above.
Carlson teaches a hollow or empty portion (258) within a conductive pillar (255), as discussed above (Fig. 2D, ¶0058-0059).
However, Kurokawa in view of Kurata and Carlson does not expressly disclose wherein at least one of the air cavities is disposed to overlap the collector layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the metal pillar (E2) of Kurokawa, as modified by Kurata and Carlson, such that at least one of the air cavities is disposed to overlap the collector layer (32), in order to accommodate the air cavities within the metal pillar while maintaining an electrically conductive path through the metal pillar, as suggested by Carlson (Fig. 2D, ¶0058-0059).
Regarding claim 20, Kurokawa discloses the semiconductor device of claim 17, as discussed above, including an emitter layer (34, Fig. 1, ¶0028).
Kurata teaches a plurality of cavities (recesses 74 having internal spaces 77 and 80) in a metal pillar (post electrode 70), as discussed above.
Carlson teaches a hollow or empty portion (258) within a conductive pillar (255), as discussed above (Fig. 2D, ¶0058-0059).
However, Kurokawa in view of Kurata and Carlson does not expressly disclose wherein the plurality of air cavities are disposed in a non-overlapping manner with regard to the emitter layer.
Kurokawa further teaches that the positional relationship between cavities (57) and operating regions (61), which substantially correspond to emitter layers (34), affects the thermal resistance of heat-transfer paths (59) (Fig. 1, ¶0038-0040).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the metal pillar (E2) of Kurokawa, as modified by Kurata and Carlson, such that the plurality of air cavities are disposed in a non-overlapping manner with regard to the emitter layer (34), in order to adjust the thermal resistance of the heat-transfer paths associated with the emitter layers and reduce temperature variations among the unit transistors, in view of Kurokawa’s teaching regarding the positional relationship between the cavities and operating regions (Fig. 1, ¶0038-0040).
Allowable Subject Matter
Claims 5-8 and 15-16 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 5 and 15 recites:
‘wherein, when viewed in a plan view, at least a first portion of the plurality of slits is disposed at a position which overlaps the collector electrode of the semiconductor substrate.”
Claims 8 and 16 recites:
“wherein a thickness of each of the plurality of slits is thinner than a thickness of the metal pillar in a thickness direction of the semiconductor substrate.
The considered prior art of record appears to fail to teach or render obvious the instant limitation in combination with all of the limitations of the independent claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pat # 6,667,489 to Suzumura et al., US Pat # 8,338,833 to Seki et al., US Pub # 2008/0088020 to Miyajima et al., US Pat # 6,852,580 to Yanagihara et al.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHSEN AHMADI whose telephone number is (571)272-5062. The examiner can normally be reached M-F: 9:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William F Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHSEN AHMADI/Primary Examiner, Art Unit 2896
