Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/391,914 filed on 12/21/2023.
Election/Restrictions
Applicant’s election with traverse of Group I (claims 1-16) in the reply filed on 05/08/2026 is acknowledged. Upon reconsideration of Applicant’s traversal and the pending claims, the traversal is persuasive. The prior restriction requirement is hereby withdrawn, and Groups I and II are rejoined and examined on the merits in the present Office action.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 16 recites “each of the plurality of unit transistors comprising” followed by recitation of “an emitter junction wiring” and “a metal pillar”. In other words, the way “emitter junction wiring” and “metal pillar” are recited subsequent to the “each of the plurality of unit transistors comprising” leads to an interpretation of the claim in which each unit transistor has a emitter junction wiring and metal pillar. Or in short, the claim could be misinterpreted as requiring a plurality of emitter junction wirings and a plurality of metal pillars, one for each unit transistor.
MPEP 2173.02(II) instructs examiners to determine definiteness, not in a vacuum, but in light of: (A) applicant’s originally filed disclosure; (B) the prior art; and (C) the interpretation as would be understood by persons skilled in the relevant art. Applicant’s originally filed disclosure is highly relevant, and often dispositive, to understanding claim language. MPEP 2111.01(I).
Applicant’s originally filed Figure 4 illustrates two transistors 101 and102 that correspond to the claimed “unit transistors.” Figure 4 also illustrates one emitter junction wiring 133 common to both unit transistors 101 and 102. Figure 4 also illustrates one metal pillar 118 common to both unit transistors 101 and 102. As is illustrated, there are not a plurality of emitter junction wirings and not a plurality of metal pillars, one for each unit transistor. Instead, the emitter junction wiring and metal pillar are common to both unit transistors.
As such, for purposes of compact prosecution, claims 1 and 11 will be interpreted as is illustrated in Figure 4, where there is one emitter junction wiring common to the plurality of unit transistors and one metal pillar common to the plurality of unit transistors. MPEP 2173.06(II).
As helpful guidance, an exemplary suggested correction is presented below; however, applicant is invited to make alternate corrections that make clear that the emitter junction wiring and metal pillar are singular for a plurality of unit transistors.
(Currently Amended) A semiconductor device, comprising:
an emitter junction wiring;
a metal pillar;
a plurality of unit transistors, each of which is disposed on a semiconductor substrate, each of the plurality of unit transistors comprising:
a collector electrode configured to output an output signal;
a base electrode configured to receive an input signal;
an emitter electrode; and
wherein the
wherein the
wherein the metal pillar comprises a plurality of slits each of which comprises a cavity.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 9-10, 17 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pub # 2020/0235026 to Kurokawa et al. (Kurokawa).
Regarding independent claim 1, Kurokawa 026” discloses a semiconductor device (Fig. 1), comprising:
a plurality of unit transistors (Fig. 1: 60), each of which is disposed on a semiconductor substrate (30), each of the plurality of unit transistors (60) comprising:
a collector electrode (C0 and ¶0027) configured to output an output signal;
a base electrode (B0 and ¶0028) configured to receive an input signal;
an emitter electrode (E0 and ¶0028);
an emitter junction wiring (E1 and ¶0032) configured to interconnect the emitter electrodes (E0) of the plurality of unit transistors (60); and
a metal pillar (E2 and ¶0034, Under the broadest reasonable interpretation consistent with the specification, the Examiner construes disclosed a second-layer emitter wiring as the claimed a metal pillar), disposed to form an interface with the emitter junction wiring (E1), and disposed to be in contact with the emitter junction wiring (see Fig. 1: E1 directly contacts E2),
wherein the metal pillar (E2) comprises a plurality of slits each of which comprises a cavity (¶0036). ¶0036 explicitly discloses “cavities 57 are located within the second-layer emitter wiring E2 as viewed from above”).
Regarding claim 2, Kurokawa 026” discloses wherein the plurality of slits (or cavity) are disposed adjacent to the emitter junction wiring (E1), and interfaces the emitter junction wiring (E1) and the metal pillar (E2). It is noted that Kurokawa explicitly discloses in ¶0036 that slits or “cavities 57 are located within the second-layer emitter wiring E2 as viewed from above”, so since the second-layer emitter wiring E2 is disposed on the emitter junction wiring (E1), therefore, the plurality of slits (or cavity) are disposed adjacent to the emitter junction wiring (E1), and interfaces the emitter junction wiring (E1) and the metal pillar (E2).
Regarding claim 3, Kurokawa 026” discloses wherein the plurality of slits (or cavity 57) are disposed apart (see Examiner’s Mark-up below) from each other at preset intervals.
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Regarding claim 4, Kurokawa 026” discloses wherein air is filled within the plurality of slits to form an air layer (Fig. 2). Kurokawa 026” teaches an air layer corresponding to cavity 57 formed within the structure. Examiner considers cavity 57 to constitute the claimed air layer because cavity 57 is a void region bounded by surrounding structural layers and would necessarily contain air or another gas after formation.
Regarding claim 9, Kurokawa 026” discloses wherein each of the plurality of unit transistors (60) is a bipolar transistor (¶0026) that comprises:
a collector layer (Fig. 1: 31 and ¶0027) disposed in an area where the collector electrode (C0) is disposed,
a base layer (Fig. 1: 33 and ¶0027) disposed in an area where the base electrode (B0) is disposed, and
an emitter layer (Fig. 1: 34 and ¶0027) disposed in an area where the emitter electrode (E0) is disposed.
Regarding claim 10, Kurokawa 026” discloses wherein the emitter junction wiring (E1) comprises a gold (Au) material (¶0032).
Regarding independent claim 17, Kurokawa 026” discloses a semiconductor device (Fig. 1), comprising:
a collector electrode (Fig. 1: C0) disposed on a collector layer (31 and ¶0027);
a base electrode (B0) disposed on a base layer (33);
an emitter electrode (E0) disposed on an emitter layer (34);
an emitter junction wiring (E1) connected to the emitter electrode (E0); and
a metal pillar (E2), disposed to contact the emitter junction wiring (E1),
wherein the collector electrode (C0), the base electrode (B0), and the emitter electrode (E0) are disposed in a single transistor (60), and
wherein a plurality of air cavities (¶0036) are disposed in the metal pillar (see ¶0036; E2) between the emitter layer (34) and the metal pillar (E2). It is noted that Kurokawa explicitly discloses in ¶0036 that “cavities 57 are located within the second-layer emitter wiring E2 as viewed from above”, therefore, the air cavities (¶0036) are disposed in the metal pillar (see ¶0036; E2) between the emitter layer (34) and the metal pillar (E2).
Regarding claim 19, Kurokawa 026” discloses wherein at least one of the air cavities (Fig. 1: 57) is disposed to overlap the collector layer (Fig. 1: 31).
Regarding claim 20, Kurokawa 026” discloses wherein the plurality of air cavities (Fig. 1: 57) are disposed in a non-overlapping manner with regard to the emitter layer (Fig. 1: 34). Specifically, it is noted that Kurokawa 026” teaches air cavities 57 that are disposed in a non-overlapping manner with respect to emitter layer 34 (including emitter layers 34A and 34B), as shown in Fig. 1, where cavities 57 are laterally displaced from the emitter layer and do not overlap the emitter layer in the illustrated cross-sectional arrangement.
Examiner interprets the recited “non-overlapping manner” as referring to the illustrated cross-sectional direction, in which cavities 57 are positioned such that they do not overlap emitter layer 34.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 11-14 rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2019/0172773 to Kurokawa et al. (Kurokawa) in view of US Pub # 2002/0171138 to Osone et al. (Osone).
Regarding independent claim 11, Kurokawa 773” discloses a power amplifier (Fig. 7 and ¶0112-0117) that amplifies a radio frequency (RF) input signal and outputs an RF output signal, the power amplifier comprising:
Kurokawa discloses a plurality of unit transistors (Fig. 2: 60), each of which is disposed on a semiconductor substrate (30), each of the plurality of unit transistors (60) comprising:
a collector electrode (C0 and ¶0051) configured to output an output signal;
a base electrode (B0 and ¶00518) configured to receive an input signal;
an emitter electrode (E0 and ¶00518);
an emitter junction wiring (E1 and ¶0054) configured to interconnect the emitter electrodes (E0) of the plurality of unit transistors (60); and
a metal pillar (E2 and ¶0054, Under the broadest reasonable interpretation consistent with the specification, the Examiner construes disclosed a second-layer emitter wiring as the claimed a metal pillar), disposed to form an interface with the emitter junction wiring (E1), and disposed to be in contact with the emitter junction wiring (see Fig. 2: E1 directly contacts E2),
wherein the metal pillar (E2) comprises a plurality of slits each of which comprises a cavity (¶0066). ¶0066 explicitly discloses “the plural cavities 45 are located within the second-layer emitter wiring E2, as viewed from above”).
Kurokawa fails to explicitly disclose a circuit board on which the plurality of unit transistors are mounted.
Osone teaches a circuit board (¶0044 explicitly discloses a mother board from a back side of the multilayer wiring board 3) on which the plurality of unit transistors (Fig. 1: 1 and ¶0042 and ¶0052) are mounted. (It should be noted that Osone teaches a multilayer wiring board. A multilayer wiring board is a type of circuit board that includes conductive wiring arranged on or within a substrate to provide electrical interconnection. Therefore, the disclosed multilayer wiring board satisfies the claimed circuit board limitation.)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the semiconductor device of Kurokawa with the mother board or multilayer wiring board as taught by Osone to ensured the thermal connection therebetween and to reduce thermal resistance between heating areas in the semiconductor device 1 and the back side of the wiring board (¶0044).
Regarding claim 12, Kurokawa 773” discloses wherein the plurality of slits (or cavity) are disposed adjacent to the emitter junction wiring (E1), and interfaces the emitter junction wiring (E1) and the metal pillar (E2). It is noted that Kurokawa explicitly discloses in ¶0066 that slits or “cavities 45 are located within the second-layer emitter wiring E2, as viewed from above”, so since the second-layer emitter wiring E2 is disposed on the emitter junction wiring (E1), therefore, the plurality of slits (or cavity) are disposed adjacent to the emitter junction wiring (E1), and interfaces the emitter junction wiring (E1) and the metal pillar (E2).
Regarding claim 13, Kurokawa 773” discloses wherein the plurality of slits (or cavity 45) are disposed apart (see Examiner’s Mark-up below) from each other at preset intervals.
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Regarding claim 14, Kurokawa 773” discloses wherein air is filled within the plurality of slits to form an air layer (Fig. 2). Kurokawa 0066” teaches an air layer corresponding to cavity 45 formed within the structure. Examiner considers cavity 45 to constitute the claimed air layer because cavity 45 is a void region bounded by surrounding structural layers and would necessarily contain air or another gas after formation.
Claim 18 rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2020/0235026 to Kurokawa et al. (Kurokawa) in view of US Pub # 2019/0198464 to Tsutsui et al. (Tsutsui)
Regarding claim 18, Kurokawa 026” disclose all of the limitations of claim 17 from which this claim depends.
Kurokawa 026” fails to explicitly discloses wherein the metal pillar comprises a copper material.
Tsutsui discloses wherein the metal pillar (Fig. 4: 33) comprises a copper material (¶0073).
Kurokawa 026” is silent as to the metal selected to act as the metal pillar E2 such that one of ordinary skill in the art would be motivated to seek exemplary metals known in the art. Tsutsui teaches it was known in the art to use copper pillar bump (¶0073 and Fig. 4) for grounding the emitter of each of the plurality of unit transistors (¶0055) and it would have been obvious to one of ordinary skill in the art at the time of the invention to have selected copper for the undisclosed metal as mere selection of an art recognized metal suitable for the intended use of Kim (MPEP §2144.07).
Allowable Subject Matter
Claims 5-8 and 15-16 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b), set forth in this Office action, and to include all of the limitations of the base claim and any intervening claims.
Claims 5 and 15 recites:
‘wherein, when viewed in a plan view, at least a first portion of the plurality of slits is disposed at a position which overlaps the collector electrode of the semiconductor substrate.”
Claims 8 and 16 recites:
“wherein a thickness of each of the plurality of slits is thinner than a thickness of the metal pillar in a thickness direction of the semiconductor substrate.
The considered prior art of record appears to fail to teach or render obvious the instant limitation in combination with all of the limitations of the independent claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pat # 6,667,489 to Suzumura et al., US Pat # 8,338,833 to Seki et al., US Pub # 2008/0088020 to Miyajima et al., US Pat # 6,852,580 to Yanagihara et al.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William F Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHSEN AHMADI/ Primary Examiner, Art Unit 2896
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