DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-10 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding Applicant’s argument (on page 6) with respect to claim 3; since the claim does not differentiate that the coating is materially different from a layer underneath the coating, the copper (a metal) pads of Martinis anticipates that “metallic coating” of claim 3.
Regarding Applicant’s argument (on page 7) with respect to claim 4 that a §102 rejection must rest on a single reference; Martinis anticipates the limitations of claim 4 in single reference because Martinis discloses that the interconnect pads are made of copper (“the interconnect pads 602 can be material such as copper to provide improved interfacing with the superconducting ground layer(s) 402 and/or superconducting signal line(s) 406” [0104]). Copper necessarily reduces outgassing from the flex ion trap interconnect at pressures below a pressure of 10-12 torr because copper does not outgas at any pressure. Such an assertion is evidenced by the teaching of Rand et al. U.S. PGPUB No. 2003/0230731, which teaches that “copper… does not outgas” [0031]). Therefore, the copper material of Martinis necessarily anticipates the limitations of claim 4.
Regarding Applicant’s argument (on page 7), with respect to claim 9, that the classical processors 302 is not a “package” as recited by the claim; Applicant recites examples from the specification of various embodiments of the claimed package. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The term “package” has been given its broadest reasonable interpretation and cannot be interpreted as limited merely to the cited examples, and the fact that Applicant cites examples implies that the “package” is not limited to such an interpretation but may include other elements as well.
Regarding Applicant’s argument (on page 8) with respect to claim 10, that Martinis does not disclose a single flex interconnect bearing a connector at the ion trap and a connector at the package, as recited by claim 10; a single flex interconnect 334 bears a connector 316 at the ion trap 304 and a connector 312 at the package 302.
Applicant contends (on page 8) that the Office Action’s mapping is internally inconsistent as element 316 is relied upon as a connector on a first sidewall for claim 8, yet as the connector to the ion trap for claim 10. First, claim 10 has separate dependency from claim 8 (claim 10 does not include the limitations of claim 8 and claim 8 does not include the limitations of claim 10). Second, element 316 is both a connector on a first sidewall and a connector to the ion trap. Since the claims are not dependent on one another, and do not include the limitations of the other claim, there is no claim recitation that the connector on a first sidewall (of claim 8) must be a separate element from the connector to the ion trap (of claim 10).
Regarding Applicant’s argument (on page 8) with respect to claim 12, that the cap 307 of Martinis is not a sidewall; a cap is indistinguishable from a sidewall, as claimed, and Applicant has not shown that the claimed sidewall has any specific limitations in the claim which differentiate it from a cap, which forms a wall in a side of a device. Similarly, Applicant asserts that flex circuit board 314 is not a connector on a sidewall, yet applicant has not shown claim recitations which distinguish the flex circuit board 314 from the claimed connector, as the flex circuit board provides connection and is located on the cap 307, which is a sidewall.
Regarding Applicant’s arguments with respect to claims 7, 11, 13, and 14; Applicant does not provide additional arguments with respect to these claims and no additional response is necessary.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 3, 4, 5, 6, 8, 9, 10, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Martinis et al. U.S. PGPUB No. 2022/0083893 in view of Deen et al. U.S. PGPUB No. 2022/0037313.
Regarding claim 1, Martinis discloses a quantum computing system (“quantum computers that are… interconnected by a digital and/or quantum data communication network” [0150]) comprising: a vacuum chamber (“The quantum computing system can include a vacuum chamber configured to receive the chamber mount and dispose the quantum hardware in a vacuum” [Abstract]); an ion trap (“Digital and/or quantum computer-readable media suitable for storing digital and/or quantum computer program instructions and digital and/or quantum data include all forms of non-volatile digital and/or quantum memory, media and memory devices, including by way of example… quantum systems, e.g., trapped atoms or electrons” [0155] – “By way of example, such systems can include atoms, electrons, photons, ions or superconducting qubits” [0147]), wherein the ion trap is inside the vacuum chamber (“The quantum computing system can include a vacuum chamber configured to receive the chamber mount and dispose the quantum hardware in a vacuum” [0005]); and a flex ion trap interconnect electrically coupled to at least a first side of the ion trap (“The quantum computing system can include at least one first flex circuit board coupled to the one or more classical processors by a classical-flex interconnect” [0007]), wherein the flex ion trap interconnect is configured to electrically transmit one or more signals to or from the ion trap (“The classical-flex interconnect can convert from a classical signal transmission medium (e.g., a coaxial cable) to the first flex circuit board(s)” [0040] – where paragraph [0155] identifies that the computer system to which the flex interconnect is connected is an ion trap quantum computer system). However, Martinis does not disclose a package, wherein the ion trap is electrically connected to the package by at least one through-silicon via (TSV).
Deen discloses a quantum computing system (“A switchable roll-off for trapped ion quantum computing applications” [0057]) comprising: a package (“metal-semiconductor field effect transistors (MOSFETs)” [0055]), wherein an ion trap is electrically connected to the package by at least one through-silicon via (TSV) (“metal-semiconductor field effect transistors (MOSFETs) may be integrated with ion trap apparatuses during surface trap fabrication. Such switches may be configured in either a conventional lateral architecture or by means of a through-silicon-via-field effect transistor (TSV-FET) structure” [0055]).
It would have been obvious to one possessing ordinary skill in the art before the effective filing date of the claimed invention to have modified Martinis by connecting the ion trap to a MOSFET package by a TSV, as discussed in Deen, in order to provide a switching control mechanism for controlling potentials applied to an ion trap so as to control movement of charged particles in the ion trap.
Regarding claim 2, Martinis discloses that the vacuum chamber (“The quantum computing system can include a vacuum chamber configured to receive the chamber mount and dispose the quantum hardware in a vacuum” [0005]) is a cryogenic vacuum chamber (“any other suitable components of quantum hardware 102 discussed with regard to FIG. 1, can be located within cryogenic cooling system 130” [0067]).
Regarding claim 3, Martinis discloses that the flex ion trap interconnect is coated with a metallic coating (“the interconnect pads 602 can be material such as copper to provide improved interfacing with the superconducting ground layer(s) 402 and/or superconducting signal line(s) 406” [0104]).
Regarding claim 4, Martinis discloses that the metallic coating is configured to reduce outgassing from the flex ion trap interconnect at pressures below a pressure of 10-12 Torr.
Martinis discloses that “the interconnect pads 602 can be material such as copper to provide improved interfacing with the superconducting ground layer(s) 402 and/or superconducting signal line(s) 406” [0104], and Rand et al. U.S. PGPUB No. 2003/0230731 teaches that “copper… does not outgas” [0031].
Regarding claim 5, Martinis discloses that the flex ion trap interconnect comprises a plurality of conductors (either end of the interconnect) and one or more electrical components (a flex circuit board on one end, and classical processor(s) on the other side) connected to one or more of the plurality of conductors (“the classical processor(s) can be coupled to the first flex circuit board(s) by a classical-flex interconnect” [0040]).
Regarding claim 6, Martinis discloses that the flex ion trap interconnect comprises a plurality of layers 402 and 406, and wherein each layer is comprised of at least one conductor (“adhesion layers (not illustrated) can be included between the interconnect pads 602 and the conductive material (e.g., the ground layer(s) 402 and/or the signal line(s) 406)” [0104]).
Regarding claim 8, Martinis discloses that the flex ion trap interconnect 334 is further electrically coupled to a connector 316 on a first sidewall 308 of the cryogenic vacuum chamber (as illustrated in figure 3 – “a vacuum chamber configured to receive the chamber mount 308 and dispose the quantum hardware 304 in a vacuum” [0070]).
Regarding claim 9, Martinis discloses a package 302, wherein the ion trap 304 (“Digital and/or quantum computer-readable media suitable for storing digital and/or quantum computer program instructions and digital and/or quantum data include all forms of non-volatile digital and/or quantum memory, media and memory devices, including by way of example… quantum systems, e.g., trapped atoms or electrons” [0155] – “By way of example, such systems can include atoms, electrons, photons, ions or superconducting qubits” [0147]) is electrically connected to the package 302 by one or more electrical connections including a first electrical connection 334 (as illustrated in figure 3).
Regarding claim 10, Martinis discloses that the first electrical connection of the package and the ion trap is via the flex ion trap interconnect 334, wherein the flex ion trap interconnect 334 is electrically coupled to the ion trap 304 with a first connector 316 and to the package 302 with a second connector 312 (as illustrated in figure 3).
Regarding claim 12, Martinis discloses that the flex ion trap interconnect 334 is further electrically coupled to a sidewall 307 with a third connector 314 (as illustrated in figure 3).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Martinis et al. U.S. PGPUB No. 2022/0083893 in view of Deen et al. U.S. PGPUB No. 2022/0037313 in view of Folman et al. U.S. PGPUB No. 20090321719.
Regarding claim 7, Martinis discloses a quantum computing system comprising an ion trap (“Digital and/or quantum computer-readable media suitable for storing digital and/or quantum computer program instructions and digital and/or quantum data include all forms of non-volatile digital and/or quantum memory, media and memory devices, including by way of example… quantum systems, e.g., trapped atoms or electrons” [0155] – “By way of example, such systems can include atoms, electrons, photons, ions or superconducting qubits” [0147]), but does not disclose that the ion trap is comprised of sapphire.
Folman discloses a quantum computing system (“A specific example of this is the contribution of the ion trap to quantum computing” [0005]) comprising an ion trap comprised of sapphire (“An integrated ion chip for a large scale quantum device of interconnected ion (or other charged particles) traps each holding a small number of particles for a finite period of time, in a preferred embodiment using sapphire as the substrate” [Abstract]).
It would have been obvious to one possessing ordinary skill in the art before the effective filing date of the claimed invention to have modified Martinis with the sapphire ion trap of Folman in order to utilize a particular substrate on which an ion trap may be formed, selecting the material of the substrate to provide suitable support for forming the ion trap while remaining electrically insulated from voltages applied to the ion trap.
Claim(s) 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Martinis et al. U.S. PGPUB No. 2022/0083893 in view of Deen et al. U.S. PGPUB No. 2022/0037313 in view of Koduri et al. U.S. PGPUB No. 2022/0109091.
Regarding claim 13, Martinis discloses the claimed invention except that while Martinis discloses a flexible interconnect (“The quantum computing system can include at least one first flex circuit board coupled to the one or more classical processors by a classical-flex interconnect” [0007]), there is no disclosure of a first, second, or third plurality of terminals.
Koduri discloses a flex interconnect 410 (“a flexible interconnect is mounted to the first chip” [0071]) further comprising a first connector comprising a first plurality of electrical terminals 440 at a first end (as illustrated in figure 4); and a second connector 450 comprising a second plurality of electrical terminals at a second end (as illustrated in figure 4); and a third connector comprising a third plurality of electrical terminals 460 located between the first connector and the second connector (as illustrated in figure 4).
It would have been obvious to one possessing ordinary skill in the art before the effective filing date of the claimed invention to have modified Martinis with the electrical terminals of Koduri in order to provide additional electrical signals through a single interconnect, thereby saving space for transmitting a plurality of electrical signals to an electrical device.
Regarding claim 14, Martinis discloses the claimed invention except that while Martinis discloses a flexible interconnect (“The quantum computing system can include at least one first flex circuit board coupled to the one or more classical processors by a classical-flex interconnect” [0007]), there is no disclosure of a first, second, or third plurality of terminals.
Koduri discloses a flex interconnect 410 (“a flexible interconnect is mounted to the first chip” [0071]) further comprising a first connector comprising a first plurality of electrical terminals 440 at a first end (as illustrated in figure 4); and a second connector 450 comprising a second plurality of electrical terminals at a second end (as illustrated in figure 4); and a third connector comprising a third plurality of electrical terminals 460 located between the first connector and the second connector (as illustrated in figure 4).
It would have been obvious to one possessing ordinary skill in the art before the effective filing date of the claimed invention to have modified Martinis with the electrical terminals of Koduri in order to provide additional electrical signals through a single interconnect, thereby saving space for transmitting a plurality of electrical signals to an electrical device.
Allowable Subject Matter
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 11; Martinis et al. U.S. PGPUB No. 2022/0083893 discloses a quantum computing system (“quantum computers that are… interconnected by a digital and/or quantum data communication network” [0150]) comprising: a vacuum chamber (“The quantum computing system can include a vacuum chamber configured to receive the chamber mount and dispose the quantum hardware in a vacuum” [Abstract]); an ion trap (“Digital and/or quantum computer-readable media suitable for storing digital and/or quantum computer program instructions and digital and/or quantum data include all forms of non-volatile digital and/or quantum memory, media and memory devices, including by way of example… quantum systems, e.g., trapped atoms or electrons” [0155] – “By way of example, such systems can include atoms, electrons, photons, ions or superconducting qubits” [0147]), wherein the ion trap is inside the vacuum chamber (“The quantum computing system can include a vacuum chamber configured to receive the chamber mount and dispose the quantum hardware in a vacuum” [0005]); and a flex ion trap interconnect electrically coupled to at least a first side of the ion trap (“The quantum computing system can include at least one first flex circuit board coupled to the one or more classical processors by a classical-flex interconnect” [0007]), wherein the flex ion trap interconnect is configured to electrically transmit one or more signals to or from the ion trap (“The classical-flex interconnect can convert from a classical signal transmission medium (e.g., a coaxial cable) to the first flex circuit board(s)” [0040] – where paragraph [0155] identifies that the computer system to which the flex interconnect is connected is an ion trap quantum computer system). However, there is no explicit disclosure that one or more electrical connections include a second electrical connection of the ion trap to a package including at least one TSV and associated bond bump.
The prior art fails to teach or reasonably suggest, in combination with the other claim limitations, a quantum computing system comprising: a package, wherein an ion trap is electrically connected to the package by one or more electrical connections including a first electrical connection via a flex ion trap interconnect; wherein a second electrical connection of the ion trap to the package includes at least one TSV and associated bond bump.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON L MCCORMACK whose telephone number is (571)270-1489. The examiner can normally be reached M-Th 7:00AM-5:00PM EST.
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/JASON L MCCORMACK/Examiner, Art Unit 2881
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